CN106405313A - Pseudo soldering test device and method for chip - Google Patents
Pseudo soldering test device and method for chip Download PDFInfo
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- CN106405313A CN106405313A CN201611042255.XA CN201611042255A CN106405313A CN 106405313 A CN106405313 A CN 106405313A CN 201611042255 A CN201611042255 A CN 201611042255A CN 106405313 A CN106405313 A CN 106405313A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/66—Testing of connections, e.g. of plugs or non-disconnectable joints
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- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The invention discloses a pseudo soldering test device and method for a chip. The pseudo soldering test device comprises an MCU, a computer, a protection circuit and test slot, and is characterized in that the chip is installed in the test slot; the protection circuit is used for detecting whether the chip is correctly installed in the test slot or not; and the MCU is used for detecting pins of the chip when the protection circuit detects that the chip is correctly installed in the test slot and sending a detection result to the computer. The pseudo soldering test device and method for the chip can realize automatic detection for the chip soldering state, a peripheral function is not required to be developed, the cost is saved, and the pseudo soldering test efficiency and the qualified rate of the chip are improved.
Description
Technical field
The present invention relates to communication test field, the rosin joint test device particularly to a kind of chip and method of testing.
Background technology
In the production of existing factory module sticker such as chip, chip is welded to the detection of situation, substantially do not have
Clearly method of testing.Because chip pin is numerous, the method for traditional test module is to adopt functional test.First enter for module
Row peripheral functionality (such as compass, gravity sensor etc.) software development, by manually judging, whether arbitration functions are normal.Thus
Whether judge module welding is normal.This scheme has some shortcoming：1) develop peripheral functionality, need to increase time cost；2) corresponding
Whether function is normal, needs manually to judge, efficiency will not be too high, and reliability is also bad；3) pin of intelligent object is numerous, work(
Can be complicated, the conventionally employed method manually carrying out test function can wrong survey, the situation generation of test leakage, can exist not when leading to dispatch from the factory
Qualified phenomenon, there is serious defect in the quality of product.
Content of the invention
The technical problem to be solved in the present invention is to overcome the detection welding situation for chip in prior art to adopt
Detected and led to by artificial judgment the low defect with high cost of detection efficiency with the peripheral functionality of exploitation, there is provided one
Plant welding test device and the method for testing of chip.
A kind of rosin joint test device of chip, including MCU (Microcontroller Unit, micro-control unit), calculates
Machine, protection circuit and test trough, described chip is installed in test trough；
Described protection circuit is used for detecting whether described chip is correctly installed in described test trough；
Described MCU is used for when described protection circuit detects described chip and is correctly installed on described test trough, to described
The pin of chip is detected, and testing result is sent to described computer.
It is preferred that described chip includes GPIO (General Purpose Input Output, universal input/output) drawing
Foot, LDO (low dropout regulator, low pressure difference linear voltage regulator) pin and ADC (Analog-to-Digital
Converter, analog-digital converter) pin；
Described MCU is used for successively described GPIO pin, LDO pin and ADC pin being detected.
It is preferred that described chip includes multiple GPIO pin；
Described MCU is used for carrying out when current GPIO pin is detected for high level to next GPIO pin or LDO pin
Detection.
It is preferred that described rosin joint test device also includes multiway analog switch, described chip includes multiple LDO pins, institute
State multiple LDO pins to electrically connect with the ADC pin of described MCU by described multiway analog switch；
Described multiway analog switch is used for by switching the multiple described LDO pins successively ADC pin with described MCU
Connection.
It is preferred that described rosin joint test device also includes first resistor and second resistance, described first resistor is series at institute
State between multiway analog switch and the ADC pin of described MCU, the ADC pin of one end of described second resistance and described MCU and institute
State the connection end electrical connection of first resistor, the other end of described second resistance is electrically connected with described earth terminal.
It is preferred that described rosin joint test device also includes the first feeder ear, 3rd resistor and the 4th resistance, described first confession
Electric end, described 3rd resistor, described 4th resistance, earth terminal are sequentially connected in series；
The ADC pin of described chip is electrically connected with the connection end of described 3rd resistor and described 4th resistance.
It is preferred that described rosin joint test device includes the 5th resistance and the 6th resistance, the first pin of described 5th resistance,
First pin of described 6th resistance is electrically connected with the second feeder ear respectively, the second pin of described 5th resistance, the described 6th
The second pin of resistance is electrically connected with described MCU respectively；
Described test trough is provided with the first metal thimble and the second metal thimble, the second pin of described 5th resistance also with
Described first metal thimble connects, and the second pin of described 6th resistance is connected with described second metal thimble.
It is preferred that described protection circuit includes audion, the 7th resistance, the 8th resistance, the first electric capacity and metal-oxide-semiconductor, described
The base electrode of audion is electrically connected with the enable pin of described MCU, and the emitter stage of described audion is connected with earth terminal, and described three
The colelctor electrode of pole pipe is connected with the first pin of described 7th resistance, the second pin of described 7th resistance and described MOS
(Metal Oxide Semiconductor, metal-oxide semiconductor (MOS)) pipe grid electrical connection, the drain electrode of described metal-oxide-semiconductor with
Second feeder ear electrical connection, the source electrode of described metal-oxide-semiconductor electrically connected with the power pins of described test trough, and the of described 8th resistance
One pin is electrically connected with the drain electrode of described metal-oxide-semiconductor, and the second pin of described 8th resistance is electrically connected with the colelctor electrode of described audion
Connect, the first pin of described first electric capacity is electrically connected with the colelctor electrode of described audion, the second pin of described first electric capacity with
The grid electrical connection of described metal-oxide-semiconductor.
It is preferred that described protection circuit also includes the second electric capacity and the 3rd electric capacity, the first pin of described second electric capacity, institute
The first pin stating the 3rd electric capacity is all electrically connected with described second feeder ear, the second pin of described second electric capacity, the described 3rd
The second pin of electric capacity is all electrically connected with earth terminal.
It is preferred that when described chip is correctly installed in described test trough, described first metal thimble and described chip
The first grounding pin electrical connection, described second metal thimble electrically connected with the second grounding pin of described chip, described test
The power pins of groove are electrically connected with the power pins of described chip.
A kind of rosin joint method of testing of chip, is realized using described rosin joint test device, and methods described includes following step
Suddenly：
S1, described protection circuit detect whether described chip is in and are correctly installed in described test trough, if so, enter
S2, if it is not, then terminate；
S2, described MCU detect to the pin of described chip, and testing result is sent to described computer.
It is preferred that described chip includes GPIO pin, LDO pin and ADC pin；
In step s 2, described MCU detects to described GPIO pin, LDO pin and ADC pin successively.
It is preferred that described chip includes multiple GPIO pin；
In step s 2, described MCU carry out when current GPIO pin is detected for high level to next GPIO pin or
The detection of LDO pin.
On the basis of meeting common sense in the field, above-mentioned each optimum condition, can combination in any, obtain final product each preferable reality of the present invention
Example.
The positive effect of the present invention is：The rosin joint test device of the chip of the present invention and method of testing can be realized
Automatic detection to chip welded condition, need not develop peripheral functionality, save cost, improve rosin joint testing efficiency and chip
Qualification rate.
Brief description
Fig. 1 is the attachment structure schematic diagram with chip for the rosin joint test device of a preferred embodiment of the present invention.
Fig. 2 is the access node that is electrically connected with chip and MCU for the protection circuit of rosin joint test device of a preferred embodiment of the present invention
Structure schematic diagram.
Fig. 3 is the flow chart of the rosin joint method of testing of chip of a preferred embodiment of the present invention.
Specific embodiment
Further illustrate the present invention below by the mode of embodiment, but therefore do not limit the present invention to described reality
Apply among a scope.
As depicted in figs. 1 and 2, the rosin joint test device of a kind of chip, including MCU 1, computer 2, protection circuit 3 and survey
Experimental tank 7, described chip 6 is installed in described test trough 7, and described protection circuit 3 is used for detecting whether described chip 6 is correctly installed
In described test trough 7, described MCU is correctly installed on described test trough for described chip 6 is detected in described protection circuit 3
When 7, the pin of described chip 6 is detected, and testing result is sent to described computer 2.Described chip 6, described MCU
All by asynchronous serial communication mouth and described computer 2 connection communication.
Described chip 6 includes multiple GPIO pin, multiple LDO pin and ADC pin, and described MCU is used for successively to described
GPIO pin, LDO pin and ADC pin are detected.When being detected successively to multiple GPIO pin, described MCU is used for
Carry out the detection to next GPIO pin or LDO pin when current GPIO pin is detected for high level.
When described current GPIO pin is not last GPIO pin, described MCU is detecting described current GPIO
Pin be high level when upper once detect when next GPIO pin is detected；When described current GPIO pin is last
During individual GPIO pin, described MCU detect described current GPIO pin be high level when, upper once detect when LDO is drawn
Foot is detected.
This rosin joint test device also includes multiway analog switch 4, first resistor 401, second resistance 402, the plurality of LDO
Pin is electrically connected with the ADC pin of described MCU by described multiway analog switch 4.Described first resistor 401 is series at described many
Between the ADC pin of path analoging switch 4 and described MCU, one end of described second resistance 402 and the ADC pin of described MCU and institute
State the connection end electrical connection of first resistor 401, the other end of described second resistance 402 is electrically connected with described earth terminal 403.Described
Multiway analog switch 4 is used for connecting multiple described LDO pins successively with the ADC pin of described MCU by switching, described
MCU is used for gathering and detect the voltage of each described LDO pin successively.
Described rosin joint test device also includes the first feeder ear 501,3rd resistor 502 and the 4th resistance 503, and described first
Feeder ear 501, described 3rd resistor 502, described 4th resistance 503, earth terminal 403 are sequentially connected in series, and the ADC of described chip 6 draws
Foot is electrically connected with the connection end of described 3rd resistor 502 and described 4th resistance 503, so can detect the ADC of described chip 6
Whether the circuit that the ADC pin of the voltage of pin and then the described chip 6 of confirmation is located turns on.
Before the GPIO pin to chip 6, LDO pin and ADC pin detect, need to examine by protection circuit 3
Survey whether described chip 6 is correctly installed in test trough 7, specific embodiment is as follows：
Described rosin joint test device includes the 5th resistance 703 and the 6th resistance 704, and the first of described 5th resistance 703 draws
Foot, the first pin of described 6th resistance 704 are electrically connected with the second feeder ear 705 respectively, and the second of described 5th resistance 703 draws
Foot, the second pin of described 6th resistance 704 are electrically connected with described MCU respectively.
Described test trough is provided with the first metal thimble 701 and the second metal thimble 702, and the of described 5th resistance 703
Two pins are also connected with described first metal thimble 701, the second pin of described 6th resistance 704 and described second metal thimble
702 connections.
Described protection circuit 3 includes audion 301, the 7th resistance 302, the 8th resistance 303, the first electric capacity 304, metal-oxide-semiconductor
305th, the second electric capacity 306 and the 3rd electric capacity 307.The base electrode of described audion 301 is electrically connected with the enable pin of described MCU,
The emitter stage of described audion 301 is connected with earth terminal 403, the colelctor electrode of described audion 301 and described 7th resistance 302
First pin connects, and the second pin of described 7th resistance 302 is electrically connected with the grid of described metal-oxide-semiconductor 305, described metal-oxide-semiconductor 305
Drain electrode electrically connect with the second feeder ear 705, the source electrode of described metal-oxide-semiconductor 305 is electrically connected with the power pins of described test trough, institute
The first pin stating the 8th resistance 303 is electrically connected with the drain electrode of described metal-oxide-semiconductor 305, the second pin of described 8th resistance 303 with
Colelctor electrode electrical connection, the first pin of described first electric capacity 304 and the colelctor electrode of described audion 301 of described audion 301
Electrical connection, the second pin of described first electric capacity 304 is electrically connected with the grid of described metal-oxide-semiconductor 305.Described second electric capacity 306
First pin, the first pin of described 3rd electric capacity 307 are all electrically connected with described second feeder ear 705, described second electric capacity 306
Second pin, the second pin of described 3rd electric capacity 307 all electrically connected with earth terminal 403.
When described chip 6 is correctly installed in described test trough, described first metal thimble 701 and described chip 6
First grounding pin electrical connection, described second metal thimble 702 is electrically connected with the second grounding pin of described chip 6, that is, described
Two pins electrically connecting with the first metal needle 701 and the second metal needle 702 of MCU are ground connection, are low level, and MCU triggers
Enable pin exports high level, and that is, A point is high level.When A point is high level, audion 301 turns on, and the second power supply
Termination power, makes B point be low level, that is, the grid of metal-oxide-semiconductor is low level, this metal-oxide-semiconductor is linked up enhancement mode metal-oxide-semiconductor for P, made this
Metal-oxide-semiconductor turns on, and by the second feeder ear 705, the power pins of test trough 7 is powered, because chip 6 is correctly installed on described survey
In experimental tank 7, the power pins of chip 6 are electrically connected by metal thimble with the power pins of described test trough 7, realize to chip 6
Power supply.
When described chip is not correctly installed in described test trough, described MCU with the first metal thimble 701 and
Two pins of two metal thimble 702 electrical connection are hanging, are high level, and now the enable pin of MCU is low level, and that is, A point is
High level, audion 301 ends, and B point is high level, and that is, the grid of metal-oxide-semiconductor 305 is high level, and this metal-oxide-semiconductor is linked up for P and strengthened
Type metal-oxide-semiconductor, the drain electrode of this metal-oxide-semiconductor and source electrode are open circuit, and now, the power pins no-voltage of test trough 7, even if chip error peace
It is loaded in described test trough, the power pins of test trough 7 do not result in the other functions pin to chip yet and cause high pressure to rush
Hit the risk leading to wafer damage.
Additionally, when chip is correctly installed in test trough, described first metal thimble is grounded with the first of described chip
Pin electrically connects, and described second metal thimble is electrically connected with the second grounding pin of described chip；When chip is not correctly installed
When in test trough, the first metal thimble is no electrically connected with the first grounding pin of described chip or the second metal thimble and institute
The second grounding pin stating chip no electrically connects the uniqueness it is ensured that circuit connects when chip is correctly installed.
In sum, realize whether being correctly installed on described test trough 7 to described chip by protection circuit 3 and examine
Survey, and to electricity on chip 6 and follow-up pin test could be carried out after proper installation, improve the safety of test with
And avoid chip because correctly not installing the damage leading to.
Correctly it is installed in test trough 7 when protection circuit 3 detects described chip 6, and described MCU is in described chip 6 just
Generate correct mount message when being really installed in described test trough 7 and be sent to computer, meanwhile, computer receive described just
MCU is really controlled to realize the detection of the pin to chip, by magnitude of voltage or the level of the pin to chip for the MCU after mount message
State, thus judging that chip whether there is rosin joint it is achieved that chip be whether there is with the automatic detection of rosin joint, has saved cost,
Improve testing efficiency and the yields of chip, reliability is higher.
As shown in figure 3, a kind of rosin joint method of testing of chip, realized using above-mentioned rosin joint test device, walk including following
Suddenly：
Step 101, described protection circuit detect whether described chip is in and are correctly installed in described test trough, if so,
Enter step 102, if it is not, then terminating.
Step 102, described MCU detect to the pin of described chip, and testing result is sent to described computer.
Described chip includes GPIO pin, LDO pin and ADC pin.Described MCU draws to described GPIO pin, LDO successively
Foot and ADC pin are detected.Described chip includes multiple GPIO pin, and described MCU is height current GPIO pin is detected
During level, that is, before deserving, this circuit no rosin joint residing for pin, then proceed the inspection to next GPIO pin or LDO pin
Survey, so can realize the automatic detection of the rosin joint to chip, improve detection efficiency, peripheral functionality and program need not be developed,
Save cost.
Although the foregoing describing the specific embodiment of the present invention, it will be appreciated by those of skill in the art that these
It is merely illustrative of, protection scope of the present invention is defined by the appended claims.Those skilled in the art is not carrying on the back
On the premise of the principle and essence of the present invention, various changes or modifications can be made to these embodiments, but these changes
Each fall within protection scope of the present invention with modification.
Claims (13)
1. a kind of rosin joint test device of chip is it is characterised in that including MCU, computer, protection circuit and test trough, described
Chip is installed in test trough；
Described protection circuit is used for detecting whether described chip is correctly installed in described test trough；
Described MCU is used for when described protection circuit detects described chip and is correctly installed on described test trough, to described chip
Pin detected, and testing result is sent to described computer.
2. the rosin joint test device of chip as claimed in claim 1 is it is characterised in that described chip includes GPIO pin, LDO
Pin and ADC pin；
Described MCU is used for successively described GPIO pin, LDO pin and ADC pin being detected.
3. the rosin joint test device of chip as claimed in claim 2 is it is characterised in that described chip includes multiple GPIO draws
Foot；
Described MCU is used for carrying out the inspection to next GPIO pin or LDO pin when current GPIO pin is detected for high level
Survey.
4. chip as claimed in claim 2 rosin joint test device it is characterised in that described rosin joint test device also include many
Path analoging switch, described chip includes multiple LDO pins, the plurality of LDO pin pass through described multiway analog switch with described
The ADC pin electrical connection of MCU；
Described multiway analog switch is used for connecting multiple described LDO pins successively with the ADC pin of described MCU by switching
Logical.
5. the rosin joint test device of chip as claimed in claim 4 is it is characterised in that described rosin joint test device also includes
One resistance and second resistance, described first resistor is series between described multiway analog switch and the ADC pin of described MCU, institute
The connection end stating one end of second resistance with the ADC pin of described MCU and described first resistor electrically connects, described second resistance
The other end is electrically connected with described earth terminal.
6. the rosin joint test device of chip as claimed in claim 2 is it is characterised in that described rosin joint test device also includes
One feeder ear, 3rd resistor and the 4th resistance, described first feeder ear, described 3rd resistor, described 4th resistance, earth terminal according to
Secondary series connection；
The ADC pin of described chip is electrically connected with the connection end of described 3rd resistor and described 4th resistance.
7. the rosin joint test device of chip as claimed in claim 1 is it is characterised in that described rosin joint test device includes the 5th
Resistance and the 6th resistance, the first pin of described 5th resistance, the first pin of described 6th resistance respectively with the second feeder ear
Electrical connection, the second pin of described 5th resistance, the second pin of described 6th resistance are electrically connected with described MCU respectively；
Described test trough is provided with the first metal thimble and the second metal thimble, the second pin of described 5th resistance also with described
First metal thimble connects, and the second pin of described 6th resistance is connected with described second metal thimble.
8. chip as claimed in claim 7 rosin joint test device it is characterised in that described protection circuit include audion,
7th resistance, the 8th resistance, the first electric capacity and metal-oxide-semiconductor, the base electrode of described audion is electrically connected with the enable pin of described MCU
Connect, the emitter stage of described audion is connected with earth terminal, the first pin of the colelctor electrode of described audion and described 7th resistance
Connect, the second pin of described 7th resistance is electrically connected with the grid of described metal-oxide-semiconductor, the drain electrode of described metal-oxide-semiconductor is powered with second
End electrical connection, the source electrode of described metal-oxide-semiconductor electrically connects with the power pins of described test trough, the first pin of described 8th resistance and
The drain electrode electrical connection of described metal-oxide-semiconductor, the second pin of described 8th resistance electrically connected with the colelctor electrode of described audion, and described the
First pin of one electric capacity is electrically connected with the colelctor electrode of described audion, the second pin of described first electric capacity and described metal-oxide-semiconductor
Grid electrical connection.
9. the rosin joint test device of chip as claimed in claim 8 is it is characterised in that described protection circuit also includes the second electricity
Hold and the 3rd electric capacity, the first pin of described second electric capacity, described 3rd electric capacity the first pin all with described second feeder ear
Electrical connection, the second pin of described second electric capacity, the second pin of described 3rd electric capacity are all electrically connected with earth terminal；.
10. the rosin joint test device of chip as claimed in claim 8 is it is characterised in that when described chip is correctly installed on institute
When stating in test trough, described first metal thimble is electrically connected with the first grounding pin of described chip, described second metal thimble
Electrically connect with the second grounding pin of described chip, the power pins of described test trough are electrically connected with the power pins of described chip
Connect.
A kind of rosin joint method of testing of 11. chips is it is characterised in that adopt rosin joint test device as claimed in claim 1 real
Existing, the method comprising the steps of：
S1, described protection circuit detect whether described chip is correctly installed in described test trough, if so, enter S2, if it is not, then
Terminate；
S2, described MCU detect to the pin of described chip, and testing result is sent to described computer.
The rosin joint method of testing of 12. chips as claimed in claim 11 it is characterised in that described chip include GPIO pin,
LDO pin and ADC pin；
In step s 2, described MCU detects to described GPIO pin, LDO pin and ADC pin successively.
The rosin joint method of testing of 13. chips as claimed in claim 12 is it is characterised in that described chip includes multiple GPIO draws
Foot；
In step s 2, described MCU carries out when current GPIO pin is detected for high level next GPIO pin or LDO are drawn
The detection of foot.
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| CN201611042255.XA CN106405313B (en) | 2016-11-24 | 2016-11-24 | The rosin joint test device and test method of chip |
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| CN108490334A (en) * | 2018-03-09 | 2018-09-04 | 北京凌宇智控科技有限公司 | Chip pin welds detection method and detection device |
| CN108760819A (en) * | 2018-05-22 | 2018-11-06 | 广州兴森快捷电路科技有限公司 | Welding quality test device and its detection method |
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| CN110568341A (en) * | 2019-08-30 | 2019-12-13 | 深圳三基同创电子有限公司 | System for automatically testing welding state of IO (input/output) interface function of PCBA (printed circuit board assembly) mainboard |
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| CN112345982A (en) * | 2020-09-29 | 2021-02-09 | 歌尔科技有限公司 | Method and device for detecting welding condition of circuit element |
| CN115033446A (en) * | 2022-04-20 | 2022-09-09 | 江苏汤谷智能科技有限公司 | Intelligent quality detection system and method of digital chip structure |
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