CN106385390B - Method and system for realizing ten-gigabit Ethernet power port transmission based on FPGA - Google Patents
Method and system for realizing ten-gigabit Ethernet power port transmission based on FPGA Download PDFInfo
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Abstract
The invention discloses a method and a system for realizing ten-gigabit Ethernet power port transmission based on an FPGA (field programmable gate array), belonging to the field of wireless transmission. The technical scheme includes that the gigabit Ethernet electric port transmission technology is applied between an extension unit and a remote unit, and a main realization part is completed inside an FPGA of the extension unit, the extension unit adopts a platform framework of a CPU + FPGA + gigabit PHY chip to realize the forwarding of a wireless optical port signal to the gigabit Ethernet electric port signal, an interface processing module is added inside the FPGA of an original framework to be matched with an external gigabit PHY chip to complete corresponding work, compared with the prior art, the application of the technology can improve the transmission bandwidth of a system in the wireless transmission field to a certain extent, the networking mode is more flexible, POE power supply can be realized, the realization is realized on the basis of the FPGA of the original framework, and the realization cost and the development difficulty are reduced.
Description
Technical Field
The invention relates to the field of wireless transmission, in particular to a method and a system for realizing gigabit Ethernet power port transmission based on an FPGA (field programmable gate array).
Background
With the rapid development of urban mobile users and the continuous increase of large buildings and high-rise buildings, the system capacity and coverage requirements are continuously increased, so that the indoor distribution system is widely applied. In the later 4G era of high-speed development of wireless transmission technology, three operators are bound to develop towards a deeper coverage direction based on a multi-network and multi-mode co-construction environment of an iron tower company, and the investment of indoor deep coverage is continuously increased in the future. However, the traditional active room subsystem has the problems of limited bandwidth, complex design, difficult construction and the like, and how to solve the problems is the key of the evolution of the traction technology. Under the premise, the development of novel indoor distributed products towards multi-frequency, multi-mode, intelligentization and miniaturization is a necessary trend, and therefore a transmission medium is required to support higher speed, higher bandwidth and more convenient construction.
Compared with the traditional fast Ethernet technology, the gigabit Ethernet transmission technology can better meet the requirement of a novel indoor distribution scheme on the bandwidth by using the higher bandwidth, and provides a more flexible networking mode. The adoption adopts the net twine transmission, and its construction portable characteristics are liked by the user deeply, can satisfy the demand of more convenient construction. In addition, by using the electrical port technology and adopting a network cable transmission mode, the realization opportunity of POE (Power Over Ethernet) power supply can be provided for the equipment. Therefore, it is very significant to apply the gigabit ethernet interface transmission technology to the wireless transmission system.
Disclosure of Invention
The invention provides a method for applying a gigabit Ethernet power interface transmission technology to a wireless transmission system, and a novel indoor distribution system is taken as an example, but not limited to the novel indoor distribution system. The method can achieve the purposes of improving the transmission bandwidth of the novel indoor distribution system and enabling the construction mode to be more convenient, and meanwhile, provides opportunities for realizing POE (Power over Ethernet) power supply.
A method for realizing ten-gigabit Ethernet power port transmission based on FPGA comprises the following steps in downlink:
step S1, the expansion unit obtains the data sent by the access unit through the optical port, and then carries out serial-parallel conversion through the SERDES interface module in the FPGA inside the expansion unit;
step S2, the CPRI module in the FPGA adopts a mode of nesting frame structures step by step according to a standard CPRI protocol, and encapsulates the data sent by the optical interface into a CPRI frame;
and step S3, sending the assembled CPRI frame to an XGMII interface module in the FPGA, wherein the module mainly comprises two parts of packaging the CPRI frame into an XGMII core interface time sequence and realizing the conversion from the XGMII interface time sequence to an XFI interface of a ten-gigabit PHY chip, converting the XGMI interface time sequence into an interface time sequence butted by the ten-gigabit PHY chip, broadcasting the interface time sequence into each electric port, and the FPGA completes the conversion from an optical port signal to a ten-gigabit Ethernet electric port signal and further broadcasting the converted signal to all remote units.
Wherein, in the step S1, the concrete steps are:
the expansion unit receives quadrature modulation signal data obtained by an optical port connected with the near-end unit, defines the data bit width and the working clock after serial-parallel conversion according to the actual total bandwidth, and realizes clock recovery and serial-parallel conversion through an SERDES interface module in an FPGA inside the expansion unit.
Wherein, the step S2 includes:
the SERDES module unframes the converted data to the CPRI module, separates and outputs signal data and monitoring data of each path, polls the monitoring data and the local monitoring data to enter a CPU, and encapsulates other corresponding monitoring data and signal data into CPRI frames in a mode of nesting frame structures step by step according to a standard CPRI protocol.
Before step S1, the method further includes:
according to the specific situation of the service types supported by the equipment, selecting the total bandwidth of the optical port of the access unit to access the expansion unit, selecting the working system clock frequency, the frame frequency of the basic optical port and the data bit width of the optical port, and calculating the number of bytes occupied by each path of service data in the basic frame.
The XGMII interface module mainly comprises 64b/66b codes, clock recovery and a high-speed SERDES conversion module, and the work of the part can be realized by a logic code high-speed SERDES kernel module or directly connected with an XGMII hard kernel.
When the CPRI module encapsulates data sent by the optical port into the CPRI frame according to the standard CPRI protocol, column 1 of each basic frame is defined here, and includes frame header information for synchronous detection, system combination type, optical port number information, characteristic value and other monitoring information, and if necessary, new monitoring information may occupy the position of the characteristic value.
A method for realizing ten-gigabit Ethernet power interface transmission based on FPGA comprises the following steps in uplink:
step S1, receiving uplink data obtained by each electric port connected with the remote unit by a gigabit PHY chip in the expansion unit, and then sending the uplink data to an XGMII interface module in the FPGA;
step S2, decapsulating the CPRI frame signal to separate out the monitoring data and the signal data, polling the monitoring data to enter the CPU, at the same time, summing the signal data of each path, framing the output monitoring data and the signal data through the CPRI module, and sending the framed data and signal data into the uplink optical port through the SERDES module;
and step S3, transmitting the signals to the access unit through the optical port to realize the forwarding of the signals from the gigabit Ethernet electrical port to the optical port.
At the receiving end of the uplink expansion unit, according to the fact that data malposition may occur when a single-bit tera signal sent by a tera PHY chip is recovered through protocol conversion, a mechanism for automatically judging whether the recovered parallel data is malpositioned or not and recovering the data is added.
A system for realizing ten-gigabit Ethernet power port transmission based on an FPGA comprises an access unit, an extension unit and a remote unit, wherein a plurality of external information sources are introduced into a radio frequency interface corresponding to the access unit through a coupler, the access unit is connected with the extension unit through an optical fiber, and the extension unit is connected with the remote unit through a network cable;
the expansion unit hardware adopts a platform architecture of a CPU + FPGA + tera PHY chip, the functions to be completed comprise photoelectric conversion, combination of digital intermediate frequency signals and broadband signals, the combined digital signals need to be framed again in a certain format, a plurality of remote units are transmitted through network cables, uplink digital signals received by each electric port are shunted, and the separated digital intermediate frequency signals are transmitted to an access unit after photoelectric conversion through a laser;
the CPU mainly completes the configuration and monitoring work of each service chip and interacts control and management information with a superior base station through the FPGA; meanwhile, the control part provides a debugging network port, an LED lamp indicator, single-disk reset and the like for single-disk debugging and fault location, and realizes the access to an external memory through a local data bus and an address bus, thereby completing the functions of system self-starting, program loading, data storage and the like;
the tera PHY chip has the main functions of transmitting data to the remote unit in an electric port mode and receiving the data transmitted by the remote unit through the electric port;
the FPGA has the main function of realizing the forwarding of a wireless optical port signal to a gigabit Ethernet electrical port signal, and comprises a CPU interface module, an SERDES interface module, a CPRI module and an XGMII interface module;
when the XGMII interface module goes down, the formed data stream is coded by means of multi-bit to more-bit serial-parallel conversion and frame head and frame tail addition, and then multi-bit to unit parallel-serial conversion is carried out, so that conversion from a CPRI protocol frame to an XFI interface is realized.
Has the advantages that:
the invention applies the gigabit Ethernet electric interface transmission technology between the extension unit and the remote unit, the main realization part is completed in the FPGA of the extension unit, the extension unit adopts the platform framework of CPU + FPGA + gigabit PHY chip, and the forwarding of the wireless optical interface signal to the gigabit Ethernet electric interface signal is realized. Compared with the prior art, the application of the technology can improve the transmission bandwidth of a system in the field of wireless transmission to a certain extent, so that the networking mode is more flexible, the development cost is reduced, and the realization efficiency is improved. And POE power supply can be realized, so that the engineering construction difficulty is simplified, and the use cost is reduced.
Drawings
Fig. 1 is a flowchart of a method for implementing gigabit ethernet interface transmission based on an FPGA in downlink.
Fig. 2 is a flowchart of a method for implementing gigabit ethernet interface transmission based on an FPGA in uplink.
Fig. 3 is a block diagram of a system networking mode for realizing gigabit ethernet power port transmission based on an FPGA.
Fig. 4 is a single-disc functional block diagram of an expansion unit.
FIG. 5 is a top level architecture diagram internal to the FPGA.
Detailed Description
The technical solution of the present invention will be described in detail with reference to the accompanying drawings and examples.
Example 1
The invention provides a method for applying a gigabit Ethernet power interface transmission technology to a wireless transmission system, and a novel indoor distribution system is taken as an example, but not limited to the novel indoor distribution system. The new indoor distribution system introduced here is a coverage solution for directly coupling base station signals, and mainly consists of three parts, namely an Access Unit (AU), an Extended Unit (EU), and a Remote Unit (RU). The system supports various networking modes, wherein a star networking mode is taken as an example, a plurality of information sources are introduced into a radio frequency interface corresponding to an access unit through a coupler, the access unit and an extension unit are in star connection, and the specific networking mode is shown in figure 3.
As shown in fig. 4, the implementation method of the present invention is mainly implemented by matching an FPGA of an extension unit with an external gigabit PHY chip, and by adding an interface processing module inside the FPGA (field programmable logic array chip) of the original architecture of the system and matching the external gigabit PHY (physical layer interface) chip, forwarding of a wireless optical port signal to a gigabit ethernet electrical port signal is implemented. The FPGA is mainly divided into a CPU Interface module, a Common Public Radio Interface (CPRI) module, a serial-parallel converter (SERDES) Interface module and an XGMII (10 Gb Interface independent of media) Interface module, and the FPGA expansion data Interface module can be added if the transmission function of multi-port gigabit Ethernet needs to be expanded. The internal top-level structure of the whole FPGA is shown in FIG. 5.
As shown in fig. 1, a method for implementing gigabit ethernet power interface transmission based on FPGA includes the following steps in downlink:
step S1, the expansion unit obtains the data sent by the access unit through the optical port, and then carries out serial-parallel conversion through the SERDES interface module in the FPGA inside the expansion unit;
step S2, the CPRI module in the FPGA adopts a mode of nesting frame structures step by step according to a standard CPRI protocol, and encapsulates the data sent by the optical interface into a CPRI frame;
and step S3, sending the assembled CPRI frame to an XGMII interface module in the FPGA, wherein the module mainly comprises two parts of packaging the CPRI frame into an XGMII core interface time sequence and realizing the conversion from the XGMII interface time sequence to an XFI interface of a ten-gigabit PHY chip, converting the XGMI interface time sequence into an interface time sequence butted by the ten-gigabit PHY chip, broadcasting the interface time sequence into each electric port, and the FPGA completes the conversion from an optical port signal to a ten-gigabit Ethernet electric port signal and further broadcasting the converted signal to all remote units.
The invention applies the gigabit Ethernet electric interface transmission technology between the extension unit and the remote unit, the main realization part is completed in the FPGA of the extension unit, the extension unit adopts the platform framework of CPU + FPGA + gigabit PHY chip, and the forwarding of the wireless optical interface signal to the gigabit Ethernet electric interface signal is realized. Compared with the prior art, the application of the technology can improve the transmission bandwidth of a system in the field of wireless transmission to a certain extent, so that the networking mode is more flexible, the development cost is reduced, and the realization efficiency is improved. And POE power supply can be realized, so that the engineering construction difficulty is simplified, and the use cost is reduced.
Wherein, in the step S1, the concrete steps are:
the expansion unit receives quadrature modulation signal data obtained by an optical port connected with the near-end unit, defines the data bit width and the working clock after serial-parallel conversion according to the actual total bandwidth, and realizes clock recovery and serial-parallel conversion through an SERDES interface module in an FPGA inside the expansion unit.
Wherein, the step S2 includes:
the SERDES module unframes the converted data to the CPRI module, separates and outputs signal data and monitoring data of each path, polls the monitoring data and the local monitoring data to enter a CPU, and encapsulates other corresponding monitoring data and signal data into CPRI frames in a mode of nesting frame structures step by step according to a standard CPRI protocol.
In the working process of each sub-module, in the downlink direction, first, before step S1, according to the specific situation of the service type supported by the device, the total bandwidth of the optical port where the access unit accesses the expansion unit is selected, the system clock frequency, the basic optical port frame frequency, and the data bit width of the optical port work are selected, and the number of bytes occupied by each path of service data in the basic frame is calculated. For example, the maximum total supported bandwidth of the single disc is 10G, and taking 10G full allocation as an example, the total effective transmission bandwidth of the service signal received by the optical interface is 10Gbps × 0.8 = 8 Gbps, the operating clock of the optical interface system is defined as 250M, and the data bit width is 32 bits. The SERDES interface module receives serial signals sent by the optical port and converts the serial signals into parallel signals according to the defined bit width and rate. And then the CPRI module encapsulates the data sent by the optical port into a CPRI frame by adopting a mode of nesting the frame structure step by step according to a standard CPRI protocol. The 1 st column of each basic frame is defined here, and contains frame header information, system combination type, optical port number information, characteristic value and other monitoring information for synchronous detection, and new monitoring information can occupy the position of the characteristic value if necessary. The assembled CPRI frame is sent to an XGMII interface module which mainly comprises two parts of packaging the CPRI frame into an XGMII core interface time sequence and realizing the conversion from the XGMII interface time sequence to an XFI interface of a PHY chip. Firstly, a buffer FIFO (first-in first-out queue) is generated, and in the input direction, valid data with a code rate of 250M and a bit width of 32 bits sent by the CPRI module is written into the corresponding buffer FIFO according to a valid indication signal. In the output direction, data is read at the read end according to the 64-bit width and the code rate of 156.25M, as indicated by the sufficient number of bytes of one XGMII frame (the length can be defined according to actual requirements, and the XGMII frame length is defined as 256 clocks by taking full configuration 10G as an example). And adding '000000 FB 00000000' as a frame header to the frame header of each frame, and adding '00000000000000 FD' as a frame tail to the frame tail of each frame, namely, putting a frame header on a data bus every time, continuously reading 256 data, and then putting a frame tail signal. And generates corresponding indication signals to be sent to the conversion part of the XGMII interface to the XFI interface. The part mainly comprises 64b/66b coding, clock recovery and a high-speed SERDES conversion module, and the work of the part can be realized by a logic code high-speed SERDES core module or directly connected with an XGMII hard core. The SERDES core outputs a 10G serial electric signal to the tera PHY chip, so that the FPGA completes the conversion work from a wireless signal to a tera Ethernet electric interface signal.
Example 2
The difference between embodiment 2 and embodiment 1 is that embodiment 1 is a method for realizing gigabit ethernet port transmission based on an FPGA in the downlink, and embodiment 2 is a method for realizing gigabit ethernet port transmission based on an FPGA in the uplink.
The only difference is that at the receiving end of the uplink expansion unit, according to the fact that the single-bit terabyte signal sent by the terabyte PHY chip is high in rate, data malposition is likely to occur through protocol conversion recovery, a mechanism for automatically judging whether the recovered parallel data is malpositioned or not and recovering is added. The specific operation method is to count several possible dislocation modes according to the mode of actually testing the special array, and enter the adjusting module to adjust when the error indicating bit of the data signal is detected to be not time-tick.
As shown in fig. 2, the method for implementing gigabit ethernet power interface transmission based on FPGA of the present invention includes the following steps in uplink:
step S1, receiving uplink data obtained by each electric port connected with the remote unit by a gigabit PHY chip in the expansion unit, and then sending the uplink data to an XGMII interface module in the FPGA;
step S2, decapsulating the CPRI frame signal to separate out the monitoring data and the signal data, polling the monitoring data to enter the CPU, at the same time, summing the signal data of each path, framing the output monitoring data and the signal data through the CPRI module, and sending the framed data and signal data into the uplink optical port through the SERDES module;
and step S3, transmitting the signals to the access unit through the optical port to realize the forwarding of the signals from the gigabit Ethernet electrical port to the optical port.
Example 3
The present embodiment is a system embodiment, and belongs to the same technical concept as the method embodiments 1 and 2, and please refer to the method embodiments 1 and 2 for the content that is not described in detail in the present embodiment.
As shown in fig. 3-5, the system for implementing gigabit ethernet power interface transmission based on FPGA according to the present invention includes an access unit, an extension unit, and a remote unit, where a plurality of external information sources are introduced into a radio frequency interface corresponding to the access unit through a coupler, the access unit is connected to the extension unit through an optical fiber, and the extension unit is connected to the remote unit through a network cable;
the expansion unit hardware adopts a platform architecture of a CPU + FPGA + tera PHY chip, the functions to be completed comprise photoelectric conversion, combination of digital intermediate frequency signals and broadband signals, the combined digital signals need to be framed again in a certain format, a plurality of remote units are transmitted through network cables, uplink digital signals received by each electric port are shunted, and the separated digital intermediate frequency signals are transmitted to an access unit after photoelectric conversion through a laser;
the CPU mainly completes the configuration and monitoring work of each service chip and interacts control and management information with a superior base station through the FPGA; meanwhile, the control part provides a debugging network port, an LED lamp indicator, single-disk reset and the like for single-disk debugging and fault location, and realizes the access to an external memory through a local data bus and an address bus, thereby completing the functions of system self-starting, program loading, data storage and the like;
the tera PHY chip has the main functions of transmitting data to the remote unit in an electric port mode and receiving the data transmitted by the remote unit through the electric port;
the FPGA has the main function of realizing the forwarding of a wireless optical port signal to a gigabit Ethernet electrical port signal, and comprises a CPU interface module, an SERDES interface module, a CPRI module and an XGMII interface module;
when the XGMII interface module goes down, the formed data stream is coded by means of multi-bit to more-bit serial-parallel conversion and frame head and frame tail addition, and then multi-bit to unit parallel-serial conversion is carried out, so that conversion from a CPRI protocol frame to an XFI interface is realized.
The main function of the FPGA is to enable the transmission of broadband information between the extension unit and the remote unit, in the downlink, quadrature modulated signal data obtained from an optical port connected to the near end unit is received, defining the data bit width and the working clock after serial-parallel conversion according to the actual total bandwidth, realizing clock recovery and serial-parallel conversion through an SERDES (parallel-serial converter) interface module, then, the data is encapsulated by a Common Public Radio Interface (CPRI) module, and then is converted in a serial-parallel manner again by a gigabit Interface module, namely an XGMII Interface module, so as to further widen the bit width and reduce the code rate, and adds frame head and tail signals, encodes, converts into interface time sequence of ten gigabit PHY chip butt joint, broadcasts to each electric port, meanwhile, the monitoring data of the optical port is sent to the CPU, and other corresponding monitoring data are broadcasted to all remote modules through the tera interface; in the uplink, the gigabit interface module is used to receive the uplink data from the electric ports connected to the remote units, perform interface protocol conversion, judge whether the received data has error according to the error indication signal, and judge whether the CPRI frame signal decoded by the XGMII interface module needs to be adjusted. If error signal exists, the frame structure is adjusted, if not, the next stage is directly output. And solving data signals in the adjusted CPRI frame signals, summing the signals, sending the summed signals to an optical port through an SERDES interface module, and receiving monitoring data from all remote units, wherein the whole work flow is the reverse process of a downlink generally.
The above examples are illustrative of the preferred embodiments of the present invention, but the present invention is not limited to the above examples, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present invention should be construed as equivalents thereof, and they are intended to be included in the scope of the present invention.
Claims (5)
1. A method for realizing ten-gigabit Ethernet power port transmission based on FPGA is characterized in that in downlink, the method comprises the following steps:
step S1, the expansion unit obtains the data sent by the access unit through the optical port, and then carries out serial-parallel conversion through the SERDES interface module in the FPGA inside the expansion unit;
step S2, the CPRI module in the FPGA adopts a mode of nesting frame structures step by step according to a standard CPRI protocol, and encapsulates the data sent by the optical interface into a CPRI frame;
step S3, sending the assembled CPRI frame to XGMII interface module in FPGA, where the module mainly includes two parts of packaging CPRI frame into XGMII core interface time sequence and realizing conversion from XGMII interface time sequence to XFI interface of ten-million PHY chip, converting the XGMI interface time sequence into interface time sequence for butt joint of ten-million PHY chip, broadcasting to each electric port, where FPGA completes the conversion work from optical port signal to ten-million Ethernet electric port signal, and further broadcasting to all remote units, the XGMI interface module mainly includes 64b/66b code, clock recovery and a high-speed SERDES conversion module, and the work of this part can be realized by logic code high-speed SERDES core module or directly connected with XGMII hard core;
in uplink, the method comprises the following steps:
step S4, receiving uplink data obtained by each electric port connected with the remote unit by a gigabit PHY chip in the expansion unit, and then sending the uplink data to an XGMII interface module in the FPGA;
step S5, decapsulating the CPRI frame signal to separate out the monitoring data and the signal data, polling the monitoring data to enter the CPU, at the same time, summing the signal data of each path, framing the output monitoring data and the signal data through the CPRI module, and sending the framed data and signal data into the uplink optical port through the SERDES module;
step S6, transmitting the signals to an access unit through an optical port to realize the forwarding of the signals from the electrical port to the optical port of the gigabit Ethernet;
at the receiving end of the uplink expansion unit, according to the fact that data malposition may occur when a single-bit tera signal sent by a tera PHY chip is recovered through protocol conversion, a mechanism for automatically judging whether the recovered parallel data is malpositioned or not and recovering the data is added.
2. The method for implementing gigabit ethernet electrical interface transmission according to claim 1, wherein in downlink, the step S1 specifically comprises:
the expansion unit receives quadrature modulation signal data obtained by an optical port connected with the near-end unit, defines the data bit width and the working clock after serial-parallel conversion according to the actual total bandwidth, and realizes clock recovery and serial-parallel conversion through an SERDES interface module in an FPGA inside the expansion unit.
3. The method for implementing gigabit ethernet electrical interface transmission according to claim 1, wherein in downlink, the step S2 includes:
the SERDES module unframes the converted data to the CPRI module, separates and outputs signal data and monitoring data of each path, polls the monitoring data and the local monitoring data to enter a CPU, and encapsulates other corresponding monitoring data and signal data into CPRI frames in a mode of nesting frame structures step by step according to a standard CPRI protocol.
4. The method for implementing gigabit ethernet port transmission according to claim 1, wherein the downlink, before step S1, further comprises:
according to the specific situation of the service types supported by the equipment, selecting the total bandwidth of the optical port of the access unit to access the expansion unit, selecting the working system clock frequency, the frame frequency of the basic optical port and the data bit width of the optical port, and calculating the number of bytes occupied by each path of service data in the basic frame.
5. The method according to claim 1, wherein in downlink, when the CPRI module encapsulates the data sent by the optical port into CPRI frames according to the standard CPRI protocol, column 1 of each basic frame is defined herein, and includes monitoring information such as frame header information for synchronous detection, system combination type, optical port number information, and feature value, and new monitoring information can occupy the location of the feature value if necessary.
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