CN106385254B - A kind of frequency scan circuit for LC type phaselocked loop - Google Patents
A kind of frequency scan circuit for LC type phaselocked loop Download PDFInfo
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- CN106385254B CN106385254B CN201610893528.5A CN201610893528A CN106385254B CN 106385254 B CN106385254 B CN 106385254B CN 201610893528 A CN201610893528 A CN 201610893528A CN 106385254 B CN106385254 B CN 106385254B
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- 238000012986 modification Methods 0.000 description 2
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
The present invention relates to a kind of frequency scan circuit for LC type phaselocked loop, which includes comparator, AND gate circuit, N-bit counter and d type flip flop, and the input terminal of comparator connects lower voltage limit VLWith judgement voltage VdectThe output end of input terminal the connection count clock Count_clk and comparator of AND gate circuit, the output end O of the D input terminal connection N-bit counter of d type flip flop, the input terminal C connection count period Count_period of N-bit counter, the output end of the C input terminal connection AND gate circuit of d type flip flop, the Q output of d type flip flop connect VCOselSelection signal, for controlling voltage controlled oscillator array switch SW < 0:2N-1>.The present invention determines voltage using the feedback loop judgement of phaselocked loop, greatly simplifies configuration circuit and process, it can be achieved that can be widely applied to LC type Design of PLL for the automatic frequency scan of voltage controlled oscillator array and selection.
Description
Technical field
The invention belongs to microelectronics technologies, are related to a kind of LC type phaselocked loop, especially a kind of to be used for LC type phaselocked loop
Frequency scan circuit.
Background technique
Phaselocked loop is straight applied to fields, performance superiority and inferiority such as Digital Frequency Synthesize, wireless receiving and dispatchings as a common part
Connect the work quality for influencing entire circuit system.Under the conditions of high band operation, LC type phaselocked loop is due to its superior making an uproar property of phase
The features such as energy, frequency stability, is used widely in wireless communication field.Since the LC oscillator frequency range of single size is relatively narrow,
It needs different size LC groups being combined into array application in practical applications, to meet broadband requirement.Conventional method is joined according to input
Frequency, frequency calculating output frequency are examined, chooses LC array in conjunction with operating temperature, calculating process and configuration are cumbersome.
Summary of the invention
The technical problem to be solved by the present invention is to overcome the existing defects, provides a kind of frequency band for LC type phaselocked loop and sweeps
Scanning circuit, the frequency scan circuit using phaselocked loop feedback loop judgement determine voltage, greatly simplifie configuration circuit and
Process can be widely applied to LC type Design of PLL, it can be achieved that for the automatic frequency scan of voltage controlled oscillator array and selection.
In order to solve the above-mentioned technical problems, the present invention provides the following technical solutions:
A kind of frequency scan circuit for LC type phaselocked loop of the present invention, which includes comparator and door
Circuit, N-bit counter and d type flip flop, the input terminal connection lower voltage limit VL and judgement voltage Vdect of comparator, AND gate circuit
Input terminal connection count clock Count_clk and comparator output end, the D input terminal connection N-bit counter of d type flip flop
Output end O, the input terminal C connection count period Count_period of N-bit counter, the connection of C input terminal and the door electricity of d type flip flop
The Q output of the output end on road, d type flip flop connects VCOsel selection signal, for controlling voltage controlled oscillator array switch SW < 0:
2N-1>。
Further, the input of frequency scan circuit determines that voltage Vdect is exported by charge pump, and voltage value is equal to voltage-controlled electricity
Press Vctrl；Frequency scan circuit output VCOsel selection signal selects array to voltage controlled oscillator.
Further, the counting period Count_period and counting clock Count_clk of frequency scan circuit, which exist, divides
Frequency relationship, Count_period=Count_clk/2N.
Further, the N value of the N-bit counter of frequency scan circuit is determined by the voltage controlled oscillator quantity of required control
Fixed, 2N is greater than voltage controlled oscillator quantity.
Further, frequency scan circuit output 2N control code.
Beneficial effects of the present invention:
Whether the feedback loop of phaselocked loop is utilized in frequency scan circuit of the invention, judge to determine voltage Vdect most
In excellent control area, voltage controlled oscillator antenna array control selection signal VCOsel is obtained；When judgement voltage Vdect is more than optimum control
When the lower voltage limit VL of region, the output valve VCOsel of the current d type flip flop of lockable.Circuit of the present invention can be realized for voltage controlled oscillation
The automatic frequency scan of device VCO array and selection, circuit simplify frequency band calculating compared with the circuit of conventional manual selection frequency band
Process and circuit configuration can be widely applied in LC type phase-locked loop circuit.
Detailed description of the invention
Fig. 1 is LC type principle of phase lock loop figure of the invention；
Fig. 2 is frequency scan circuit diagram of the invention；
Fig. 3 is the frequency scan circuit diagram of the N=5 of one embodiment of the invention；
Fig. 4 is the LC array circuit figure of one embodiment of the invention.
Specific embodiment
A specific embodiment of the invention is illustrated below in conjunction with drawings and concrete examples.
Fig. 1 is the present invention applied LC type phase-locked loop circuit schematic diagram in specific implementation, which is typical LC
Type phaselocked loop, voltage controlled oscillator 2 is using 32 sections of array structures as shown in figure 4, the output of voltage controlled oscillator 2 is through N1 frequency divider 3, N2 points
Frequency device 4 is supplied to frequency discrimination phase-sensitive detector PFD 5 and input reference clock Refclk frequency discrimination phase-detecting after dividing twice.Frequency scan circuit
1 among charge pump 6 and voltage controlled oscillator 2, obtains 32 selection signal VCOset by comparing judgement voltage Vdect and is used for
Control 2 array switch SW<0:31>of voltage controlled oscillator.
The lower limit value of the optimal voltage-controlled voltage range of voltage controlled oscillator 2 is VL, upper limit value VH in the example, in this voltage
LC voltage controlled oscillator 2 all in array has the linear convergent rate optimized in range, which can guarantee entire voltage controlled oscillation
Device 2 is exported with continuous frequency band.
Fig. 2 is frequency scan circuit diagram, which includes comparator CMP111, AND gate circuit AND12, N position
The input terminal connection lower voltage limit VL and judgement electricity of counter N_Counter 13 and d type flip flop DFF 14, comparator CMP111
Press Vdect, the output end of input terminal the connection count clock Count_clk and comparator CMP111 of AND gate circuit AND 12, D touching
The output end O of the D input terminal connection N-bit counter N_Counter13 of device DFF 14 is sent out, N-bit counter N_Counter's 13
The C input terminal connection AND gate circuit AND's 12 of input terminal C connection count period Count_period, d type flip flop DFF 14 is defeated
Outlet, the Q output of d type flip flop DFF 14 connect VCOsel selection signal, for control 2 array switch SW of voltage controlled oscillator <
0:2N-1>。
Fig. 3 is a kind of exemplary embodiments of Fig. 2, which includes comparator 11, AND gate circuit 12, N-bit counter 13 and D
Trigger 14, since LC array is 32 sections, so the N value of N-bit counter 13 is 5 in the example.Wherein, period Count_ is counted
There are frequency dividing relationship, Count_period=31.25KHz, 32ms, Count_clk=with counting clock Count_clk by period
1MHz, 1000ns, N-bit counter 13 is added up with the clock interval of 32ms, and (the time interval design value should be locked much larger than phaselocked loop
It fixes time).
Fig. 4 is LC array circuit figure, since frequency scan terminates since low-frequency band BAND-0 to high frequency band BAND-31,
Voltage-controlled voltage Vctrl and determine that voltage Vdect is from low toward high before the unlocked selection of the circuit, Vdect is lower than optimal voltage-controlled
When voltage lower limit value VL, AND gate circuit 12 can provide the 1MHz clock transfer of Count_clk to the C input terminal of d type flip flop 14
Clock extension signal, at this time d type flip flop 14 will using 32ms as the period export Continuous accumulation VCOsel selection signal, from 00000 to
11111；When the LC segment frequence that VCOsel selection signal is selected meets current frequency setting, by feeding back obtained voltage-controlled electricity
Pressure Vctrl and judgement voltage Vdect will be greater than optimal voltage-controlled voltage lower limit value VL, and AND gate circuit 12 will export perseverance 0 at this time, at this time
D type flip flop 14 can lock current VCOsel selection signal, and be allocated to array switch signal SW<0:31>.So far, the LC type
Phaselocked loop completes automatic frequency scan and selection.
Embodiment cited by the present invention, is merely used to help understand the present invention, should not be construed as protecting model to the present invention
The restriction enclosed for those skilled in the art without departing from the inventive concept of the premise, can also be right
The present invention makes improvements and modifications, these improvement and modification are also fallen into the range of the claims in the present invention protection.
Claims (5)
1. a kind of frequency scan circuit for LC type phaselocked loop, it is characterised in that: the frequency scan circuit (1) includes comparing
The input terminal of device (11), AND gate circuit (12), N-bit counter (13) and d type flip flop (14), comparator (11) connects lower voltage limit
VLWith judgement voltage Vdect, the output of the input terminal connection count clock Count_clk and comparator (11) of AND gate circuit (12)
End, the output end O of D input terminal connection N-bit counter (13) of d type flip flop (14), the input terminal C connection of N-bit counter (13)
Count period Count_period, the output end of C input terminal connection AND gate circuit (12) of d type flip flop (14), d type flip flop (14)
Q output connect VCOselSelection signal, for controlling voltage controlled oscillator (2) array switch SW < 0:2N-1>。
2. the frequency scan circuit according to claim 1 for LC type phaselocked loop, it is characterised in that: the frequency scan
Circuit (1) input determines voltage VdectIt is exported by charge pump (6), voltage value is equal to voltage-controlled voltage Vctrl；Frequency scan circuit
(1) VCO is exportedselSelection signal selects array to voltage controlled oscillator (2).
3. the frequency scan circuit according to claim 1 for LC type phaselocked loop, it is characterised in that: the frequency scan
There are frequency dividing relationship, Count_period=with counting clock Count_clk by the counting period Count_period of circuit (1)
Count_clk/2N。
4. the frequency scan circuit according to claim 1 for LC type phaselocked loop, it is characterised in that: the frequency scan
The N value of the N-bit counter (13) of circuit (1) determines by voltage controlled oscillator (2) quantity of required control, 2NGreater than voltage controlled oscillation
Device (2) quantity.
5. the frequency scan circuit according to claim 1 for LC type phaselocked loop, it is characterised in that: the frequency scan
Circuit (1) output 2NPosition control code.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610893528.5A CN106385254B (en) | 2016-10-13 | 2016-10-13 | A kind of frequency scan circuit for LC type phaselocked loop |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610893528.5A CN106385254B (en) | 2016-10-13 | 2016-10-13 | A kind of frequency scan circuit for LC type phaselocked loop |
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| CN106385254A CN106385254A (en) | 2017-02-08 |
| CN106385254B true CN106385254B (en) | 2019-04-19 |
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| CN201610893528.5A Active CN106385254B (en) | 2016-10-13 | 2016-10-13 | A kind of frequency scan circuit for LC type phaselocked loop |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102158208A (en) * | 2011-04-02 | 2011-08-17 | 东南大学 | Whole-course adjustable digital pulse width modulator based on oscillation ring circuit |
| US8358159B1 (en) * | 2011-03-10 | 2013-01-22 | Applied Micro Circuits Corporation | Adaptive phase-locked loop (PLL) multi-band calibration |
| CN103346787A (en) * | 2013-06-14 | 2013-10-09 | 浙江大学 | Phase-locked loop frequency synthesizer structure with automatic frequency correction |
-
2016
- 2016-10-13 CN CN201610893528.5A patent/CN106385254B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8358159B1 (en) * | 2011-03-10 | 2013-01-22 | Applied Micro Circuits Corporation | Adaptive phase-locked loop (PLL) multi-band calibration |
| CN102158208A (en) * | 2011-04-02 | 2011-08-17 | 东南大学 | Whole-course adjustable digital pulse width modulator based on oscillation ring circuit |
| CN103346787A (en) * | 2013-06-14 | 2013-10-09 | 浙江大学 | Phase-locked loop frequency synthesizer structure with automatic frequency correction |
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| CN106385254A (en) | 2017-02-08 |
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