CN106385252A - Multi-phase clock generation method and circuit for realizing high precision phase difference control - Google Patents
Multi-phase clock generation method and circuit for realizing high precision phase difference control Download PDFInfo
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- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
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Abstract
The invention relates to a multi-phase clock generation method for realizing high precision phase difference control, and the method comprises the steps: a multi-phase clock generation circuit outputs n-channel clock signals with equidistant phase differences in a way of differential signal, n-channel clock signals are respectively transmitted to corresponding controlled time-delay circuits through match circuits and differential transmission lines to perform phase correction, and the corrected n-channel clock signals are respectively transmitted to driven terminals. According to the invention, a controlled time-delay circuit is added to correct the phase of each clock signal in clock signal transmission process, so that the high precision control for phase difference between multi-phase clock can be realized.
Description
Technical field
The present invention relates to High-speed Digital Circuit Design field, realize high-precision phase position difference more particularly, to one kind and control
Multi-phase clock production method and circuit.
Background technology
Clock circuit is vital part in High-speed Digital Circuit Design, with integrated level and the complexity of Circuits System
Degree improves constantly, and may relate to the equidistant clock signal of multiple frequency same phases difference in same design, this just to clock jitter,
The phase error that skewed clock causes proposes higher and higher requirement.In multi-phase clock system, generally adopt traditional lock phase
Ring (PLL) technology produces high-frequency signal, produces multi-phase clock signal in combination with delay locked loop (DLL) technology.This technology
Because its structure is simple, good stability is widely applied, but when target devices are driven by transmission line, high speed signal
Affected by impedance discontinuity, crosstalk, load and environment noise etc., and be difficult to realize from dynamic(al) correction on circuit, this is just very
It is easily caused the phase deviation causing between multi-phase clock, thus causing uncertainty in time domain and showing as the not true of amplitude
Qualitative, reduce attainable make an uproar bottom and corresponding quality factor, such as signal to noise ratio (SNR).Because multiphase clock phase error is to letter
Number reconstruction quality impact maximum, many has had further investigation with regard to the acquisition methods of multi-phase clock and correcting algorithm, such as
For producing the design of the delay-locked loop special IC of multi-phase clock, eliminate emphatically shake, reduce phase noise to carry
The precision of high multi-phase clock, in addition the Channel Mismatch bearing calibration of high time efficiency, when multiphase is carried out based on sinusoidal digital signal
Method of clock phase error correction etc., reaches, from algorithm level, the purpose reducing multiphase clock phase error, but this method meter
Calculation amount is big, difficulty is high, brings very big challenge to system design.
Obviously, many engineering researcies lay stress on generation end and the receiving terminal of multi-phase clock, but, in many high speed numbers
In word design system, clock transfer needs also exist for through complicated wiring and drive environment, if having ignored clock transmit process
The phase noise of middle introducing, this just greatly wastes the meticulous circuit design that end occurs, and also increases the calculation of receiving terminal simultaneously
Method corrects difficulty.
Content of the invention
The present invention is the difficult problem solving above prior art, there is provided a kind of realize high-precision phase position difference control multiphase when
Clock production method, the method is passed through to set up a controllable time delay circuit Lai Duige road clock signal during clock signal transmission
Phase place be corrected, be enable to realize high-precision control to the phase contrast between multi-phase clock.
For realizing above goal of the invention, employed technical scheme comprise that：
A kind of multi-phase clock production method realizing high-precision phase position difference control, is to make multi-phase clock produce circuit with difference
The form of sub-signal exports the equidistant clock signal of n road phase contrast, also resides in and makes n road clock signal pass through match circuit, difference
Transmission line is transmitted separately to carry out phasing in corresponding controllable time delay circuit, then by the n road clock signal of correction respectively
Transmit to driven moved end.
Preferably, described multi-phase clock generation circuit includes constant-temperature crystal oscillator, phase discriminator PFD, charge pump CP, loop filtering
LF, voltage controlled oscillator VCO, frequency divider DIVIDER/N and n road frequency divider Divider/ Φ, the wherein outfan of constant-temperature crystal oscillator with
The input one of phase discriminator PFD connects, the input one of the outfan one of phase discriminator PFD, outfan two and charge pump CP, input
End two connection, the outfan of charge pump CP is connected with the input of loop filtering LF, and the outfan of loop filtering LF is shaken with voltage-controlled
The control end swinging device VCO connects, and the outfan of voltage controlled oscillator VCO is connected with n road frequency divider Divider/ Φ, n road frequency divider
Divider/ Φ is connected with n road match circuit respectively；The outfan of voltage controlled oscillator VCO passes through frequency divider DIVIDER/N and mirror
The input two of phase device PFD connects；
Wherein constant-temperature crystal oscillator provides reference input F for phase discriminator PFDref, frequency divider DIVIDER/N is phase discriminator PFD offer
Feedback signal Flock；Phase discriminator PFD is according to reference input Fref, feedback signal FlockPhase relation act on charge pump CP, electricity
Lotus pump CP is according to reference input Fref, feedback signal FlockPhase contrast be converted into low-frequency d level Vctrl1；Low-frequency d level
Vctrl1Form control voltage V of voltage controlled oscillator VCO through loop filtering LFc(t), VcT () exports letter to voltage controlled oscillator VCO
Number frequency be controlled；On the one hand the signal of voltage controlled oscillator VCO output enters in the frequency divider Divider/ Φ of n road, is formed
The equidistant clock signal of the n road phase contrast of differential signalling form, on the other hand forms feedback letter after frequency divider DIVIDER/N
Number Flock.
Preferably, described controllable time delay circuit include inductance L1, inductance L2, inductance L3, inductance L4, inductance L5, inductance L6,
Resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, resistance R6, electric capacity C1, electric capacity C2, electric capacity C3, electric capacity C4, transfiguration two
Pole pipe D1, varactor D2, varactor D3, varactor D4, digital to analog converter DAC and VADJ voltage amplification electricity
Road；
Two of which difference transmission lines pass through inductance L1, inductance L2, inductance L3 and inductance L4, inductance L5, inductance L6 respectively
It is connected with driven moved end；Wherein one end of electric capacity C2 is connected with inductance L1, inductance L2, the negative electrode of the other end and varactor D1
Connect, the anode of varactor D1 is connected with the anode of varactor D3, the negative electrode of varactor D3 passes through electric capacity C3
It is connected with inductance L4, inductance L5, varactor D1, the anode of varactor D3 are grounded by resistance R3；The one of electric capacity C1
End is connected with inductance L2, inductance L3, and the other end is connected with the negative electrode of varactor D2, the anode of varactor D2 and transfiguration
The anode of diode D4 connects, and the negative electrode of varactor D4 is connected with inductance L5, inductance L6 by electric capacity C4, varactor
D2, the anode of varactor D4 are grounded by resistance R4；Described electric capacity C2, the negative electrode of varactor D1 pass sequentially through resistance
R1, resistance R2 are connected with electric capacity C1, varactor D2；Described electric capacity C3, the negative electrode of varactor D3 pass sequentially through resistance
R5, resistance R6 are connected with electric capacity C4, varactor D4；The outfan of described digital to analog converter DAC and VADJ voltage amplification electricity
The input on road connects, and the outfan of VADJ voltage amplifier circuit is respectively with resistance R1, resistance R2 and resistance R4, resistance R5 even
Connect；
Described when carrying out phasing using controllable time delay circuit, by digital to analog converter DAC export a program-controlled electric
Press and be amplified by VADJ voltage amplifier circuit, the voltage after amplification passes through resistance R1, resistance R2, resistance R5, resistance R6
Isolation, and act on varactor D1, varactor D2, varactor D3, varactor D4, make varactor
D1, varactor D2, varactor D3, the capacitance size of varactor D4 change, thus to differential signal
CLKI_m_P and CLKI_m_N carries out time delay fine setting, thus the correction of phase place.
Meanwhile, present invention also offers a kind of circuit applying above method, its specific scheme is as follows：
Produce circuit including multi-phase clock, described multi-phase clock produces circuit and includes n outfan, and multi-phase clock produces electricity
The n outfan on road exports phase contrast equidistant clock signal in n road in the form of differential signal, and described circuit also includes coupling
Each outfan that circuit, difference transmission lines and controllable time delay circuit, wherein multi-phase clock produce circuit passes sequentially through coupling electricity
Road, difference transmission lines and controllable time delay circuit are connected with driven moved end.
Preferably, described multi-phase clock generation circuit includes constant-temperature crystal oscillator, phase discriminator PFD, charge pump CP, loop filtering
LF, voltage controlled oscillator VCO, frequency divider DIVIDER/N and n road frequency divider Divider/ Φ, the wherein outfan of constant-temperature crystal oscillator with
The input one of phase discriminator PFD connects, the input one of the outfan one of phase discriminator PFD, outfan two and charge pump CP, input
End two connection, the outfan of charge pump CP is connected with the input of loop filtering LF, and the outfan of loop filtering LF is shaken with voltage-controlled
The control end swinging device VCO connects, and the outfan of voltage controlled oscillator VCO is connected with n road frequency divider Divider/ Φ, n road frequency divider
Divider/ Φ is connected with n road match circuit respectively；The outfan of voltage controlled oscillator VCO passes through frequency divider DIVIDER/N and mirror
The input two of phase device PFD connects.
Preferably, described controllable time delay circuit include inductance L1, inductance L2, inductance L3, inductance L4, inductance L5, inductance L6,
Resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, resistance R6, electric capacity C1, electric capacity C2, electric capacity C3, electric capacity C4, transfiguration two
Pole pipe D1, varactor D2, varactor D3, varactor D4, digital to analog converter DAC and VADJ voltage amplification electricity
Road；
Two of which difference transmission lines pass through inductance L1, inductance L2, inductance L3 and inductance L4, inductance L5, inductance L6 respectively
It is connected with driven moved end；Wherein one end of electric capacity C2 is connected with inductance L1, inductance L2, the negative electrode of the other end and varactor D1
Connect, the anode of varactor D1 is connected with the anode of varactor D3, the negative electrode of varactor D3 passes through electric capacity C3
It is connected with inductance L4, inductance L5, varactor D1, the anode of varactor D3 are grounded by resistance R3；The one of electric capacity C1
End is connected with inductance L2, inductance L3, and the other end is connected with the negative electrode of varactor D2, the anode of varactor D2 and transfiguration
The anode of diode D4 connects, and the negative electrode of varactor D4 is connected with inductance L5, inductance L6 by electric capacity C4, varactor
D2, the anode of varactor D4 are grounded by resistance R4；Described electric capacity C2, the negative electrode of varactor D1 pass sequentially through resistance
R1, resistance R2 are connected with electric capacity C1, varactor D2；Described electric capacity C3, the negative electrode of varactor D3 pass sequentially through resistance
R5, resistance R6 are connected with electric capacity C4, varactor D4；The outfan of described digital to analog converter DAC and VADJ voltage amplification electricity
The input on road connects, and the outfan of VADJ voltage amplifier circuit is respectively with resistance R1, resistance R2 and resistance R4, resistance R5 even
Connect.
The method that the present invention provides or circuit pass through to control the controllable time delay circuit realiration of clock transmitting circuit that clock is passed
The clock phase skew occurring during sending compensates, and realizes the control to high-precision phase position difference.Meanwhile, with constant-temperature crystal oscillator
(TCXO) produce the reference clock signal F of high stabilityref, the output letter of high stability, low jitter is obtained by PHASE-LOCKED LOOP PLL TECHNIQUE
Number fout, obtain the equidistant clock signal of phase contrast through pre- frequency dividing, phase place coarse adjustment, because differential signal has than single-ended signal
Preferably common mode rejection ratio, the features such as capacity of resisting disturbance is higher, the method that the present invention provides clock signal by single-ended switch to poor
Sub-signal, by high-speed differential signal termination technology, makes clock be sent to receiving terminal.Take in specific implementation process simultaneously
Isometric, equal space line design and impedance control measure, reduce the time delay that high speed signal runs in transmit process, anti-as far as possible
Penetrate, crosstalk the problems such as it is ensured that the integrity of high speed signal, high-speed clock signal reaches receiving terminal by transmission line, controlled prolongs
When circuit control the capacitance size of varactor to change delay time by controlling the DAC voltage signal that exports and amplify, right
The offset error producing in multi-phase clock generation and transmitting procedure carries out automatic fine tuning, achieves high speed multi-phase clock signal with this
High-precision phase position difference correction.
Brief description
Fig. 1 produces the structural representation of circuit for multi-phase clock.
Tu2Wei tetra- road phase contrast is 90 ° of multi-phase clock oscillogram.
Fig. 3 is the structural representation of circuit.
Fig. 4 is the structural representation of controllable time delay circuit.
Fig. 5 is delay circuit phase contrast S21Analogous diagram.
Fig. 6 is the error performance comparison diagram of ADC before and after clock improvement.
Specific embodiment
Being for illustration only property of accompanying drawing illustrates it is impossible to be interpreted as the restriction to this patent；
Below in conjunction with drawings and Examples, the present invention is further elaborated.
Embodiment 1
Multi-phase clock produces the structure of circuit as shown in figure 1, it includes constant-temperature crystal oscillator, phase discriminator PFD, charge pump CP, ring
Road filtering LF, voltage controlled oscillator VCO, frequency divider DIVIDER/N and n road frequency divider Divider/ Φ, wherein constant-temperature crystal oscillator is defeated
Go out end to be connected with the input one of phase discriminator PFD, the input of the outfan one of phase discriminator PFD, outfan two and charge pump CP
First, input two connects, and the outfan of charge pump CP is connected with the input of loop filtering LF, the outfan of loop filtering LF with
The control end of voltage controlled oscillator VCO connects, and the outfan of voltage controlled oscillator VCO is connected with n road frequency divider Divider/ Φ, n road
Frequency divider Divider/ Φ is connected with n road match circuit (matchn as in Fig. 3) respectively；The outfan of voltage controlled oscillator VCO
It is connected with the input two of phase discriminator PFD by frequency divider DIVIDER/N.
In listing scheme, provide, for phaselocked loop, the reference that phase jitter is low, noise is little and degree of stability is high using constant-temperature crystal oscillator
Input Fref, PFD detection FrefWith feedback signal FlockPhase relation and act on charge pump CP, be converted to low according to phase contrast
Frequency DC level Vctrl1, this signal is through control voltage V of loop filtering LF formation voltage controlled oscillatorcT (), exports to agitator
The frequency of signal is implemented to control.If the gain of PFD is Kpd, the transfer function of LF is F (s), and the gain of VCO is Kvco, phaselocked loop
θ is used at input and output phase angle respectivelyinAnd θoutRepresent, then the small-signal transmission function of PLL is：
Output signal foutObtain the multi-phase clock signal of certain phase contrast by frequency dividing and phase place coarse adjustment Divider, with item
As a example four road multi-phase clocks of mesh engineer applied, as shown in Fig. 2 being compensated by the out of phase configuring each frequency divider, thus
Realize the phase delays of different outputs, when meeting fout=n*fclkWhen (diagram n=4), Δ t=1/fout, wherein Δ t is current
Clock signal is poor with the time interval of input signal.The output clk1 of multi-phase clock is finally completed using differential pair mode,
Clk2 ..., clkn.
The structural representation of circuit shown in Fig. 3, clock transfer take near-end termination method, Match1,
Match2 ..., Matchn carry out output matching to n road clock, reduce the signaling reflex of outfan, the differential clocks letter after coupling
Number it is sent to far-end by differential lines, using SigXplorer, multi-phase clock is entered with line delay setting, in design on board level, fully
, it is ensured that clk1, complete ground level under clk2 ..., clkn signal, using SI9000 to height for the return path considering high speed signal
Fast cabling carries out live width, line-spacing budget and circuit board laminate setting it is ensured that high-speed-differential line CLKI_i_P/CLKI_i_N
100 Ω differential impedances control requirement.Clock exports through phase place coarse adjustment from source, by matched termination, is sent to by transmission line
Driven moved end, because by device itself and circuit environmental effect, the multi-phase clock of coarse adjustment output is easily subject to plate level transmit process
Impact, high-speed clock signal thus produces the deflection of shake and phase place, therefore takes controllable delay circuit P1, and P2 ..., Pn are to many
Phase clock carries out fine tuning phase, is finally reached the high-precision purpose of phase contrast.
The structure of controllable time delay circuit is as shown in Figure 4.It include inductance L1, inductance L2, inductance L3, inductance L4, inductance L5,
Inductance L6, resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, resistance R6, electric capacity C1, electric capacity C2, electric capacity C3, electric capacity C4,
Varactor D1, varactor D2, varactor D3, varactor D4, digital to analog converter DAC and VADJ voltage are put
Big circuit；
Two of which difference transmission lines pass through inductance L1, inductance L2, inductance L3 and inductance L4, inductance L5, inductance L6 respectively
It is connected with driven moved end；Wherein one end of electric capacity C2 is connected with inductance L1, inductance L2, the negative electrode of the other end and varactor D1
Connect, the anode of varactor D1 is connected with the anode of varactor D3, the negative electrode of varactor D3 passes through electric capacity C3
It is connected with inductance L4, inductance L5, varactor D1, the anode of varactor D3 are grounded by resistance R3；The one of electric capacity C1
End is connected with inductance L2, inductance L3, and the other end is connected with the negative electrode of varactor D2, the anode of varactor D2 and transfiguration
The anode of diode D4 connects, and the negative electrode of varactor D4 is connected with inductance L5, inductance L6 by electric capacity C4, varactor
D2, the anode of varactor D4 are grounded by resistance R4；Described electric capacity C2, the negative electrode of varactor D1 pass sequentially through resistance
R1, resistance R2 are connected with electric capacity C1, varactor D2；Described electric capacity C3, the negative electrode of varactor D3 pass sequentially through resistance
R5, resistance R6 are connected with electric capacity C4, varactor D4；The outfan of described digital to analog converter DAC and VADJ voltage amplification electricity
The input on road connects, and the outfan of VADJ voltage amplifier circuit is respectively with resistance R1, resistance R2 and resistance R4, resistance R5 even
Connect；
Differential signal CLKI_m_P and CLKI_m_N enters the delay circuit being made up of LCR of a high degree of symmetry, this electricity
The time delay nominal value on road, depending on first cycle time of LCR damped oscillation
For reaching the purpose that automatically controls of time delay, then need to change the parameter of LCR, because resistance and inductance parameters change method
More difficult, so being taken through changing, in figure exports a program-controlled voltage and by VADJ electricity by digital to analog converter (DAC)
Pressure amplifying circuit is amplified, and the voltage after amplification passes through R1, R2 and the R5 of big resistance such as 100K, and R6 isolates, and acts on change
Hold D1, D2 and the D3 of diode BB184, D4, and time delay fine setting is carried out to differential signal CLKI_m_P and CLKI_m_N, by
In the high symmetry ensureing CLKI_m_P and CLKI_m_N transmitting circuit, then the time delay controlling through ADC is also of substantially equal
's.BB184 when control voltage 1～10V changes, capacitance DcExcursion is 2pF～14pF, it is now assumed that the clock of system transfers
When signal frequency is 500MHz, under meeting impedance matching requirements, take L1=L3=L4=L6=2.2nH, L2=L2=
When 5.6nH, C1=C2=C3=C4=6.8pF, time delay and Phase delay corresponding to circuit are as shown in Figure 5 respectively.When
Electric capacity when 2pF～14pF changes, corresponding transmission delay TdFor
I.e. controlled transmission delay is 106～280ps.
Next step, carries out the correction of multi-phase clock, during system initialization, makes control transfiguration taking four road multi-phase clocks as a example
The DAC voltage of diode is in midpoint 5.5V, and corresponding capacitor's capacity 8pF, with the clock signal of first via zero phase
DIVIDER0 as the reference signal of multi-phase clock, simultaneously as the global clock signal of FPGA.The first step, when carrying out
The correction of clock DIVIDER2, when FPGA is in clock signal next one trailing edge triggering, detects DIVIDER2's simultaneously
Rising edge, and judge the sequencing of both triggerings, if the rising edge triggering of DIVIDER2 declines early than DIVIDER0 is next
Along triggering, then control pga circuit output 5.5+V (θ), wherein V (θ) is the relation adjusting with DAC voltage with regard to phase place
Function, approximately can be obtained by multiple measurement LC delay circuit sensitivity, if the rising edge triggering of DIVIDER2 lags behind
DIVIDER0 next one trailing edge triggering, then control pga circuit output 5.5-V (θ), arrange a threshold value in programming,
So circulation is adjusted, until feedback loop stable, then complete phase place accurate delay in 90 °.According to method same above, correct
DIVIDER1 and DIVIDER3, phase contrast is 90 °.Second step, now consider clock DIVIDER1, first DIVIDER0 be divided into A,
B two-way, with DIVIDER0_A triggering any one rising edge as reference, monitoring after this DIVIDER1, DIVIDER2 with
DIVIDER3 triggering first rising edge, when detecting the rising edge of DIVIDER0_A again, if triggering time prior to
During DIVIDER0_B, then pga circuit output 5.5+V'(θ)/2 (because DIVIDER1 and DIVIDER3 occur identical
Relative time delay), if the time of triggering when DIVIDER0_B, pga circuit exports 5.5-V'(θ)/2 to controlled
Delay circuit carries out feedback regulation, then can complete 90 ° of phase adjusted of DIVIDER1 and DIVIDER0, with the method for the first step again
Secondary regulation DIVIDER3, is finally completed DIVIDER0 and DIVIDER1,90 ° of phase contrast between DIVIDER2, DIVIDER3,
180 °, 270 ° of regulation.For improving precision further, three above step can also be circulated, specific requirement visible system calculates
Depending on amount and design requirement.
The present invention applies in high speed analog-to-digital conversion time-interleaved (Time Interleave) ADC, due to clock signal
Improve, the performance such as SNR of ADC, SFDR can be obviously improved, sampling error reduces, as shown in fig. 6, the method can improve
Multiphase clock phase difference precision, has very big reference significance in high-frequency clock design circuit.
Obviously, the above embodiment of the present invention is only intended to clearly illustrate example of the present invention, and is not right
The restriction of embodiments of the present invention.For those of ordinary skill in the field, also may be used on the basis of the above description
To make other changes in different forms.There is no need to be exhaustive to all of embodiment.All this
Any modification, equivalent and improvement made within the spirit of invention and principle etc., should be included in the claims in the present invention
Protection domain within.
Claims (6)
1. a kind of multi-phase clock production method realizing high-precision phase position difference control, is to make multi-phase clock produce circuit with difference
The form of signal export the equidistant clock signal of n road phase contrast it is characterised in that：Also reside in and make n road clock signal pass through coupling
Circuit, difference transmission lines are transmitted separately to carry out phasing in corresponding controllable time delay circuit, then by the n road clock of correction
Signal is transmitted separately to driven moved end.
2. according to claim 1 realize high-precision phase position difference control multi-phase clock production method it is characterised in that：Institute
State multi-phase clock generation circuit to include constant-temperature crystal oscillator, phase discriminator PFD, charge pump CP, loop filtering LF, voltage controlled oscillator VCO, divide
Frequency device DIVIDER/N and n road frequency divider Divider/ Φ, the wherein outfan of constant-temperature crystal oscillator and the input one of phase discriminator PFD
Connect, the outfan one of phase discriminator PFD, outfan two are connected with the input one of charge pump CP, input two, charge pump CP
Outfan is connected with the input of loop filtering LF, and the outfan of loop filtering LF is connected with the control end of voltage controlled oscillator VCO,
The outfan of voltage controlled oscillator VCO is connected with n road frequency divider Divider/ Φ, n road frequency divider Divider/ Φ respectively with n road
Distribution road connects；The outfan of voltage controlled oscillator VCO is connected with the input two of phase discriminator PFD by frequency divider DIVIDER/N；
Wherein constant-temperature crystal oscillator provides reference input F for phase discriminator PFDref, frequency divider DIVIDER/N is phase discriminator PFD offer feedback
Signal Flock；Phase discriminator PFD is according to reference input Fref, feedback signal FlockPhase relation act on charge pump CP, charge pump
CP is according to reference input Fref, feedback signal FlockPhase contrast be converted into low-frequency d level Vctrl1；Low-frequency d level Vctrl1
Form control voltage V of voltage controlled oscillator VCO through loop filtering LFc(t), VcT () is to voltage controlled oscillator VCO output signal
Frequency is controlled；On the one hand the signal of voltage controlled oscillator VCO output enters in the frequency divider Divider/ Φ of n road, forms difference
The equidistant clock signal of the n road phase contrast of signal form, on the other hand forms feedback signal after frequency divider DIVIDER/N
Flock.
3. according to claim 1 realize high-precision phase position difference control multi-phase clock production method it is characterised in that：Institute
State controllable time delay circuit and include inductance L1, inductance L2, inductance L3, inductance L4, inductance L5, inductance L6, resistance R1, resistance R2, electricity
Resistance R3, resistance R4, resistance R5, resistance R6, electric capacity C1, electric capacity C2, electric capacity C3, electric capacity C4, varactor D1, varactor
D2, varactor D3, varactor D4, digital to analog converter DAC and VADJ voltage amplifier circuit；
Two of which difference transmission lines pass sequentially through inductance L1, inductance L2, inductance L3 and inductance L4, inductance L5, inductance L6 respectively
It is connected with driven moved end；Wherein one end of electric capacity C2 is connected with inductance L1, inductance L2, the negative electrode of the other end and varactor D1
Connect, the anode of varactor D1 is connected with the anode of varactor D3, the negative electrode of varactor D3 passes through electric capacity C3
It is connected with inductance L4, inductance L5, the anode of varactor D1, the anode of varactor D3 are grounded by resistance R3；Electric capacity
One end of C1 is connected with inductance L2, inductance L3, and the other end is connected with the negative electrode of varactor D2, the anode of varactor D2
It is connected with the anode of varactor D4, the negative electrode of varactor D4 is connected with inductance L5, inductance L6 by electric capacity C4, transfiguration
The anode of diode D2, the anode of varactor D4 are grounded by resistance R4；Described electric capacity C2, the negative electrode of varactor D1
Pass sequentially through resistance R1, resistance R2 is connected with the negative electrode of electric capacity C1, varactor D2；Described electric capacity C3, varactor D3
Negative electrode pass sequentially through resistance R5, resistance R6 is connected with the negative electrode of electric capacity C4, varactor D4；Described digital to analog converter DAC
Outfan be connected with the input of VADJ voltage amplifier circuit, the outfan of VADJ voltage amplifier circuit respectively with resistance R1,
Resistance R2 and resistance R4, resistance R5 connect；
Described when carrying out phasing using controllable time delay circuit, by digital to analog converter DAC export a program-controlled voltage simultaneously
It is amplified by VADJ voltage amplifier circuit, the voltage after amplification passes through resistance R1, resistance R2, resistance R5, resistance R6 isolation,
And act on varactor D1, varactor D2, varactor D3, varactor D4, make varactor D1, change
Appearance diode D2, varactor D3, the capacitance size of varactor D4 change, thus to differential signal CLKI_m_P
Carry out time delay fine setting with CLKI_m_N, thus the correction of phase place.
4. a kind of circuit according to claims 1 to 3 any one methods described it is characterised in that：Produce electricity including multi-phase clock
Road, described multi-phase clock produces circuit and includes n outfan, and multi-phase clock produces n outfan of circuit with differential signal
Form exports the equidistant clock signal of n road phase contrast, and described circuit also includes match circuit, difference transmission lines and controllable time delay
Each outfan that circuit, wherein multi-phase clock produce circuit passes sequentially through match circuit, difference transmission lines and controllable time delay electricity
Road is connected with driven moved end.
5. circuit according to claim 4 it is characterised in that：Described multi-phase clock produces circuit and includes constant-temperature crystal oscillator, mirror
Phase device PFD, charge pump CP, loop filtering LF, voltage controlled oscillator VCO, frequency divider DIVIDER/N and n road frequency divider Divider/
The outfan of Φ, wherein constant-temperature crystal oscillator is connected with the input one of phase discriminator PFD, the outfan one of phase discriminator PFD, outfan two
It is connected with the input one of charge pump CP, input two, the outfan of charge pump CP is connected with the input of loop filtering LF, ring
The outfan that road filters LF is connected with the control end of voltage controlled oscillator VCO, the outfan of voltage controlled oscillator VCO and n road frequency divider
Divider/ Φ connects, and n road frequency divider Divider/ Φ is connected with n road match circuit respectively；The outfan of voltage controlled oscillator VCO
It is connected with the input two of phase discriminator PFD by frequency divider DIVIDER/N.
6. circuit according to claim 4 it is characterised in that：Described controllable time delay circuit includes inductance L1, inductance L2, electricity
Sense L3, inductance L4, inductance L5, inductance L6, resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, resistance R6, electric capacity C1, electricity
Appearance C2, electric capacity C3, electric capacity C4, varactor D1, varactor D2, varactor D3, varactor D4, digital-to-analogue turn
Parallel operation DAC and VADJ voltage amplifier circuit；
Two of which difference transmission lines pass through inductance L1, inductance L2, inductance L3 and inductance L4, inductance L5, inductance L6 and are subject to respectively
Drive end connects；Wherein one end of electric capacity C2 is connected with inductance L1, inductance L2, and the other end is connected with the negative electrode of varactor D1
Connect, the anode of varactor D1 is connected with the anode of varactor D3, the negative electrode of varactor D3 pass through electric capacity C3 with
Inductance L4, inductance L5 connect, and varactor D1, the anode of varactor D3 are grounded by resistance R3；One end of electric capacity C1
It is connected with inductance L2, inductance L3, the other end is connected with the negative electrode of varactor D2, the anode of varactor D2 and transfiguration two
The anode of pole pipe D4 connects, and the negative electrode of varactor D4 is connected with inductance L5, inductance L6 by electric capacity C4, varactor
D2, the anode of varactor D4 are grounded by resistance R4；Described electric capacity C2, the negative electrode of varactor D1 pass sequentially through resistance
R1, resistance R2 are connected with electric capacity C1, varactor D2；Described electric capacity C3, the negative electrode of varactor D3 pass sequentially through resistance
R5, resistance R6 are connected with electric capacity C4, varactor D4；The outfan of described digital to analog converter DAC and VADJ voltage amplification electricity
The input on road connects, and the outfan of VADJ voltage amplifier circuit is respectively with resistance R1, resistance R2 and resistance R4, resistance R5 even
Connect.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610818245.4A CN106385252A (en) | 2016-09-12 | 2016-09-12 | Multi-phase clock generation method and circuit for realizing high precision phase difference control |
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| CN201610818245.4A CN106385252A (en) | 2016-09-12 | 2016-09-12 | Multi-phase clock generation method and circuit for realizing high precision phase difference control |
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| CN109101074A (en) * | 2018-07-24 | 2018-12-28 | 中国电子科技集团公司第二十四研究所 | A kind of multi-phase clock generative circuit that random perturbation is added |
| CN109600126A (en) * | 2018-12-06 | 2019-04-09 | 中国科学院微电子研究所 | A kind of clock generator |
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