CN106383624A - Array substrate, display panel and driving method thereof, and display device - Google Patents
Array substrate, display panel and driving method thereof, and display device Download PDFInfo
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- CN106383624A CN106383624A CN201610947720.8A CN201610947720A CN106383624A CN 106383624 A CN106383624 A CN 106383624A CN 201610947720 A CN201610947720 A CN 201610947720A CN 106383624 A CN106383624 A CN 106383624A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Human Computer Interaction (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention provides an array substrate, a display panel and a driving method thereof, and a display device. A first data line, a second data line, a third data line and a fourth data line of an i-th data line unit of the array substrate are respectively electrically connected with i-th switch units of a first multiplex circuit, a second multiplex circuit, a third multiplex circuit and a fourth multiplex circuit in a one-to-one corresponding manner; accordingly, an integrated circuit unit transmits first polarity signals to the i-th switch units of the first multiplex circuit and the second multiplex circuit, and transmits second polarity signals to the i-th switch units of the third multiplex circuit and the fourth multiplex circuit, namely two lines of inverse driving modes are achieved. The array substrate, the display panel and the display device provided by the invention only provides the signals of one kind of polarity to the same multiplex circuit unit within a frame of scanning time, so that the display panel and the display device are low in power consumption.
Description
Technical field
The present invention relates to display device technical field, more particularly, it relates to a kind of array base palte, display floater and its drive
Dynamic method and display device.
Background technology
With reference to Fig. 1, Fig. 1 is the planar structure schematic diagram of array base palte in a kind of existing self-tolerant touch-control display panel,
This array base palte includes a plurality of gate line 10, multiple data line group 11, multiple pixel cell 12 in array arrangement and multiple
Touch control electrode 13.Wherein, each data line group 11 includes three data line unit 11a, 11b and 11c, each data line unit again
Include neighbouring the first data wire 110 being arranged in the same row gap between pixel cell 12 and the second data wire 111, often again
Individual touch control electrode 13 is all passed through a touch-control lead 130 and is connected with touch drive circuit, and this touch drive circuit is used for touch-control
Electrode 13 inputs touching signals, carries out the detection of position of touch.And, in order to avoid the signal in data wire is to touch-control lead
Touching signals in 130 interfere, and touch-control lead 130 is provided separately within a row gap between pixel cell 12.
As shown in figure 1, this array base palte also includes multiple multiplex circuit groups A, it is multiple that each multiplex circuit group A includes first again
With circuit unit A1 and the second multiplex circuit unit A2, each multiplex circuit unit includes three switch K1 to K3 again, and first is multiple
It is connected, switchs K2 and data line unit with the first data wire 110 in data line unit 11a with the switch K1 in circuit unit A1
The first data wire 110 in 11b is connected, switch K3 is connected with the first data wire 110 in data line unit 11c, the second multiplexing
Switch K1 in circuit unit A2 is connected, switchs K2 and data line unit with the second data wire 111 in data line unit 11a
The second data wire 111 in 11b is connected, switch K3 is connected with the second data wire 111 in data line unit 11c.
In order to avoid phase between opposite polarity signal in the first data wire 110 of neighbouring setting and the second data wire 111
The mutually extra power consumption of interference, initiation, this self-tolerant touch-control display panel is driven using the type of drive of two column inversions, such as schemes
Shown in 2, Fig. 2 is the signal timing diagram of the array base palte shown in Fig. 1, and integrated circuit unit 14 is in the first of a vertical interval
Section T10 provides positive signal+TX to the switch K1 of all multiplex circuit units, and control line CK1 controls all switch K1 conductings,
Positive signal+TX is made to transmit the first data wire 110 to data line unit 11a and the second data wire 111；Integrated circuit list
Unit 14 provides minus polarity signal-TX, control in the second period T11 of a vertical interval to the switch K2 of all multiplex circuit units
Line CK2 processed controls all switch K2 conductings, makes minus polarity signal-TX transmit the first data wire 110 to data line unit 11b
With the second data wire 111；Integrated circuit unit 14 a vertical interval the 3rd period T12 to all multiplex circuit units
Switch K3 provide positive signal+TX, and control line CK3 controls all switch K3 conductings, so that positive signal+TX is transmitted to data
The first data wire 110 in line unit 11c and the second data wire 111.But, due in a vertical interval, integrated circuit
Unit 14 needs to carry out the switching of positive-negative polarity signal twice during providing signal to same multiplex circuit unit, therefore, leads
Cause integrated circuit unit 14 signal polarity switching frequency higher, and then lead to touch-control display panel power consumption higher.
Content of the invention
In view of this, the invention provides a kind of array base palte, display floater and its driving method and display device, to solve
The certainly higher problem of the signal polarity switching frequency of integrated circuit unit in prior art.
For achieving the above object, the present invention provides following technical scheme：
A kind of array base palte, including：
The multiple data line group being arranged in order in the first direction, each described data line group include along described first direction according to
To the n-th data cell, each described data line unit includes arranging successively along described first direction 1st data line unit of secondary arrangement
First data wire of row, the second data wire, the 3rd data wire and the 4th data wire；
The multiple multiplex circuit groups being arranged in order along described first direction, each described multiplex circuit group includes along described
The first multiplex circuit unit that first direction is arranged in order, the second multiplex circuit unit, the 3rd multiplex circuit unit and the 4th are multiple
With circuit unit, described first multiplex circuit unit, the second multiplex circuit unit, the 3rd multiplex circuit unit and the 4th multiplexing electricity
Road unit all includes the 1st switch element being arranged in order along described first direction to the n-th switch element；Wherein, each described number
According to the first data wire of the i-th data line unit in line group, the second data wire, the 3rd data wire and the 4th data wire respectively with right
The first multiplex circuit unit in the described multiplex circuit group answered, the second multiplex circuit unit, the 3rd multiplex circuit unit, the 4th
I-th switch element of multiplex circuit unit corresponds electrical connection；
Integrated circuit unit, described integrated circuit unit is electrically connected with described i-th switch element, and described integrated circuit list
The first polar signal is transmitted to the i-th switch element of described first multiplex circuit unit and described second multiplex circuit unit in unit,
The i-th switch element to described 3rd multiplex circuit unit and described 4th multiplex circuit unit transmits the second polar signal, institute
State the first polarity and the opposite polarity of described second polarity；
Many control lines, described first multiplex circuit unit, the second multiplex circuit unit, the 3rd multiplex circuit unit and
Described 1st switch element to the n-th switch element of four multiplex circuit units is electrically connected from different described control lines respectively, and institute
State the described of the first multiplex circuit unit, the second multiplex circuit unit, the 3rd multiplex circuit unit and the 4th multiplex circuit unit
I-th switch element is electrically connected with same described control line；
Wherein, n is the integer more than 1；I is any integer between 1 to n, including endpoint value.
A kind of display floater, including array base palte as above.
A kind of driving method of display floater, is applied to display floater as above, including：
To the first multiplex circuit unit of arbitrary multiplex circuit group and the i-th switch element transmission of the second multiplex circuit unit
First polar signal, single to the 3rd multiplex circuit unit of described multiplex circuit group and the i-th switch of the 4th multiplex circuit unit
Unit's transmission the second polar signal, and control the i-th switch element of described first multiplex circuit unit by described first polar signal
Transmit the first data wire of the i-th data line unit to respective data lines group, control the i-th of described second multiplex circuit unit to open
Close unit to transmit described first polar signal to the second data wire of described i-th data line unit, control described 3rd multiplexing
Described second polar signal is transmitted to the 3rd data wire of described i-th data line unit, control by the i-th switch element of circuit unit
The i-th switch element making described 4th multiplex circuit unit transmits described second polar signal to described i-th data line unit
The 4th data wire, wherein, the opposite polarity of described first polarity and described second polarity.
A kind of display device, including display floater as above.
Compared with prior art, technical scheme provided by the present invention has advantages below：
The driving method of display device provided by the present invention, display floater, array base palte and display floater, each data
Line group includes the 1st data line unit being arranged in order in the first direction to the n-th data cell, and each data line unit is included along
The first data wire, the second data wire, the 3rd data wire and the 4th data wire that one direction is arranged in order, each multiplex circuit group
Including the first multiplex circuit unit being arranged in order, the second multiplex circuit unit, the 3rd multiplex circuit unit and the 4th multiplexing electricity
Road unit, the first data wire of the i-th data line unit in each data line group, the second data wire, the 3rd data wire and the 4th
Data wire respectively with the first multiplex circuit unit in a corresponding multiplex circuit group, the second multiplex circuit unit, the 3rd multiple
Correspond electrical connection with the i-th switch element of circuit unit, the 4th multiplex circuit unit, based on this, integrated circuit unit exists
To i-th switch element transmission the first polarity letter of the first multiplex circuit unit and the second multiplex circuit unit in one vertical interval
Number, transmit the second polar signal to the i-th switch element of the 3rd multiplex circuit unit and the 4th multiplex circuit unit, you can realize
The type of drive of two column inversions.Because integrated circuit unit only provides one to same multiplex circuit unit in a vertical interval
The signal of kind of polarity, therefore, the signal polarity switching frequency of integrated circuit unit relatively low so that display floater and display device
Power consumption is relatively low.
Brief description
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
Have technology description in required use accompanying drawing be briefly described it should be apparent that, drawings in the following description be only this
Inventive embodiment, for those of ordinary skill in the art, on the premise of not paying creative work, can also basis
The accompanying drawing providing obtains other accompanying drawings.
Fig. 1 is the planar structure schematic diagram of array base palte in a kind of existing self-tolerant touch-control display panel；
Fig. 2 is the signal timing diagram of the array base palte shown in Fig. 1；
Fig. 3 is a kind of planar structure schematic diagram of array base palte provided in an embodiment of the present invention；
Fig. 4 is the signal timing diagram of the array base palte shown in Fig. 3；
Fig. 5 is the planar structure schematic diagram of another kind array base palte provided in an embodiment of the present invention；
Fig. 6 is the signal timing diagram of the array base palte shown in Fig. 5；
Fig. 7 is the planar structure schematic diagram of another array base palte provided in an embodiment of the present invention；
Fig. 8 is the enlarged drawing of the first multiplex circuit unit B 1 in Fig. 7；
Fig. 9 is the concrete structure schematic diagram of the array base palte shown in Fig. 3；
Figure 10 is the cross-sectional view along AA ' line of cut for the array base palte shown in Fig. 9.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation description is it is clear that described embodiment is only a part of embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of not making creative work
Embodiment, broadly falls into the scope of protection of the invention.
Embodiments provide a kind of array base palte, as shown in figure 3, Fig. 3 is one kind provided in an embodiment of the present invention
The planar structure schematic diagram of array base palte, this array base palte includes multiple data line group S, the edge that X in the first direction is arranged in order
Multiple multiplex circuit groups B, integrated circuit unit 20 and the Duo Gen control line being arranged in order.It should be noted that the present embodiment
Only taking one group of data line group S and one group of multiplex circuit group B as a example illustrate in accompanying drawing, other data line group S and multiplex circuit
The annexation of group B is identical with the annexation of data line group S shown in the present embodiment accompanying drawing and multiplex circuit group B, here
Repeat no more.
In the present embodiment, each data line group S includes the 1st data line unit that X in the first direction is arranged in order to the n-th number
According to unit, wherein, n is the integer more than 1.Optionally, n be equal to 3, or, n be equal to 2.So that n is equal to 3 as a example illustrate, such as
Shown in Fig. 3, data line group S includes the 1st data line unit S1 that X in the first direction is arranged in order to the 3rd data cell S3, and every
Individual data line unit include again the first data wire a, the second data wire b, the 3rd data wire c that X in the first direction is arranged in order and
4th data wire d.
The first multiplex circuit unit B 1 that each multiplex circuit group B includes being arranged in order, the second multiplex circuit unit B 2,
3rd multiplex circuit unit B 3 and the 4th multiplex circuit unit B 4, and the inclusion of each multiplex circuit unit is arranged in order the 1st
Switch element is to the n-th switch element.As shown in figure 3, each multiplex circuit unit includes the 1st switch element T1 being arranged in order extremely
3rd switch element T3.
In the present embodiment, in each data line group S, data wire is corresponding with the switch element in multiplex circuit group B even
Connect.Wherein, the first data wire a of the i-th data line unit in each data line group S, the second data wire b, the 3rd data wire c and
4th data wire d respectively with the first multiplex circuit unit B 1 in corresponding multiplex circuit group B, the second multiplex circuit unit
B2, the 3rd multiplex circuit unit B 3, the i-th switch element of the 4th multiplex circuit unit B 4 correspond electrical connection.Wherein, i is 1
Any integer to n, including endpoint value.
Specifically, as shown in figure 3, in the first data wire a and the first multiplex circuit unit B 1 in the 1st data line unit S1
The 1st switch element T1 electrical connection, the second data wire b and the 1st of the second multiplex circuit unit B 2 the in the 1st data line unit S1
Switch element T1 electrically connects, the 1st switch of the 3rd data wire c in the 1st data line unit S1 and the 3rd multiplex circuit unit B 3
Unit T1 electrical connection, the 4th data wire d in the 1st data line unit S1 and the 1st switch element of the 4th multiplex circuit unit B 4
T1 electrically connects；
The 2nd switch element T2 electricity in the first data wire a and the first multiplex circuit unit B 1 in 2nd data line unit S2
Connect, the second data wire b in the 2nd data line unit S2 is electrically connected with the 2nd switch element T2 of the second multiplex circuit unit B 2,
The 3rd data wire c in 2nd data line unit S2 is electrically connected with the 2nd switch element T2 of the 3rd multiplex circuit unit B 3, the 2nd number
Electrically connect with the 2nd switch element T2 of the 4th multiplex circuit unit B 4 according to the 4th data wire d in line cell S 2；
The 3rd switch element T3 electricity in the first data wire a and the first multiplex circuit unit B 1 in 3rd data line unit S3
Connect, the second data wire b in the 3rd data line unit S3 is electrically connected with the 3rd switch element T3 of the second multiplex circuit unit B 3,
The 3rd data wire c in 3rd data line unit S3 is electrically connected with the 3rd switch element T3 of the 3rd multiplex circuit unit B 3, the 3rd number
Electrically connect with the 3rd switch element T3 of the 4th multiplex circuit unit B 4 according to the 4th data wire d in line cell S 3.
In the present embodiment, integrated circuit unit 20 is electrically connected with the i-th switch element, and this integrated circuit unit 20 is to first
I-th switch element of multiplex circuit unit B 1 and the second multiplex circuit unit B 2 transmits the first polar signal, to the 3rd multiplexing electricity
I-th switch element of road unit B 3 and the 4th multiplex circuit unit B 4 transmits the second polar signal, the first polar signal and second
The opposite polarity of polar signal.
Wherein, during the driving of integrated circuit unit 20, display floater need to be controlled to carry out frame reversion, to avoid liquid crystal
The polarization of molecule, based on this, in a vertical interval, the first polar signal of integrated circuit unit 20 output is believed for positive polarity
Number, the second polar signal be minus polarity signal；In next vertical interval, the first polarity letter of integrated circuit unit 20 output
Number for minus polarity signal, the second polar signal be positive signal.
In the present embodiment, the first multiplex circuit unit B 1, the second multiplex circuit unit B 2, the 3rd multiplex circuit unit B 3 and
1st switch element to the n-th switch element of the 4th multiplex circuit unit B 4 is electrically connected from different control lines respectively, and first is multiple
Opened with the i-th of circuit unit B 1, the second multiplex circuit unit B 2, the 3rd multiplex circuit unit B 3 and the 4th multiplex circuit unit B 4
Close unit to electrically connect with same control line.
As shown in figure 3, multiple control lines include control line CK1 to CK3, wherein, the first multiplex circuit unit B 1, second is multiple
With the 1st switch element T1 of circuit unit B 2, the 3rd multiplex circuit unit B 3 and the 4th multiplex circuit unit B 4 all with same
Control line CK1 electrically connects, the first multiplex circuit unit B 1, the second multiplex circuit unit B 2, the 3rd multiplex circuit unit B 3 and the
2nd switch element T2 of four multiplex circuit unit B 4 is electrically connected with same control line CK2, the first multiplex circuit unit B 1,
3rd switch element T3 of the second multiplex circuit unit B 2, the 3rd multiplex circuit unit B 3 and the 4th multiplex circuit unit B 4 all with
Same control line CK3 electrical connection.
Based on the structure shown in Fig. 3, with reference to Fig. 4, Fig. 4 is the signal timing diagram of the array base palte shown in Fig. 3, sweeps in a frame
Retouch the first period T10 of time, integrated circuit unit 20 is to the first multiplex circuit unit B 1 and the second multiplex circuit unit B 2
1st switch element T1 transmit the first polar signal+TX, to the 3rd multiplex circuit unit B 3 and the 4th multiplex circuit unit B 4 the
1 switch element T1 transmits the second polar signal-TX, and control line CK1 passes through to input control signal to all of 1st switch element T1
Control the 1st switch element T1 conducting of all multiplex circuit units, so that the 1st switch element T1 of the first multiplex circuit unit B 1 is incited somebody to action
First polar signal+TX transmits to the 1st switch of the first data wire a of the 1st data line unit S1, the second multiplex circuit unit B 2
First polar signal+TX is transmitted to the second data wire b of the 1st data line unit S1, the 3rd multiplex circuit unit B 3 by unit T1
The 1st switch element T1 by the second polar signal-TX transmit to the 3rd data wire c of the 1st data line unit S1, the 4th multiplexing electricity
1st switch element T1 of road unit B 4 transmits the second polar signal-TX to the 4th data wire d of the 1st data line unit S1；
In the second period T11 of a vertical interval, integrated circuit unit 20 is to the first multiplex circuit unit B 1 and second
2nd switch element T2 of multiplex circuit unit B 2 transmits the first polar signal+TX, answers to the 3rd multiplex circuit unit B 3 and the 4th
Transmit the second polar signal-TX with the 2nd switch element T2 of circuit unit B 4, control line CK2 passes through single to all of 2nd switch
First T2 inputs the 2nd switch element T2 conducting that control signal controls all multiplex circuit units, makes the first multiplex circuit unit B 1
The 2nd switch element T2 the first polar signal+TX is transmitted to the first data wire a of the 2nd data line unit S2, second multiplexing electricity
2nd switch element T2 of road unit B 2 first polar signal+TX is transmitted to the second data wire b of the 2nd data line unit S2,
Second polar signal-TX is transmitted to the 3rd number of the 2nd data line unit S2 by the 2nd switch element T2 of three multiplex circuit unit B 3
The 2nd switch element T2 according to line c, the 4th multiplex circuit unit B 4 transmits the second polar signal-TX to the 2nd data line unit S2
The 4th data wire d；
In the 3rd period T12 of a vertical interval, integrated circuit unit 20 is to the first multiplex circuit unit B 1 and second
3rd switch element T3 of multiplex circuit unit B 2 transmits the first polar signal+TX, answers to the 3rd multiplex circuit unit B 3 and the 4th
Transmit the second polar signal-TX with the 3rd switch element T3 of circuit unit B 4, control line CK3 passes through single to all of 3rd switch
First T3 inputs the 3rd switch element T3 conducting that control signal controls all multiplex circuit units, makes the first multiplex circuit unit B 1
The 3rd switch element T3 the first polar signal+TX that integrated circuit unit 20 exports is transmitted to the of the 3rd data line unit S3
The first polar signal that integrated circuit unit 20 is exported by one data wire a, the 3rd switch element T3 of the second multiplex circuit unit B 2
The 3rd switch element T3 that+TX transmits to the second data wire b of the 3rd data line unit S3, the 3rd multiplex circuit unit B 3 will be integrated
Second polar signal-TX of circuit unit 20 output transmits to the 3rd data wire c of the 3rd data line unit S3, the 4th multiplexing electricity
3rd switch element T3 of road unit B 4 transmits the second polar signal-TX that integrated circuit unit 20 exports to the 3rd data wire list
The 4th data wire d of first S3.
Based on this, in a vertical interval, the first data wire a in the 1st data line unit S1 and the second data wire b pass
Defeated first polar signal+TX, the 3rd data wire c and the 4th data wire d transmit the second polar signal-TX, the 2nd data line unit S2
In the first data wire a and the second data wire b transmit the first polar signal+TX, the 3rd data wire c and the 4th data wire d transmission
Second polar signal-TX, the first data wire a in the 3rd data line unit S3 and the second data wire b transmission the first polar signal+
TX, the 3rd data wire c and the 4th data wire d transmit the second polar signal-TX, it is achieved thereby that the type of drive of two column inversions,
Avoid the single-row signal polarity inverting i.e. in the data wire of setting on the contrary, the signal causing disturbs and causes extra power consumption
Problem.
And, because integrated circuit unit 20 only provides a kind of pole to same multiplex circuit unit in a vertical interval
Property signal, for example, all multiple to first in the first period T10, the second period T11 and the 3rd period T12 of a vertical interval
There is provided the first polar signal+TX with circuit unit B 1, in the first period T10, the second period T11 and the 3rd of a vertical interval
Period T12 provides the second polar signal-TX, therefore, the pickup electrode of integrated circuit unit 20 to the 3rd multiplex circuit unit B 3
Property switching frequency is relatively low, and the power consumption of integrated circuit unit 20 and array base palte is relatively low.
It should be noted that the i-th switch element in the present embodiment includes first switch pipe, the control of this first switch pipe
End is connected with corresponding control line, and the first end of this first switch pipe is connected with integrated circuit unit 20, this first switch pipe
Second end is connected with corresponding data wire.
As shown in figure 3, the 1st switch element in the first multiplex circuit unit B 1 is control end and the control of first switch pipe
Line CK1 is connected, first end is connected with output end S1 of integrated circuit unit 20, in the second end and the 1st data line unit S1 the
One data wire a is connected, and the 2nd switch element in the first multiplex circuit unit B 1 is control end and the control line of first switch pipe
CK2 is connected, first end is connected with output end S1 of integrated circuit unit 20, in the second end and the 2nd data line unit S2 first
Data wire a is connected, and the 3rd switch element in the first multiplex circuit unit B 1 is control end and the control line CK3 of first switch pipe
It is connected, first end is connected with output end S1 of integrated circuit unit 20, the first data in the second end and the 3rd data line unit S3
Line a is connected.
Wherein, the same signal of the first end of first switch pipe in same multiplex circuit unit and integrated circuit unit 20
Output end is connected, and the first end of first switch pipe in different multiplex circuit units is defeated with the unlike signal of integrated circuit unit 20
Go out end to be connected.As shown in figure 3, the first end of the first switch pipe of the first multiplex circuit unit B 1 all with integrated circuit unit 20
Output end D1 is connected, the first end of the first switch pipe of the second multiplex circuit unit B 2 output end all with integrated circuit unit 20
D2 is connected, the first end of the first switch pipe of the 3rd multiplex circuit unit B 3 output end D3 phase all with integrated circuit unit 20
Even, the first end of the first switch pipe of the 4th multiplex circuit unit B 4 is all connected with output end D4 of integrated circuit unit 20.Base
In this, integrated circuit unit 20 passes through output end D1 provides the first polar signal+TX to the first multiplex circuit unit B 1, by defeated
Go out to hold D2 to provide the first polar signal+TX, pass through output end D3 to the 3rd multiplex circuit unit to the second multiplex circuit unit B 2
B3 provides the second polar signal-TX, provides the second polar signal-TX by output end D4 to the 4th multiplex circuit unit B 4.
Wherein, first switch pipe can be PMOS transistor or nmos pass transistor, when first switch pipe is PMOS
When transistor or nmos pass transistor, its grid is the control end of first switch pipe, and source electrode is the first end of first switch pipe, drain electrode
For the second end of first switch pipe, certainly, the present invention is not limited to this.
In structure shown in Fig. 3, illustrate taking n=3 as a example, but, the present invention is not limited to this, real at other
Apply in example, n can also be equal to 2.
As shown in figure 5, Fig. 5 is the planar structure schematic diagram of another kind array base palte provided in an embodiment of the present invention, this battle array
Row substrate equally include X is arranged in order in the first direction multiple data line group S, along multiple multiplex circuit groups B being arranged in order,
Integrated circuit unit 20 and Duo Gen control line, but, each data line group S only includes the 1st number that X in the first direction is arranged in order
According to line cell S 1 and the 2nd data cell S2, each multiplex circuit unit only includes the 1st switch element T1 and the 2nd being arranged in order
Switch element T2, multiple control lines only include control line CK1 and CK2.
Structure shown in Fig. 5 is with the something in common of the structure shown in Fig. 3, and each data line unit is included along first
The first data wire a that direction X is arranged in order, the second data wire b, the 3rd data wire c and the 4th data wire d, each multiplex circuit
The first multiplex circuit unit B 1 that group B includes being arranged in order, the second multiplex circuit unit B 2, the 3rd multiplex circuit unit B 3 and
4th multiplex circuit unit B 4.
Wherein, the 1st switch in the first data wire a and the first multiplex circuit unit B 1 in the 1st data line unit S1 is single
First T1 electrical connection, the second data wire b in the 1st data line unit S1 and the 1st switch element T1 of the second multiplex circuit unit B 2
Electrical connection, the 3rd data wire c in the 1st data line unit S1 and the 1st switch element T1 of the 3rd multiplex circuit unit B 3 is electrically connected
Connect, the 4th data wire d in the 1st data line unit S1 is electrically connected with the 1st switch element T1 of the 4th multiplex circuit unit B 4；
The 2nd switch element T2 electricity in the first data wire a and the first multiplex circuit unit B 1 in 2nd data line unit S2
Connect, the second data wire b in the 2nd data line unit S2 is electrically connected with the 2nd switch element T2 of the second multiplex circuit unit B 2,
The 3rd data wire c in 2nd data line unit S2 is electrically connected with the 2nd switch element T2 of the 3rd multiplex circuit unit B 3, the 2nd number
Electrically connect with the 2nd switch element T2 of the 4th multiplex circuit unit B 4 according to the 4th data wire d in line cell S 2.
Additionally, the first multiplex circuit unit B 1, the second multiplex circuit unit B 2, the 3rd multiplex circuit unit B 3 and the 4th are multiple
All electrically connected with same control line CK1 with the 1st switch element T1 of circuit unit B 4, the first multiplex circuit unit B 1, second
2nd switch element T2 of multiplex circuit unit B 2, the 3rd multiplex circuit unit B 3 and the 4th multiplex circuit unit B 4 all with same
Root control line CK2 electrically connects.
Based on the structure shown in Fig. 5, as shown in fig. 6, Fig. 6 is the signal timing diagram of the array base palte shown in Fig. 5, in a frame
The first period T20 of sweep time, integrated circuit unit 20 is to the first multiplex circuit unit B 1 and the second multiplex circuit unit B 2
The 1st switch element T1 transmit the first polar signal+TX, to the 3rd multiplex circuit unit B 3 and the 4th multiplex circuit unit B 4
1st switch element T1 transmits the second polar signal-TX, and control line CK1 passes through to control letter to all of 1st switch element T1 input
Number control all multiplex circuit units the 1st switch element T1 conducting, make the 1st switch element T1 of the first multiplex circuit unit B 1
First polar signal+TX is transmitted to the first data wire a of the 1st data line unit S1, the 1st the opening of the second multiplex circuit unit B 2
Close unit T1 to transmit the first polar signal+TX to the second data wire b of the 1st data line unit S1, the 3rd multiplex circuit unit
The 1st switch element T1 of B3 transmits the second polar signal-TX to the 3rd data wire c of the 1st data line unit S1, the 4th multiplexing
The 1st switch element T1 of circuit unit B4 transmits the second polar signal-TX to the 4th data wire d of the 1st data line unit S1；
In the second period T21 of a vertical interval, integrated circuit unit 20 is to the first multiplex circuit unit B 1 and second
2nd switch element T2 of multiplex circuit unit B 2 transmits the first polar signal+TX, answers to the 3rd multiplex circuit unit B 3 and the 4th
Transmit the second polar signal-TX with the 2nd switch element T2 of circuit unit B 4, control line CK2 passes through single to all of 2nd switch
First T2 inputs the 2nd switch element T2 conducting that control signal controls all multiplex circuit units, makes the first multiplex circuit unit B 1
The 2nd switch element T2 the first polar signal+TX is transmitted to the first data wire a of the 2nd data line unit S2, second multiplexing electricity
2nd switch element T2 of road unit B 2 first polar signal+TX is transmitted to the second data wire b of the 2nd data line unit S2,
Second polar signal-TX is transmitted to the 3rd number of the 2nd data line unit S2 by the 2nd switch element T2 of three multiplex circuit unit B 3
The 2nd switch element T2 according to line c, the 4th multiplex circuit unit B 4 transmits the second polar signal-TX to the 2nd data line unit S2
The 4th data wire d.
Based on this, in a vertical interval, the first data wire a in the 1st data line unit S1 and the second data wire b pass
Defeated first polar signal+TX, the 3rd data wire c and the 4th data wire d transmit the second polar signal-TX, the 2nd data line unit S2
In the first data wire a and the second data wire b transmit the first polar signal+TX, the 3rd data wire c and the 4th data wire d transmission
Second polar signal-TX, not only achieves the type of drive of two column inversions, and reduces the pickup electrode of integrated circuit unit 20
Property switching frequency, reduces the power consumption of integrated circuit unit 20 and array base palte.
In structure shown in Fig. 3 and Fig. 5, the i-th switch element only includes first switch pipe, but, the present invention not only
It is limited to this, in other embodiments, as shown in Figure 7 and Figure 8, Fig. 7 is another array base palte provided in an embodiment of the present invention
Planar structure schematic diagram, Fig. 8 is the enlarged drawing of the first multiplex circuit unit B 1 in Fig. 7, and the i-th switch element can also include first
Switching tube and second switch pipe, and, control line includes the first control line and the second control line, the control end of first switch pipe with
First control line be connected, the first end of first switch pipe is connected with integrated circuit unit, the second end of first switch pipe with corresponding
Data wire be connected, the control end of second switch pipe is connected with the second control line, the first end of second switch pipe and first switch
The first end of pipe is connected, and the second end of second switch pipe is connected with the second end of first switch pipe.
As shown in figure 8, control line includes the first control line CK1 to CK3 and the second control line CKB1 to CKB3.1st switch
Unit T1 includes first switch pipe T1a and second switch pipe T1b, the control end of first switch pipe T1a and the first control line CK1 phase
Even, first end is connected with integrated circuit unit 20, the second end is connected with the first data wire a of the 1st data line unit S1, and second opens
The control end of pass pipe T1b is connected with the second control line CKB1, first end is connected with integrated circuit unit 20, the second end is opened with first
The control end closing pipe T1a is connected.2nd switch element T2 includes first switch pipe T2a and second switch pipe T2b, first switch pipe
The control end of T2a is connected with the first control line CK2, first end is connected with integrated circuit unit 20, the second end and the 2nd data wire list
First S2 first data wire a be connected, the control end of second switch pipe T2b is connected with the second control line CKB2, first end with integrated
Circuit unit 20 is connected, the second end is connected with the control end of first switch pipe T2a.3rd switch element T3 includes first switch pipe
T3a and second switch pipe T3b, the control end of first switch pipe T3a is connected with the first control line CK3, first end and integrated circuit
Unit 20 is connected, the second end is connected with the first data wire a of the 3rd data line unit S3, the control end of second switch pipe T3b and the
Two control line CKB3 are connected, first end is connected with integrated circuit unit 20, the control end phase of the second end and first switch pipe T3a
Even.
When integrated circuit unit 20 transmits the first polar signal to the first multiplex circuit unit B 1, the first control line CK1
First switch pipe T1a conducting, the second control line CKB1 is controlled to control second switch pipe T1b conducting, so that the 1st switch element T1 opens
Open；When integrated circuit unit 20 stops transmitting the first polar signal to the first multiplex circuit unit B 1, the first control line CK1 control
First switch pipe T1a cut-off processed, the second control line CKB1 control second switch pipe T1b cut-off, so that the 1st switch element T1 closes
Close.The opening and closing process of the 2nd switch element T2 and the 3rd switch element T3 is identical with this, will not be described here.Wherein,
One switching tube is nmos pass transistor, and first switch pipe is PMOS transistor；Or, first switch pipe is PMOS transistor, first
Switching tube is nmos pass transistor.That is, passing through by a PMOS transistor and a nmos pass transistor simultaneously in the present embodiment
Connection, to constitute switch element, is lost with the threshold value reducing switch element transmission signal.
As a example structure shown in below by Fig. 3, the other structures of array base palte in the embodiment of the present invention are illustrated, ginseng
Examine Fig. 9, Fig. 9 is the concrete structure schematic diagram of the array base palte shown in Fig. 3, this array base palte also includes a plurality of gate line 21, many
Individual pixel cell 22, multiple touch control electrode 23 and a plurality of touch-control lead 24.With reference to Figure 10, Figure 10 is the array base palte edge in Fig. 9
The cross-sectional view of AA ' line of cut, each pixel cell 22 includes thin film transistor (TFT) 220 and pixel electrode 221, and film is brilliant
Body pipe 220 includes grid 220a, source electrode 220b and drain electrode 220c, and grid 220a is connected with gate line, source electrode 220b and data wire
It is connected, drain electrode 220c is connected with pixel electrode 221.Wherein, each touch control electrode 23 is corresponding with touch-control lead 24 connects,
And, all of touch-control lead 24 is connected with touch drive circuit, so that touch drive circuit passes through touch-control lead 24 to touch-control
Electrode 23 inputs touching signals, carries out the detection of position of touch.Touch drive circuit in the present embodiment can and integrated circuit
Unit 20 is integrated in same chip it is also possible to be integrated in respectively in different chips.
In the present embodiment, between pixel cell 22, include multiple gaps that Y in a second direction extends, second direction Y and the
One direction X is vertical, and wherein, multiple gaps that Y extends in a second direction are included between the first gap L 1, the second gap L 2 and the 3rd again
Gap L3.
As shown in Figures 9 and 10, the first gap L 1, the second gap L 2 and third space L3 be located at adjacent pixel cell 22 it
Between, specifically, the first gap L 1, the second gap L 2 and third space L3 are limited by adjacent pixel electrode 221 and form.First number
It is arranged in the first gap L 1 that Y extends in a second direction according to line a and the second data wire b is neighbouring, the 3rd data wire c and the 4th number
It is arranged in the second gap L 2 that Y extends in a second direction according to line d is neighbouring, touch-control lead 24 is arranged on Y in a second direction and extends
Third space L3 in, the first gap L 1 and the second gap L 2 are arranged alternately, and third space L3 is located at the first adjacent gap L 1
With second between gap L 2.Based on this, touch-control lead 24 is in the projection on array base palte and throwing on array base palte for the data wire
Shadow no overlap, it is to avoid the interference to touching signals in touch-control lead 24 for the signal in data wire.Wherein, the knot shown in Figure 10
In structure, touch-control lead 24 and data line bit in same layer, but, the present invention is not limited to this, in other embodiments, touch-control
Lead 24 can also be located at same layer with grid 220a or pixel electrode 221, or touch-control lead 24 is provided separately within a conduction
Layer.
In the present embodiment, touch control electrode 23 is block type electrode, and multiple touch control electrode 23 are in that array is arranged.And, this touches
Control electrode 23 is multiplexed with public electrode, and that is, in the display time interval of a vertical interval, this touch control electrode 23 is multiplexed with public electrode,
This public electrode drives pixel cell 22 to carry out the electric field that image shows with the pixel electrode formation in pixel cell 22；In a frame
The touch-control period of sweep time, this touch control electrode 23 carries out the detection of position of touch.In structure shown in Figure 10, touch control electrode
23 sides away from thin film transistor (TFT) 220 being located at pixel electrode 221, but, the present invention is not limited to this, in other enforcements
In example, touch control electrode 23 may be located on the film layer between pixel electrode 221 and thin film transistor (TFT) 220, will not be described here.
The array base palte that the embodiment of the present invention is provided, each data line group includes the 1st being arranged in order in the first direction
Data line unit to the n-th data cell, the first data wire that each data line unit includes being arranged in order in the first direction, second
Data wire, the 3rd data wire and the 4th data wire, the first multiplex circuit unit that each multiplex circuit group includes being arranged in order,
Second multiplex circuit unit, the 3rd multiplex circuit unit and the 4th multiplex circuit unit, the i-th data wire in each data line group
First data wire of unit, the second data wire, the 3rd data wire and the 4th data wire respectively with a corresponding multiplex circuit group
In the first multiplex circuit unit, the second multiplex circuit unit, the 3rd multiplex circuit unit, the i-th of the 4th multiplex circuit unit
Switch element corresponds electrical connection, and based on this, integrated circuit unit is in a vertical interval to the first multiplex circuit unit
It is multiplexed with i-th switch element transmission the first polar signal of the second multiplex circuit unit, to the 3rd multiplex circuit unit and the 4th
I-th switch element of circuit unit transmits the second polar signal, you can realize the type of drive of two column inversions.Due to integrated circuit
Unit only provides a kind of signal of polarity, therefore, integrated circuit unit to same multiplex circuit unit in a vertical interval
Signal polarity switching frequency relatively low so that the power consumption of display floater and display device is relatively low.
The embodiment of the present invention additionally provides a kind of display floater, and this display floater includes the battle array that any of the above-described embodiment provides
Row substrate.
The embodiment of the present invention additionally provides a kind of driving method of display floater, is applied to above-mentioned display floater, this driving
Method includes：
To the first multiplex circuit unit of arbitrary multiplex circuit group and the i-th switch element transmission of the second multiplex circuit unit
First polar signal, single to the 3rd multiplex circuit unit of described multiplex circuit group and the i-th switch of the 4th multiplex circuit unit
Unit's transmission the second polar signal, and control the i-th switch element of described first multiplex circuit unit by described first polar signal
Transmit the first data wire of the i-th data line unit to respective data lines group, control the i-th of described second multiplex circuit unit to open
Close unit to transmit described first polar signal to the second data wire of described i-th data line unit, control described 3rd multiplexing
Described second polar signal is transmitted to the 3rd data wire of described i-th data line unit, control by the i-th switch element of circuit unit
The i-th switch element making described 4th multiplex circuit unit transmits described second polar signal to described i-th data line unit
The 4th data wire, wherein, described first polarity and described second polarity opposite polarity.
Taking include the display floater of the array base palte shown in Fig. 3 and Fig. 4 as a example, this driving method includes：
In the first period T10 of a vertical interval, integrated circuit unit 20 is to the first multiplex circuit unit B 1 and second
1st switch element T1 of multiplex circuit unit B 2 transmits the first polar signal+TX, answers to the 3rd multiplex circuit unit B 3 and the 4th
Transmit the second polar signal-TX with the 1st switch element T1 of circuit unit B 4, control line CK1 passes through single to all of 1st switch
First T1 inputs the 1st switch element T1 conducting that control signal controls all multiplex circuit units, makes the first multiplex circuit unit B 1
The 1st switch element T1 the first polar signal+TX that integrated circuit unit 20 exports is transmitted to the of the 1st data line unit S1
The first polar signal that integrated circuit unit 20 is exported by one data wire a, the 1st switch element T1 of the second multiplex circuit unit B 2
The 1st switch element T1 that+TX transmits to the second data wire b of the 1st data line unit S1, the 3rd multiplex circuit unit B 3 will be integrated
Second polar signal-TX of circuit unit 20 output transmits to the 3rd data wire c of the 1st data line unit S1, the 4th multiplexing electricity
1st switch element T1 of road unit B 4 transmits the second polar signal-TX that integrated circuit unit 20 exports to the 1st data wire list
The 4th data wire d of first S1；
In the second period T11 of a vertical interval, integrated circuit unit 20 is to the first multiplex circuit unit B 1 and second
2nd switch element T2 of multiplex circuit unit B 2 transmits the first polar signal+TX, answers to the 3rd multiplex circuit unit B 3 and the 4th
Transmit the second polar signal-TX with the 2nd switch element T2 of circuit unit B 4, control line CK2 passes through single to all of 2nd switch
First T2 inputs the 2nd switch element T2 conducting that control signal controls all multiplex circuit units, makes the first multiplex circuit unit B 1
The 2nd switch element T2 the first polar signal+TX that integrated circuit unit 20 exports is transmitted to the of the 2nd data line unit S2
The first polar signal that integrated circuit unit 20 is exported by one data wire a, the 2nd switch element T2 of the second multiplex circuit unit B 2
The 2nd switch element T2 that+TX transmits to the second data wire b of the 2nd data line unit S2, the 3rd multiplex circuit unit B 3 will be integrated
Second polar signal-TX of circuit unit 20 output transmits to the 3rd data wire c of the 2nd data line unit S2, the 4th multiplexing electricity
2nd switch element T2 of road unit B 4 transmits the second polar signal-TX that integrated circuit unit 20 exports to the 2nd data wire list
The 4th data wire d of first S2；
In the 3rd period T12 of a vertical interval, integrated circuit unit 20 is to the first multiplex circuit unit B 1 and second
3rd switch element T3 of multiplex circuit unit B 2 transmits the first polar signal+TX, answers to the 3rd multiplex circuit unit B 3 and the 4th
Transmit the second polar signal-TX with the 3rd switch element T3 of circuit unit B 4, control line CK3 passes through single to all of 3rd switch
First T3 inputs the 3rd switch element T3 conducting that control signal controls all multiplex circuit units, makes the first multiplex circuit unit B 1
The 3rd switch element T3 the first polar signal+TX that integrated circuit unit 20 exports is transmitted to the of the 3rd data line unit S3
The first polar signal that integrated circuit unit 20 is exported by one data wire a, the 3rd switch element T3 of the second multiplex circuit unit B 2
The 3rd switch element T3 that+TX transmits to the second data wire b of the 3rd data line unit S3, the 3rd multiplex circuit unit B 3 will be integrated
Second polar signal-TX of circuit unit 20 output transmits to the 3rd data wire c of the 3rd data line unit S3, the 4th multiplexing electricity
3rd switch element T3 of road unit B 4 transmits the second polar signal-TX that integrated circuit unit 20 exports to the 3rd data wire list
The 4th data wire d of first S3.
Based on this, the display floater using this driving method not only achieves two column inversions, it is to avoid single-row reversion is neighbour
Signal polarity in the data wire of nearly setting is contrary, and the signal causing disturbs and causes the problem of extra power consumption, and, reduce
The signal polarity switching frequency of integrated circuit unit, reduces the power consumption of integrated circuit unit, array base palte and display floater.
The embodiment of the present invention additionally provides a kind of display device, and this display device includes the display surface of above-described embodiment offer
Plate, this display device can be liquid crystal indicator or other kinds of display device, and the present invention is not limited in
This.In display device provided in an embodiment of the present invention, the signal polarity switching frequency of integrated circuit unit is relatively low, and power consumption is also relatively
Low.
In this specification, each embodiment is described by the way of going forward one by one, and what each embodiment stressed is and other
The difference of embodiment, between each embodiment identical similar portion mutually referring to.For device disclosed in embodiment
For, because it corresponds to the method disclosed in Example, so description is fairly simple, say referring to method part in place of correlation
Bright.
Described above to the disclosed embodiments, makes professional and technical personnel in the field be capable of or uses the present invention.
Multiple modifications to these embodiments will be apparent from for those skilled in the art, as defined herein
General Principle can be realized without departing from the spirit or scope of the present invention in other embodiments.Therefore, the present invention
It is not intended to be limited to the embodiments shown herein, and be to fit to and principles disclosed herein and features of novelty phase one
The scope the widest causing.
Claims (11)
1. a kind of array base palte is it is characterised in that include：
The multiple data line group being arranged in order in the first direction, each described data line group includes arranging successively along described first direction
1st data line unit to the n-th data cell of row, each described data line unit includes being arranged in order along described first direction
First data wire, the second data wire, the 3rd data wire and the 4th data wire；
The multiple multiplex circuit groups being arranged in order, each described multiplex circuit group includes the first multiplex circuit list being arranged in order
Unit, the second multiplex circuit unit, the 3rd multiplex circuit unit and the 4th multiplex circuit unit, described first multiplex circuit unit,
The 1st switch that second multiplex circuit unit, the 3rd multiplex circuit unit and the 4th multiplex circuit unit all include being arranged in order is single
Unit is to the n-th switch element；Wherein, the first data wire of the i-th data line unit in each described data line group, the second data
Line, the 3rd data wire and the 4th data wire respectively with the first multiplex circuit unit in corresponding described multiplex circuit group, second
Multiplex circuit unit, the 3rd multiplex circuit unit, the i-th switch element of the 4th multiplex circuit unit correspond electrical connection；
Integrated circuit unit, described integrated circuit unit is electrically connected with described i-th switch element, and described integrated circuit unit to
I-th switch element of described first multiplex circuit unit and described second multiplex circuit unit transmits the first polar signal, to institute
The i-th switch element stating the 3rd multiplex circuit unit and described 4th multiplex circuit unit transmits the second polar signal, and described the
One polarity and the opposite polarity of described second polarity；
Many control lines, described first multiplex circuit unit, the second multiplex circuit unit, the 3rd multiplex circuit unit and the 4th are multiple
With described 1st switch element to the n-th switch element of circuit unit respectively from different described control line electrical connections, and described the
Described the i-th of one multiplex circuit unit, the second multiplex circuit unit, the 3rd multiplex circuit unit and the 4th multiplex circuit unit opens
Close unit to electrically connect with same described control line；
Wherein, n is the integer more than 1；I is any integer between 1 to n, including endpoint value.
2. array base palte according to claim 1 is it is characterised in that described i-th switch element includes first switch pipe；Institute
The control end stating first switch pipe is electrically connected with corresponding described control line, and the first end of described first switch pipe is integrated with described
Circuit unit electrically connects, and the second end of described first switch pipe is electrically connected with corresponding described data wire.
3. array base palte according to claim 2 is it is characterised in that described first switch pipe is PMOS transistor or NMOS
Transistor.
4. array base palte according to claim 1 it is characterised in that described i-th switch element include first switch pipe and
Second switch pipe；Described control line includes the first control line and the second control line；
The control end of described first switch pipe is connected with described first control line, the first end of described first switch pipe and described collection
Circuit unit is become to be connected, the second end of described first switch pipe is connected with corresponding described data wire；
The control end of described second switch pipe is connected with described second control line, the first end of described second switch pipe and described the
The first end of one switching tube is connected, and the second end of described second switch pipe is connected with the second end of described first switch pipe.
5. array base palte according to claim 4 is it is characterised in that described first switch pipe is nmos pass transistor, described
First switch pipe is PMOS transistor；
Or, described first switch pipe is PMOS transistor, and described first switch pipe is nmos pass transistor.
6. the array base palte according to any one of claim 1 to 5 is it is characterised in that n=3, or, n=2.
7. array base palte according to claim 1 is it is characterised in that described first data wire and described second data wire are adjacent
Closely it is arranged in the first gap extending in a second direction, described 3rd data wire and described 4th data wire is neighbouring is arranged on edge
In the second gap that described second direction extends, described second direction is vertical with described first direction, described first gap and institute
State the second gap to be arranged alternately.
8. array base palte according to claim 7 is it is characterised in that also include multiple touch control electrode and multiple touch-control draws
Line, described touch control electrode is corresponding with described touch-control lead to be connected；
Described touch-control lead is arranged in the third space extending along described second direction, and described third space is located at adjacent institute
State between the first gap and described second gap.
9. a kind of display floater is it is characterised in that include the array base palte described in any one of claim 1 to 8.
10. a kind of driving method of display floater is it is characterised in that be applied to the display floater described in claim 9, including：
To the first multiplex circuit unit of arbitrary multiplex circuit group and the i-th switch element transmission first of the second multiplex circuit unit
Polar signal, passes to the 3rd multiplex circuit unit of described multiplex circuit group and the i-th switch element of the 4th multiplex circuit unit
Defeated second polar signal, and control the i-th switch element of described first multiplex circuit unit to transmit described first polar signal
To the i-th data line unit of respective data lines group the first data wire, control described second multiplex circuit unit the i-th switch single
Described first polar signal is transmitted to the second data wire of described i-th data line unit, controls described 3rd multiplex circuit by unit
Described second polar signal is transmitted to the 3rd data wire of described i-th data line unit, controls institute by the i-th switch element of unit
Described second polar signal is transmitted to the of described i-th data line unit by the i-th switch element stating the 4th multiplex circuit unit
Four data wires, wherein, the opposite polarity of described first polarity and described second polarity.
A kind of 11. display devices are it is characterised in that include the display floater described in claim 9.
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| CN108181770A (en) * | 2018-02-11 | 2018-06-19 | 厦门天马微电子有限公司 | A kind of display panel and display device |
| CN108198539A (en) * | 2018-02-13 | 2018-06-22 | 厦门天马微电子有限公司 | Display panel and its driving method, display device |
| CN111025710A (en) * | 2019-12-25 | 2020-04-17 | 厦门天马微电子有限公司 | Display panel and display device |
| CN111477137A (en) * | 2020-04-08 | 2020-07-31 | 福建华佳彩有限公司 | Demux display screen structure and driving method thereof |
| WO2021212997A1 (en) * | 2020-04-21 | 2021-10-28 | 京东方科技集团股份有限公司 | Display panel and driving method therefor, and display device |
| US11741905B2 (en) | 2020-04-21 | 2023-08-29 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Display panel, driving method for same, and display device |
| CN112419992A (en) * | 2020-11-26 | 2021-02-26 | 厦门天马微电子有限公司 | Display panel, driving method thereof and display device |
| WO2022188210A1 (en) * | 2021-03-12 | 2022-09-15 | 武汉华星光电半导体显示技术有限公司 | Touch panel and display apparatus |
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