CN106374896A - Power off reset system - Google Patents
Power off reset system Download PDFInfo
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- CN106374896A CN106374896A CN201610970328.5A CN201610970328A CN106374896A CN 106374896 A CN106374896 A CN 106374896A CN 201610970328 A CN201610970328 A CN 201610970328A CN 106374896 A CN106374896 A CN 106374896A
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- reset signal
- power
- reset
- pin
- electric capacity
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
- H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
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Abstract
The invention discloses a power off reset system which comprises a reset signal generating unit, a reset signal delay unit and a power supply switch unit. The reset signal generating unit is connected with the reset signal delay unit. The reset signal generating unit generates a reset signal based on the system state, and inputs the reset signal into the reset signal delay unit. The reset signal delay unit is connected with the power supply switch unit. The reset signal delay unit delays the reset signal, and then inputs the signal into the power supply switch unit. The power supply switch unit realizes power off and power on reset of the system according to the reset signal. According to the invention, the reset signal delay unit is set to realize power off and power on of the system to realize the reset of the system. The stability of the system is effectively increased. The system which restarts is prevented from abnormality.
Description
Technical field
The present invention relates to protection circuit technical field, especially relate to a kind of power-out reset system being applied to switch.
Background technology
Traditional switch reset schemes are available to cpu and the certain reset delay of exchange chip, in chip initiation
It is used for the preparation of power supply and clock to the chip regular hour, typical time is 200ms, and this time passes through special before
Reset chip provide, reset circuit operation principle is simple, only need to be to the delay pulse of one certain time of system, cpu
With exchange chip, the reset that delay pulse is feasible system is obtained on reseting pin.
House dog type reset circuit mainly utilize cpu normal work when, timing reset enumerator so that the value of enumerator not
Exceed the value of a certain setting, when cpu cisco unity malfunction, because enumerator can not be reset, therefore its counting can exceed certain
One value, thus producing reset pulse so that cpu recovers normal operating conditions, the reliability of this reset circuit depends primarily on soft
Part designs, and it is optimum design that the program that regularly will send pulse to reset circuit is placed on where, general, by this section of program
It is placed in timer interrupt service subprogram；However, program still can be caused to walk sometimes through this design and flying or just do not work
Often, reason is mainly: when program " walking winged " occurs, intervalometer initialize and open after interruption, this walk winged situation
It is possible to be returned by watchdog reset circuit correction, because timer interruption is producing always, even if program is abnormal,
House dog also can be by normal reset.
By intervalometer plus default method for designing, it is pressed into one address of storehouse in initialization, holds in this address
Row is that a pass is interrupted and an endless loop sentence, uses subprogram as much as possible in all addresses not taken by program code
Return instruction ret replaces, and so, after program is walked to fly, it enters the probability of trap and will greatly increase.And once entering sunken
Trap, intervalometer quits work and cuts out interruption, so that watchdog reset circuit can produce a reset pulse by cpu again
Position.Certainly, this technology is used for thering is certain difficulty, this time-delay reset mode in the stronger control of real-time or process software
May be because the reason such as external interference cpu or exchange chip system reset cannot normally start when occurring to reset
Problem, sometimes as certain chip for electrical characteristic particular/special requirement, also occur reset insufficient.
Content of the invention
It is an object of the invention to overcoming the defect of prior art, providing a kind of power-out reset system, system can be passed through
The mode that electricity is gone up in power-off again realizes system reset.
For achieving the above object, the present invention proposes a kind of following technical scheme: power-out reset system, sends out including reset signal
Raw unit, reset signal delay unit, and power switch unit, described reset signal generating unit and described reset signal are prolonged
Shi Danyuan is connected, and described reset signal generating unit occurs reset signal according to system mode, and will be defeated for described reset signal
Enter to reset signal delay unit, described reset signal delay unit is connected with described power switch unit, the described letter that resets
Number delay unit inputs after reset signal time delay to power switch unit, and described power switch unit is according to described reset signal
Realize power-off and the electrification reset of system.
Preferably, described reset signal generating unit includes bipolar junction transistor on-off circuit, and and dipole
The first load that transistor switching circuit is connected, bipolar junction transistor on-off circuit includes reset instruction input, reset
Signal output part, bipolar junction transistor.
Preferably, described reset instruction input is connected with erasable Programmadle logic device, described erasable compiles
Collect the reset instruction that logical device provides, described reset instruction is by software trigger.
Preferably, described reset signal delay unit includes time delay device, and second being connected with time delay device is negative
Carry, described time delay device can adjust the delay time of reset signal according to system reset property requirements.
Preferably, described second load includes the 4th resistance, the 5th resistance, the 6th resistance, the 7th resistance, the second electric capacity,
And the 3rd electric capacity, described time delay device includes eight pins, the first pin ground connection, second pin and described reset signal output
End is connected, and to power switch unit, the 4th pin is connected to work electricity the 3rd pin output reset signal by the 4th resistance
Source, the 5th pin passes through the second capacity earth.
Preferably, described 3rd electric capacity passes through the 6th resistance being connected in series and the 7th resistance is connected with working power, the
One end of three electric capacity is connected with one end of the 6th resistance, and the opposite end ground connection of described 3rd electric capacity, and the 6th of time delay device the
Pin is connected between the 3rd electric capacity and the 6th resistance by the 5th resistance, the 7th pin connect to and connect to the 3rd electric capacity with
Between 6th resistance.
Preferably, described power switch unit includes the 4th electric capacity and the 5th that step-up device is connected with step-up device
Electric capacity, high-power mos pipe, and the complex capacitance being connected with high-power mos pipe, described step-up device and high-power mos pipe
It is connected, control conducting and the cut-off of high-power mos pipe.
Preferably, described step-up device includes five pins, and the first pin is connected jointly with one end of described 4th electric capacity
To working power, the opposite end ground connection of described 4th electric capacity, between the 4th pin and the earth terminal of the 4th electric capacity, it is connected with the 5th
Electric capacity.
Preferably, the 4th pin of described step-up device is connected with the grid of high-power mos pipe, the 5th pin and time delay
3rd pin of device is connected, the reset signal after input time delay.
The invention has the beneficial effects as follows:
Power-out reset system of the present invention, realizes system cut-off by setting reset signal delay unit 2 and goes up electricity again
Thus realizing system reset, it is effectively increased the stability of system, it is to avoid system occurs abnormal when restarting.
Brief description
Fig. 1 is the system block diagram schematic diagram of the present invention；
Fig. 2 is the reset signal generating unit circuit diagram schematic diagram of the present invention；
Fig. 3 is that the reset signal time-delay unit circuit diagram of the present invention is intended to；
Fig. 4 is the step-up device circuit diagram schematic diagram in the power switch unit of the present invention；
Fig. 5 is the high-power mos pipe circuit diagram schematic diagram in the on and off switch power supply of the present invention.
Reference: 1, reset signal generating unit, 2, reset signal delay unit, 3, power switch unit, 11, bipolar
Junction transistor on-off circuit, 111, reset instruction input, 112, reset signal outfan, 113, bipolar junction transistor,
114th, first resistor, 115, second resistance, the 116, first power supply, the 12, first load, 121,3rd resistor, the 122, first electric capacity,
21st, time delay device, the 22, the 4th resistance, the 23, the 5th resistance, the 24, the 6th resistance, the 25, the 7th resistance, the 26, second electric capacity, 27,
Three electric capacity, 31, step-up device, the 32, the 4th electric capacity, the 33, the 5th electric capacity, 34, high-power mos pipe, the 4, the 8th resistance.
Specific embodiment
Below in conjunction with the accompanying drawing of the present invention, clear, complete description is carried out to the technical scheme of the embodiment of the present invention.
Power-out reset system of the present invention, is mainly used in switch system, increases the stability of switch, this
In embodiment, it is described in detail taking the switch as core for the exchange chip ctc5160 based on Sheng section network as a example.
In conjunction with shown in Fig. 1, disclosed power-out reset system, including reset signal generating unit 1, reset signal
Delay unit 2, and power switch unit 3, described reset signal generating unit 1 is connected with described reset signal delay unit 2
Connect, described reset signal generating unit 1 produces reset signal, and described reset signal is inputted to reset signal delay unit 2,
Described reset signal delay unit 2 is connected with described power switch unit 3, and described reset signal delay unit 2 is believed resetting
Input to power switch unit 3 after number time delay, described power switch unit 3 realizes the upper electric and disconnected of system according to reset signal
Electricity, sends reset signal to power switch unit 3 again by arranging certain delay time, exchange system can be made to have certain
Buffer time, thus avoid electrifying timing sequence to occur confusion to lead to the exchange system cannot normal work.
Specifically, as shown in Fig. 2 reset signal generating unit 1 includes bjt (bipolar junction
Transistor, bipolar junction transistor) on-off circuit and the first load 12 being connected with bjt on-off circuit, specifically
, described bjt on-off circuit include reset instruction input 111, reset signal outfan 112, bjt, first resistor 114,
Two resistance 115 and the first power supply 116, wherein, bjt is npn silicone tube, one end of described first resistor 114 and the base of bjt
Pole is connected, and opposite end is reset instruction input 111, the grounded emitter of described bjt, one end of described second resistance 115
It is connected with the first power supply 116, opposite end is connected with the colelctor electrode of bjt, and be connected with reset signal outfan 112, institute
State reset instruction input to be connected with erasable Programmadle logic device (not shown), described erasable Programmadle logic device
The reset instruction being given, described reset instruction is by software trigger.
Described first load 12 is 3rd resistor 121 and the first electric capacity being connected in reset instruction input 111 in parallel
122, specifically, described 3rd resistor 121 and the first electric capacity 122, and one end of first resistor 114 is commonly connected to bipolar junction
In the base stage of transistor npn npn 113, and the opposite end of described 3rd resistor 121 and the first electric capacity 122 is common with the emitter stage of bjt
Ground connection, described first resistor 114, and the first electric capacity 122 are used for adjusting input voltage, and described second resistance 115 is used for adjusting
Output voltage, wherein, bjt is npn silicone tube, and when input low level, zero inclined (v is become in the transmitting of bjtbe=0), current collection is become
Reverse bias (vbc＜ 0), the electric current of only very little flows through pn-junction, and bjt is operated in cut-off state, therefore exports and prolongs to reset signal
Voltage in Shi Danyuan 2 is high level, and when input is for high level, namely when sending reset instruction, bjt turns on, and bjt is operated in
Saturation, therefore exporting voltage to reset signal delay unit 2 is low level it is preferable that in the present embodiment, described three
Model cmpt3904-lf of level pipe, the resistance of first resistor 114, the capacity of the first electric capacity 122, and second resistance 115,
3rd resistor 121, can be adjusted according to real work demand.
When switch system abnormal, system can send reset instruction, and system exception situation generally includes system and runs
Fly, board temperature is too high, master chip excess temperature, and system fan exception etc., reset instruction inputs, to reset signal, list occurs
So that the conducting of npn silicone tube in unit 1, that is, bipolar junction transistor on-off circuit 11 works, and so that output voltage is reduced, and produces multiple
Position signal input is to reset signal delay unit 2.
Further, as shown in figure 3, reset signal delay unit 22 includes time delay device 21, and and time delay device
21 the second loads being connected, described second load includes the 4th resistance 222, the 5th resistance 23, the 6th resistance 24, the 7th resistance
25th, the second electric capacity 26, and the 3rd electric capacity 27.In the present embodiment, described time delay device 21 is selected from National Semiconductor
Lmc555cm delay chip, described lmc555cm delay chip can by outside connected electric capacity, resistance big
Minor adjustment delay time, described lmc555cm delay chip totally 8 pins, wherein, the first pin is grounding pin (ground),
Second pin is triggering pin (trigger), and the 3rd pin is output pin (output), and the 4th pin is to reset pin
(reset), the 5th pin is control voltage pin (control voltage), and the 6th pin is critical pin
(threshold), the 7th pin is electric discharge pin (discharge), and the 8th pin is power pins (vcc).
Specifically, the first pin ground connection, second pin is connected with the reset signal outfan 112 of reset signal generation unit
Connect, between described reset signal outfan 112 and second pin, be additionally provided with the 8th resistance 4, reduce input further to the letter that resets
Voltage in number delay unit 2, thus Time delay action, the 3rd pin continues output voltage in delay time and opens to power supply
Close unit 3, thus controlling power switch unit 3 that exchange system is carried out with electrification reset, the 4th pin passes through the 4th resistance 22 even
It is connected to working power, when the voltage of the 4th pin is less than 0.4v, the 3rd pin is output as electronegative potential, and the 7th pin is over the ground
Short circuit, the 5th pin is connected with one end of the second electric capacity 26, and the opposite end ground connection of the second electric capacity 26；3rd electric capacity 27 is designated as
C, the 3rd electric capacity 27 passes through the 6th resistance 24 being connected in series and the 7th resistance 25 is connected with working power, and the one of the 3rd electric capacity 27
End is connected with one end of the 6th resistance 24, and the opposite end ground connection of described 3rd electric capacity 27, the 6th pin of time delay device 21
Connected between the 3rd electric capacity 27 and the 6th resistance 24 by the 5th resistance 23, the 7th pin connects to and connects to the 3rd electric capacity
27 and the 6th between resistance 24, and wherein, the 6th resistance 24 is designated as r1, and the 7th resistance 25 is designated as r2, described 6th resistance 24 and
Seven resistance 25, control delay time with the 3rd electric capacity 27, specifically, t=(r1+r2) * c, when delay time reaches, the
Three pins return to original level state, the external working power of the 8th pin, for providing lmc555cm to provide running voltage, make
Its normal work, is also parallel with complex capacitance between the 8th pin and external working power, for adjusting the electricity of the 8th pin
Pressure.
Specifically, the reset signal outfan 112 of reset signal generating unit 1 is connected with the second pin of lmc555cm
Connect, second pin trailing edge triggers, when reset signal occurs so that the input voltage of second pin declines, trigger further,
Make the 3rd port output HIGH voltage, after high voltage time delay for a period of time, persistently input to voltage switching element.
In conjunction with shown in Fig. 4, Fig. 5, power switch unit 3 is whole system power-off and the core of upper electricity, described on and off switch
Unit 33 includes the 4th electric capacity 3232 and the 5th electric capacity 33, the high-power mos pipe that step-up device 31 is connected with step-up device 31
34, and the complex capacitance being connected with high-power mos pipe 34, described step-up device 31 is connected with high-power mos pipe 34, controls
Make conducting and the cut-off of high-power mos pipe 34, specifically, after reset signal delay unit 2 completes time delay, time delay device 21
The output state conversion of the 3rd pin (namely output pin), controls step-up device 31, and step-up device 31 then passes through control further
Make the conducting of high-power mos pipe 34 and cut-off realizing the power-off of system and upper electricity, thus completion system resets.
Specifically, described step-up device 31 is selected from the step-up device 31 of model hip1020ckz-t, and it includes five and draws
Foot, the first pin is power pins (vcc), and second pin is grounding pin (ground), and the 3rd pin is that electronegative potential mos pipe drives
Dynamic pin (lgate), the 4th pin is that high potential mos pipe drives pin (hgate), and the 5th pin is to enable pin, this enforcement
In example, the first pin is commonly connected to working power, the opposite end of described 4th electric capacity 32 with one end of described 4th electric capacity 32
Ground connection, is connected with the 5th electric capacity 33 between the 4th pin and the earth terminal of the 4th electric capacity 32, enables the normal work of step-up device 31
Make, second pin be grounded, due to control high-power mos pipe 34 need high voltage, the therefore the 3rd pin does not use, the 4th pin with
The grid of high-power mos pipe 34 is connected, for controlling conducting and the cut-off of high-power mos pipe 34, the 5th pin and the letter that resets
3rd pin (output pin) of number delay unit 2 is connected, and the 5th pin passes through to receive the clock signal of output pin input, control
Make the output of the 4th pin, the 4th pin can export 0-22v voltage, when the voltage of high-power mos pipe 34 is more than 20v, greatly
Power mos pipe 34 turns on, thus being embodied as system electrification, starting and resetting, and when voltage is not up to preset value, mos pipe ends, and is
System power-off, time delay resets for a period of time afterwards.
Power-out reset system of the present invention passes through to arrange time delay, increases system stability, it is to avoid occur in when restarting
The generation of abnormal conditions.
The technology contents of the present invention and technical characteristic have revealed that as above, but those of ordinary skill in the art still may base
Make a variety of replacements without departing substantially from spirit of the present invention and modification, therefore, the scope of the present invention in teachings of the present invention and announcement
The content disclosed in embodiment should be not limited to, and the various replacements without departing substantially from the present invention and modification should be included, and be this patent Shen
Please claim be covered.
Claims (9)
1. a kind of power-out reset system it is characterised in that include reset signal generating unit, reset signal delay unit, and
Power switch unit, described reset signal generating unit is connected with described reset signal delay unit, and described reset signal is sent out
There is reset signal according to system mode in raw unit, and described reset signal is inputted to reset signal delay unit, described multiple
Position signal lag unit is connected with described power switch unit, and described reset signal delay unit will be defeated after reset signal time delay
Enter to power switch unit, described power switch unit realizes power-off and the electrification reset of system according to described reset signal.
2. power-out reset system according to claim 1 it is characterised in that described reset signal generating unit include bipolar
Junction transistor on-off circuit, and the first load being connected with bipolar junction transistor on-off circuit, bipolar junction transistor
Pipe on-off circuit includes reset instruction input, reset signal outfan, bipolar junction transistor.
3. power-out reset system according to claim 2 it is characterised in that described reset instruction input with erasable can
Editorial logic device is connected, the reset instruction that described erasable Programmadle logic device is given, described reset instruction by
Software trigger.
4. power-out reset system according to claim 1 is it is characterised in that described reset signal delay unit includes time delay
Device, and the second load being connected with time delay device, described time delay device can be adjusted according to system reset property requirements
The delay time of reset signal.
5. power-out reset system according to claim 3 it is characterised in that described second load include the 4th resistance, the
Five resistance, the 6th resistance, the 7th resistance, the second electric capacity, and the 3rd electric capacity, described time delay device includes eight pins, and first
Pin is grounded, and second pin is connected with described reset signal outfan, and the 3rd pin output reset signal is on and off switch list
Unit, the 4th pin is connected to working power by the 4th resistance, and the 5th pin passes through the second capacity earth.
6. power-out reset system according to claim 5 is it is characterised in that described 3rd electric capacity passes through the being connected in series
Six resistance and the 7th resistance are connected with working power, and one end of the 3rd electric capacity is connected with one end of the 6th resistance, and described
The opposite end ground connection of three electric capacity, the 6th pin of time delay device by the 5th resistance connect to the 3rd electric capacity and the 6th resistance it
Between, the 7th pin connects between the 3rd electric capacity and the 6th resistance.
7. power-out reset system according to claim 1 is it is characterised in that described power switch unit includes booster
The 4th electric capacity and the 5th electric capacity, high-power mos pipe that part is connected with step-up device, and be connected with high-power mos pipe
Complex capacitance, described step-up device is connected with high-power mos pipe, controls conducting and the cut-off of high-power mos pipe.
8. power-out reset system according to claim 7 is it is characterised in that described step-up device includes five pins, and
One pin is commonly connected to working power, the opposite end ground connection of described 4th electric capacity with one end of described 4th electric capacity, and the 4th draws
It is connected with the 5th electric capacity between the earth terminal of foot and the 4th electric capacity.
9. power-out reset system according to claim 8 is it is characterised in that the 4th pin of described step-up device and big work(
The grid of rate mos pipe is connected, and the 5th pin is connected with the 3rd pin of time delay device, the reset signal after input time delay.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610970328.5A CN106374896B (en) | 2016-11-04 | 2016-11-04 | Power-out reset system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610970328.5A CN106374896B (en) | 2016-11-04 | 2016-11-04 | Power-out reset system |
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| Publication Number | Publication Date |
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| CN106374896A true CN106374896A (en) | 2017-02-01 |
| CN106374896B CN106374896B (en) | 2019-05-31 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610970328.5A Active CN106374896B (en) | 2016-11-04 | 2016-11-04 | Power-out reset system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109863410A (en) * | 2017-09-19 | 2019-06-07 | 深圳市汇顶科技股份有限公司 | The measurement method and system of power-on reset time |
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| CN203181140U (en) * | 2013-01-08 | 2013-09-04 | 上海大学 | Set top box structure with reset-delay control |
| CN205229961U (en) * | 2015-11-30 | 2016-05-11 | 山东康威通信技术股份有限公司 | Anti breech lock power -off reset circuit of CMOS singlechip |
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| CN1743999A (en) * | 2004-08-30 | 2006-03-08 | 上海贝岭股份有限公司 | Clock synchronous power-on reset signal generating circuit |
| CN102545854A (en) * | 2010-12-31 | 2012-07-04 | 鸿富锦精密工业（深圳）有限公司 | Reset circuit and electronic device |
| CN203181140U (en) * | 2013-01-08 | 2013-09-04 | 上海大学 | Set top box structure with reset-delay control |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109863410A (en) * | 2017-09-19 | 2019-06-07 | 深圳市汇顶科技股份有限公司 | The measurement method and system of power-on reset time |
| CN109863410B (en) * | 2017-09-19 | 2021-03-05 | 深圳市汇顶科技股份有限公司 | Method and system for measuring power-on reset time |
| US11287453B2 (en) | 2017-09-19 | 2022-03-29 | Shenzhen GOODIX Technology Co., Ltd. | Method and system for measuring power-on reset time |
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