CN106373942B - Semiconductor structure - Google Patents
Semiconductor structure Download PDFInfo
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- CN106373942B CN106373942B CN201510666469.3A CN201510666469A CN106373942B CN 106373942 B CN106373942 B CN 106373942B CN 201510666469 A CN201510666469 A CN 201510666469A CN 106373942 B CN106373942 B CN 106373942B
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- buried layer
- trap
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- doped region
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000004020 conductor Substances 0.000 claims description 13
- 230000003068 static effect Effects 0.000 claims description 2
- 238000012423 maintenance Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
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- Semiconductor Integrated Circuits (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
Abstract
A semiconductor structure is used for releasing an electrostatic discharge current and comprises a substrate, a first buried layer, a second buried layer, a first well, a second well, a first doped region, a trench gate and a second doped region. First and second buried layers are formed over a substrate. The first well is formed over the first buried layer. The second well is formed over the second buried layer, overlapping a portion of the second buried layer. The first doped region is formed in the first well. The trench gate extends into the second well and the first buried layer. The second doped region is formed in the second well and contacts the trench gate.
Description
Technical field
The invention relates to a kind of semiconductor structures, in particular to one kind to release electrostatic electric discharge (ESD) electricity
The semiconductor structure of stream.
Background technique
The esd event of integrated circuit refers to the electrostatic charge with high voltage, through the release of IC chip
Journey.The transient energy of discharge electrostatic charges is comparable considerable, if not kind plus processing, often will cause the burning of integrated circuit
It ruins.
Summary of the invention
The present invention provides a kind of semiconductor structure, covers to discharge a static discharge current, and including a substrate, one first
Buried layer, one second buried layer, one first trap, one second trap, one first doped region, a ditching type grid and one second doping
Area.Substrate has a first conductive type state.First buried layer is formed in substrate, and has a second conductive type state.Second
Buried layer is formed in substrate, and has third conductivity.First trap is formed on the first buried layer, and has second
Conductivity.Second trap is formed on the second buried layer, the first buried layer of lap, and has third conductivity.The
One doped region is formed among the first trap, and has third conductivity.Ditching type grid extends into the second trap and first
Buried layer.Second doped region is formed among the second trap, contacts ditching type grid, and have the second conductive type state.
The present invention provides a kind of semiconductor structure, wherein the first conductive type state is p-type, the second conductive type state is
N-type, the third conductivity are p-type.
The present invention provides a kind of semiconductor structure, wherein the first conductive type state is N-type, the second conductive type state is
N-type, the third conductivity are p-type.
The present invention provides a kind of semiconductor structure, wherein the first conductive type state is N-type, the second conductive type state is
P-type, the third conductivity are N-type.
The present invention provides a kind of semiconductor structure, wherein the concentration of first buried layer is higher than first trap, it is described
The concentration of second buried layer is higher than second trap.
The present invention provides a kind of semiconductor structure, wherein the semiconductor structure further includes：
One third doped region is formed among second trap, contacts the ditching type grid, and has described second to lead
Electric kenel.
The present invention provides a kind of semiconductor structure, wherein second doped region contacts the one first of the ditching type grid
Side wall, the third doped region contact a second sidewall of the ditching type grid, and the first side wall is relative to described second
Side wall.
The present invention provides a kind of semiconductor structure, wherein the ditching type grid does not penetrate first buried layer.
The present invention provides a kind of semiconductor structure, wherein having one between first buried layer and second buried layer
Gap.
The present invention provides a kind of semiconductor structure, wherein the semiconductor structure further includes：
One the 4th doped region is formed among first trap, and has the second conductive type state, wherein described first
And the 4th doped region couple one first plain conductor；
One the 5th doped region is formed among second trap, and has the third conductivity, wherein described first
Doped region, the ditching type grid and the 5th doped region couple one second plain conductor.
For the features and advantages of the present invention can be clearer and more comprehensible, preferred embodiment is cited below particularly out, and cooperate institute's attached drawing
Formula is described in detail below：
Detailed description of the invention
Fig. 1-Fig. 3 is the possibility schematic diagram of semiconductor structure of the invention.
Fig. 4 is the forming method schematic diagram of semiconductor structure of the invention.
Label declaration
100,300 semiconductor structure；
110 substrates；
121,122 buried layer；
131,132 trap；
140 ditching type grids；
141,142 side wall；
151~155 doped regions；
The gap GA；
S410, S420, S430, S440, S450, S460, S470, S480 step.
Specific embodiment
Fig. 1 is semiconductor structure schematic diagram of the invention.As shown, semiconductor structure 100 includes a substrate 110, covers
Buried layer (buried layer) 121,122,131,132, one ditching type grid of trap (trench gate) 140, doped region 151 with
152.The present invention does not limit the conductivity of substrate 110.One may in embodiment, the conductivity of substrate 110 be N-type or
P-type.
Buried layer 121 and 122 is formed on substrate 110.In a possible embodiment, the conduction of buried layer 121 and 122
Kenel is not identical.For example, when the conductivity of buried layer 121 is N-type or p-type, the conductivity of buried layer 122 is
P-type or N-type.In the present embodiment, there is a gap GA between buried layer 121 and 122, but be not intended to limit the invention.?
In other embodiments, does not have gap between buried layer 121 and 122, but be in direct contact with together.
Trap 131 is formed on buried layer 121.In a possible embodiment, trap 131 has phase homotype with buried layer 121
The dopant of state is such as N-type or p-type.In the present embodiment, the doping concentration of buried layer 121 is dense higher than the doping of trap 131
Degree, therefore the equivalent impedance of trap 131 can be reduced.
Trap 132 is formed on buried layer 122, and the buried layer 121 of lap.In a possible embodiment, trap 132
There is the dopant of identical kenel with buried layer 122.In the present embodiment, the doping concentration of buried layer 122 is higher than mixing for trap 132
Miscellaneous concentration, therefore the equivalent impedance of trap 132 can be reduced.
Ditching type grid 140 extends into trap 132 and buried layer 121.As shown, ditching type grid 140 penetrates trap
132, but do not penetrate buried layer 121.In another possible embodiment, ditching type grid 140 penetrates trap 132 and buried layer 121.
Doped region 151 is formed among trap 131.In a possible embodiment, the conductivity of doped region 151 is different from trap
131 conductivity.For example, when the conductivity of doped region 151 is N-type or p-type, the conductivity of trap 131 is p-type
Or N-type.In other embodiments, the conductivity of doped region 151 is equal to the conductivity of buried layer 122, be such as N-type or
P-type.In some embodiments, the doping concentration of doped region 151 could possibly be higher than or lower than buried layer 122 doping concentration.
Doped region 152 is formed among trap 132 and contacts ditching type grid 140.In a possible embodiment, doped region
152 conductivity is different from the conductivity of trap 132.For example, when the conductivity of doped region 152 is N-type or p-type
When, the conductivity of trap 132 is p-type or N-type.In other embodiments, the conductivity of doped region 152 is equal to buried layer
121 conductivity is such as N-type or p-type.In some embodiments, the doping concentration of doped region 152 could possibly be higher than or be lower than
The doping concentration of buried layer 121.
In a possible embodiment, the conductivity of substrate 110 is p-type.In this instance, buried layer 121, trap 131 and
The conductivity of doped region 152 is N-type, and the conductivity of buried layer 122, trap 132 and doped region 151 is p-type, but
It is not intended to limit the invention.In other embodiments, when the conductivity of substrate 110 is p-type, buried layer 121, trap 131
And the conductivity of doped region 152 is p-type, and the conductivity of buried layer 122, trap 132 and doped region 151 is N
Type.In another possible embodiment, when the conductivity of substrate 110 is N-type, buried layer 121, trap 131 and doped region 152
Conductivity be N-type, and the conductivity of buried layer 122, trap 132 and doped region 151 is p-type.
Fig. 2 is another possible embodiment of semiconductor structure of the invention.Fig. 2 similar diagram 1, the difference is that Fig. 2 is more
Doped region 153.As shown, doped region 153 is formed among trap 132, and contact the side wall 141 of ditching type grid 140.?
In this example, doped region 152 contacts the side wall 142 of ditching type grid 140.Side wall 141 is relative to side wall 142.In the present embodiment,
The conductivity having the same of doped region 153 and 152.May be in embodiment one, the doping concentration of doped region 153 is higher than or low
In the doping concentration of buried layer 121.
Fig. 3 is another possible embodiment of semiconductor structure of the invention.Fig. 3 similar diagram 2, the difference is that Fig. 3 is more
Doped region 154 and 155.In the present embodiment, the conductivity of doped region 154 is identical as trap 131, to as trap 131
Electrical contact end.In addition, the conductivity of doped region 155 is identical as trap 132, to the electrical contact end as trap 132.
As shown, doped region 154 and 151 couples plain conductor P1, doped region 153,152,155 and ditching type grid
140 coupling plain conductor P2.For convenience of description, below by using the conductivity of substrate 110 as p-type, buried layer 121, trap 131,
The conductivity of doped region 152,153,154 is N-type, and the conductivity of buried layer 122, trap 132, doped region 151,155
For being p-type.As shown, doped region 151, trap 131 and substrate 110 constitute a pnp transistor Q1.Symbol RN represents trap
131 equivalent resistance.In addition, doped region 152, trap 132 and buried layer 121 constitute a npn transistor Q2.Symbol RP represents trap
132 equivalent resistance.Doped region 152, trap 132 and buried layer 121 also constitute a N-type transistor Q3 simultaneously.Doped region 153, trap
132 constitute another N-type transistor Q4 with buried layer 121.
In the present embodiment, semiconductor structure 300 is that a low-voltage triggers thyristor (Low Voltage
Trigger Silicon Controlled Rectifier；LVTSCR), rapidly to discharge when esd event occurs
ESD electric current.For example, when a positive voltage esd event betides plain conductor P1, and plain conductor P2 is coupled to ground,
Transistor Q1~Q4 is both turned on, to discharge ESD electric current.Since transistor Q3 and Q4 provides two discharge paths, therefore can be rapidly
Discharge ESD electric current.Furthermore, it is assumed that (no esd event) under normal operation, plain conductor P1 and P2 are respectively received two operations
Since trap 131 and 132 has lesser equivalent resistance, therefore the maintenance voltage of LVTSCR can be improved in voltage (such as Vcc and GND)
(holding voltage), is accidentally triggered to avoid LVTSCR.In addition, long by the extension of control ditching type grid 140
Degree also can adjust the maintenance voltage of LVTSCR.
Fig. 4 is the forming method of semiconductor structure of the invention.In the present embodiment, by forming method shown in Fig. 4,
A LVTSCR element can be formed, to discharge ESD electric current.Firstly, forming a substrate (step S410).The present invention does not limit lining
The conductivity at bottom.In a possible embodiment, the conductivity of substrate is p-type or N-type.
One first buried layer is formed at substrate (step S420), re-forms one second buried layer in substrate (step
Rapid S430).In the present embodiment, the first buried layer and not in contact with the second buried layer, that is to say, that first and second buried layer it
Between there is a gap, but be not intended to limit the invention.In other embodiments, the first buried layer contacts the second buried layer.
The present invention does not limit the conductivity of first and second buried layer.In the present embodiment, first buried layer is led
Electric kenel is different from the conductivity of the second buried layer.For example, when the conductivity of the first buried layer is N-type or p-type,
The conductivity of second buried layer is p-type or N-type.In addition, the present invention does not limit the sequence of step S420 and S430.Another
In possible embodiment, step S430 is earlier than step S420.
Then, one first trap (step S440) is formed on the first buried layer, and forms one on the second buried layer
Second trap (step S450).It may be applied in example one, the conductivity for the first buried layer that the conductivity of the first trap is equal to,
And the conductivity for the second buried layer that the conductivity of the second trap is equal to.In the present embodiment, the doping of the first buried layer
Concentration is higher than the doping concentration of the first trap, and therefore, the first trap has lesser equivalent resistance.In addition, the doping of the second buried layer
Concentration is also above the doping concentration of the second trap, and therefore, the second trap also has lesser equivalent resistance.Since first and second trap has
There is lesser equivalent resistance, therefore the maintenance voltage of LVTSCR can be increased, to avoid at normal operating (no esd event), accidentally touches
Send out LVTSCR.In addition, in other embodiments, step S450 is earlier than step S440.
In other embodiments, before executing step 440, an epitaxial layer is first formed on first and second buried layer
(epitaxial layer), so that first and second subsequent trap is formed on epitaxial layer.In a possible embodiment, extension
Layer has P-type conduction kenel, but is not intended to limit the invention.
Then, a ditching type grid (step S460) is formed.In the present embodiment, ditching type grid is extended into toward the second trap
Enter the first buried layer.In a possible embodiment, ditching type grid penetrates the second trap, does not penetrate the first buried layer.Another
In possible embodiment, ditching type grid penetrates the second trap and the first buried layer.In other embodiments, by increasing ditching type grid
The development length of pole can also increase the maintenance voltage of LVTSCR.
The first doped region (step S470) is formed in the first trap.In the present embodiment, the conductivity of the first doped region
It is equal to the conductivity of the second trap.In a possible embodiment, the concentration of the first doped region is higher than the doping concentration of the second trap.
In some embodiments, the concentration of the first doped region is higher or lower than the concentration of the second buried layer.
The second doped region (step S480) is formed in the second trap.In the present embodiment, the second doped region contacts ditching type
The one side wall of grid.The conductivity of second doped region is equal to the conductivity of the first trap.In a possible embodiment, second
The concentration of doped region is higher than the doping concentration of the first trap.In some embodiments, the concentration of the second doped region is higher or lower than the
The concentration of one buried layer.In another possible embodiment, step S480 is that two doped regions are formed in the second trap, and two doping are distinguished
Not Jie Chu ditching type grid two sidewalls.In this instance, two doped regions have same conductivity, and concentration having the same, use
To provide two discharge paths, to discharge ESD electric current.
The present invention does not limit the sequence of step S470 and S480.In another possible embodiment, step S480 be earlier than
Step S470.In other embodiments, after step S480, each one doped region of self-forming in first and second trap, makees respectively
For the electrical contact end of first and second trap.
Then, other corresponding metallization process (metallization) are carried out then.In a possible embodiment,
After metallization process, the second doped region is electrically connected the electrical contact end of the first trap, and is coupled to one first plain conductor.In addition, the
One doped region is electrically connected the electrical contact end of the second trap with ditching type grid, and is coupled to one second plain conductor.When esd event is sent out
It is raw in the first plain conductor, and when the second plain conductor is coupled to ground, ESD electric current can from the second doped region, flow through the first trap,
First buried layer, the second trap, the first doped region are discharged to ground.
Since first and second trap is respectively formed on first and second buried layer, and first and second buried layer
Concentration is higher than the concentration of first and second trap, therefore can reduce the equivalent resistance of first and second trap, and then increases the dimension of LVTSCR
Hold voltage.Furthermore by the development length for controlling ditching type grid, the maintenance voltage of LVTSCR also can control.When LVTSCR's
When maintenance voltage is enhanced, (no esd event occurs) under normal operation can be avoided, LVTSCR is influenced by false triggering
Normal operating.
Unless otherwise defined, all vocabulary (including technology and scientific terms) belong in the technical field of the invention herein
Has the general understanding of usually intellectual.In addition, unless clear expression, definition of the vocabulary in general dictionary should be interpreted that and it
Meaning is consistent in the article of correlative technology field, and should not be construed as perfect condition or excessively formal voice.
Although the present invention has been disclosed as a preferred embodiment, however, it is not to limit the invention, any affiliated technology
Has usually intellectual in field, without departing from the spirit and scope of the present invention, when can make some changes and embellishment, therefore
Protection scope of the present invention is subject to the claim institute defender of view front.
Claims (10)
1. a kind of semiconductor structure, which is characterized in that the semiconductor structure to discharge a static discharge current, and including：
One substrate has a first conductive type state；
One first buried layer is formed in the substrate, and has a second conductive type state；
One second buried layer is formed in the substrate, and has a third conductivity；
One first trap is formed on first buried layer, and has the second conductive type state；
One second trap is formed on second buried layer, the first buried layer described in lap, and there is the third to lead
Electric kenel；
One first doped region is formed among first trap, and has the third conductivity；
One ditching type grid extends into second trap and first buried layer；And one second doped region, it is formed in
Among second trap, the ditching type grid is contacted, and there is the second conductive type state；
First buried layer and second buried layer be not be overlapped, the first conductive type state and the third conductivity phase
It is same and different from the second conductive type state.
2. semiconductor structure according to claim 1, which is characterized in that the first conductive type state be p-type, described second
Conductivity is N-type, and the third conductivity is p-type.
3. semiconductor structure according to claim 1, which is characterized in that the first conductive type state be N-type, described second
Conductivity is N-type, and the third conductivity is p-type.
4. semiconductor structure according to claim 1, which is characterized in that the first conductive type state be N-type, described second
Conductivity is p-type, and the third conductivity is N-type.
5. semiconductor structure according to claim 1, which is characterized in that the concentration of first buried layer is higher than described the
The concentration of one trap, second buried layer is higher than second trap.
6. semiconductor structure according to claim 1, which is characterized in that the semiconductor structure further includes：
One third doped region is formed among second trap, contacts the ditching type grid, and have the second conductive type
State.
7. semiconductor structure according to claim 6, which is characterized in that second doped region contacts the ditching type grid
One the first side wall of pole, the third doped region contact a second sidewall of the ditching type grid, and the first side wall is opposite
In the second sidewall.
8. semiconductor structure according to claim 1, which is characterized in that the ditching type grid does not penetrate described first
Buried layer.
9. semiconductor structure according to claim 1, which is characterized in that first buried layer and second buried layer
Between have a gap.
10. semiconductor structure according to claim 1, which is characterized in that the semiconductor structure further includes：
One the 4th doped region is formed among first trap, and has the second conductive type state, wherein described first and the
Four doped regions couple one first plain conductor；
One the 5th doped region is formed among second trap, and has the third conductivity, wherein first doping
Area, the ditching type grid and the 5th doped region couple one second plain conductor.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104123648 | 2015-07-22 | ||
| TW104123648A TWI555163B (en) | 2015-07-22 | 2015-07-22 | Semiconductor structure |
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| Publication Number | Publication Date |
|---|---|
| CN106373942A CN106373942A (en) | 2017-02-01 |
| CN106373942B true CN106373942B (en) | 2018-11-27 |
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| CN201510666469.3A Active CN106373942B (en) | 2015-07-22 | 2015-10-15 | Semiconductor structure |
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| TW (1) | TWI555163B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1913148A (en) * | 2005-08-09 | 2007-02-14 | 台湾积体电路制造股份有限公司 | ESD protection device and semiconductor chip |
| CN102054835A (en) * | 2009-10-28 | 2011-05-11 | 上海宏力半导体制造有限公司 | Thyristor for electrostatic discharge |
| CN104009087A (en) * | 2014-05-29 | 2014-08-27 | 深圳市盛元半导体有限公司 | Electrostatic shielding effect transistor and design method thereof |
| CN104269396A (en) * | 2014-09-26 | 2015-01-07 | 武汉新芯集成电路制造有限公司 | Parasitic thyristor and electrostatic protection circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6586317B1 (en) * | 2001-05-08 | 2003-07-01 | National Semiconductor Corporation | Method of forming a zener diode in a npn and pnp bipolar process flow that requires no additional steps to set the breakdown voltage |
| CN103199017B (en) * | 2003-12-30 | 2016-08-03 | 飞兆半导体公司 | Form buried conductive layer method, material thickness control methods, form transistor method |
| US7372083B2 (en) * | 2005-08-09 | 2008-05-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Embedded silicon-controlled rectifier (SCR) for HVPMOS ESD protection |
| US8648419B2 (en) * | 2010-01-20 | 2014-02-11 | Freescale Semiconductor, Inc. | ESD protection device and method |
| DE102010005715B4 (en) * | 2010-01-26 | 2016-10-20 | Austriamicrosystems Ag | Transistor arrangement as ESD protection measure |
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2015
- 2015-07-22 TW TW104123648A patent/TWI555163B/en active
- 2015-10-15 CN CN201510666469.3A patent/CN106373942B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1913148A (en) * | 2005-08-09 | 2007-02-14 | 台湾积体电路制造股份有限公司 | ESD protection device and semiconductor chip |
| CN102054835A (en) * | 2009-10-28 | 2011-05-11 | 上海宏力半导体制造有限公司 | Thyristor for electrostatic discharge |
| CN104009087A (en) * | 2014-05-29 | 2014-08-27 | 深圳市盛元半导体有限公司 | Electrostatic shielding effect transistor and design method thereof |
| CN104269396A (en) * | 2014-09-26 | 2015-01-07 | 武汉新芯集成电路制造有限公司 | Parasitic thyristor and electrostatic protection circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201705433A (en) | 2017-02-01 |
| CN106373942A (en) | 2017-02-01 |
| TWI555163B (en) | 2016-10-21 |
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