CN106371972A - Bus monitoring method and device for ensuring data consistency among primary equipment - Google Patents

Bus monitoring method and device for ensuring data consistency among primary equipment Download PDF

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Publication number
CN106371972A
CN106371972A CN201610780725.6A CN201610780725A CN106371972A CN 106371972 A CN106371972 A CN 106371972A CN 201610780725 A CN201610780725 A CN 201610780725A CN 106371972 A CN106371972 A CN 106371972A
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Prior art keywords
bus
information
main equipment
data consistency
caching
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CN201610780725.6A
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CN106371972B (en
Inventor
王粟
肖佐楠
郑茳
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TIANJIN TIANXIN TECHNOLOGY CO LTD
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TIANJIN TIANXIN TECHNOLOGY CO LTD
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/3003Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3027Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a bus
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/3055Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Debugging And Monitoring (AREA)

Abstract

The invention provides a bus monitoring method and device for ensuring data consistency among primary equipment, and aims to solve the problem of consistency maintenance of shared data between primary equipment with cache and other primary equipment. Through the bus monitoring method, an access request for the shared data on a bus can be monitored in real time, multi-path comparison is performed on internally-stored history bus data, and whether a data consistency problem occurs currently between certain two pieces of primary equipment or not is judged through multi-level judgment. When the presence of a data consistency risk is judged, interruption is launched to relevant primary equipment, so that corresponding primary equipment can eliminate the current data consistency risk as soon as possible by interrupting a processing program.

Description

For solving the method for monitoring bus of data consistency and device between main equipment
Technical field
The invention belongs to IC chip intraconnection bus field, especially relate to one kind and be used for solving between main equipment The method for monitoring bus of data consistency and device.
Background technology
In a soc (system on chip, system-on-a-chip), generally comprise several main equipments and from equipment, In main equipment between equipment, it is connected by the bus of specific protocol, to realize the transmission of data.When multiple main equipments it Between, share some data within certain a period of time, and wherein at least one main equipment, open caching (cache) to accelerate The read-write efficiency of shared data, then cached between the main equipment of shared data and other main equipments, data one will be produced Cause sex chromosome mosaicism.I.e. when certain main equipment is modified to shared data, other cached this shared data main equipment it is impossible to By bus on chip, know that this data is modified.Above-mentioned situation can lead to the main equipment having cached shared data to be led with other Equipment, the inconsistent risk of shared data value.
One typical scene of the shared data consistency problem between multiple main equipments is as shown in Figure 1.With caching The main equipment #1 of main equipment #0 and no caching, by bus on chip, is connected with from equipment #2.Main equipment #0 and #1 can pass through To the operation being read or write from equipment #2, main equipment #0, first from have read a shared data from equipment #2, being worth and is bus X0, and this data is stored in the caching of oneself, afterwards, main equipment #1 is changed to this shared data from equipment #2 Write, value is changed into x1, afterwards, when main equipment #0 again reads off this shared data, due to the value of the shared data of storage in its caching It is still x0, leads to the main equipment #0 could not be from reading new value x1 from equipment #2, that is, main equipment #0 and main equipment #1 there occurs number According to inconsistence problems.
In order to tackle the data inconsistence problems between the above-mentioned many main equipments leading to due to caching, typically there are two kinds of solutions Method: one is the method allowing multiple main equipments share L2 cache, and the method treatment effeciency is very high, but main equipment is had higher Requirement, typically require main equipment will observe the complicated monitoring protocols of certain set in architecture design, the therefore suitability will be relatively low, right The quantity of main equipment is also restricted, is commonly used on the data syn-chronization between 1 to 4 same type processor.Second method is by altogether Enjoy data configuration and become non-caching data, the method is solved although there being the high suitability by way of software, but damage Lose the performance when reading shared data for the main equipment.When multiple main equipments with caching, need repeatedly to read and write shared data When, the performance loss that the method is brought is particularly acute.
Content of the invention
In view of this, it is contemplated that proposing a kind of method for monitoring bus for solving data consistency between main equipment, When occurring can initiating in time when data is inconsistent between main equipment to interrupt, eliminate risk.
For reaching above-mentioned purpose, the technical scheme is that and be achieved in that:
A kind of method for monitoring bus for solving data consistency between main equipment, specifically includes following steps:
(1) receive the signal that bus sends, bus signals carried out parsing, extract, pack and storing, judge to pass in real time Defeated address information whether there is identical address information in the address information of bus historical information;
(2) if there is identical address information, then enter read-write and judge, whether judge that Current bus access is to write behaviour Make, if YES, then initiate interrupt requests, corresponding bus historical information is removed meanwhile;If not, not processing;
(3) if there is no identical address information, then enter caching and read (cacheline read) judgement, judge current Whether bus access is caching read operation, if it is, the real time information that storage Current bus access;If not, not doing Process.
Further, in described step (1), the information after bus parsing includes address information, reading writing information, main equipment Number information, and caching opening imformation.
With respect to prior art, a kind of monitoring bus side for solving data consistency between main equipment of the present invention Method has the advantage that
Method of the present invention can be in real-time monitoring bus to shared data access request, and with internal bus Historical data carries out multichannel comparison, according to the judgement of multi-layer, judges currently whether occur in that the data between certain two main equipment Consistency problem, when judgement is implicitly present in data consistency risk, it will initiates to interrupt to related main equipment, makes corresponding main equipment As early as possible current data consistency risk is eliminated by interrupt handling routine, treatment effeciency of the present invention is high, strong applicability.
Another object of the present invention is to proposing a kind of bus guardian for solving data consistency between main equipment, To realize, when occurring can initiating to interrupt to main equipment in time when data is inconsistent between main equipment, eliminating risk.
For reaching above-mentioned purpose, the technical scheme is that and be achieved in that:
A kind of bus guardian for solving data consistency between main equipment, including
Receive the signal that bus sends, the bus resolver that bus signals are parsed for parsing;
Information for storing and resolving and the storage device of bus historical information;
Sentence for judging the address of bus real time information and multiple bus historical information address whether identical address being mated Disconnected device;
For judge Current bus access be whether write operation read-write judgment means;
Whether it is that the caching caching read operation reads judgment means for judging that Current bus access.
Further, also include screening depositor in address in described bus resolver.
Described a kind of it is used for solving to lead for solving the bus guardian of data consistency and above-mentioned one kind between main equipment The bus guardian of equipment room data consistency is had the advantage that identical with respect to prior art, will not be described here.
Brief description
The accompanying drawing constituting the part of the present invention is used for providing a further understanding of the present invention, the schematic reality of the present invention Apply example and its illustrate, for explaining the present invention, not constituting inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 for the present invention one simplification many main equipments system-on-a-chip structural representation;
Fig. 2 is the connection in the system-on-a-chip based on many main equipments of bus guardian described in the embodiment of the present invention Relation;
Fig. 3 is the flow chart of the monitoring method described in the embodiment of the present invention.
Specific embodiment
It should be noted that in the case of not conflicting, the embodiment in the present invention and the feature in embodiment can phases Mutually combine.
To describe the present invention below with reference to the accompanying drawings and in conjunction with the embodiments in detail.
Method for monitoring bus for solving the Data Consistency between multiple main equipments of the present invention, monitoring dress Put annexation with the master and slave equipment of bus as shown in Fig. 2 in bus in system-on-a-chip, hang with m (m >=1) carry slow Deposit the main equipment of function, n (n >=1) is without the main equipment of caching function, and x (x >=1) is from equipment.The present invention's is total Line supervising device be articulated in bus from device port it is possible to any one the m main equipment with caching function Or multiple initiation interrupt requests.
Method for monitoring bus of the present invention, monitors the access request that each main equipment is initiated to bus, judges certain Between two main equipments (1 in m main equipment 2 or 1 in m main equipment and n main equipment), currently whether deposit In Data Consistency, if it is present initiating to interrupt to the related main equipment with caching function, notify this main equipment Pass through interrupt processing function as early as possible, release current Data Consistency.
Method for monitoring bus flow chart of the present invention is as shown in figure 3, the knot of bus guardian of the present invention Structure at least includes 3 parts:
(1) bus resolver, is responsible for receiving the bus transfer signal sending after bus arbitration, opens including transmission Open information, address information, reading writing information, main equipment number information and caching opening imformation.Bus resolver receive information Afterwards, first filter out effective address information, reading writing information, main equipment number information and caching according to transmission opening imformation to open Open information;
Then address information one side is passed to storage device to be indexed, on the other hand pass to address discriminating gear and carry out Address compares.Additionally, in bus resolver, configurable address screening depositor can be added when necessary, be used for into The address filtering of one step.
(2) storage device, one piece of storage array being used for the historical information that storage is extracted through bus resolver, this is deposited The index address of storage array is a part for the bus address extracting through bus resolver, and the storage content of this storage array is History reading writing information through the packing of bus resolver, history main equipment number information and history buffer information.This storage battle array Depending on the size of row is according to situations such as the addressing range of system-on-a-chip, the distribution of shared data, each memory element corresponding The buffer unit of individual or multiple main equipment.In the micro structure of storage array, the buffer structure that is connected using multichannel group realizing, To improve the utilization rate of storage array.
(3) address matching judgment device
The bus real time information that bus resolver is sent and multiple bus historical information are compared one by one, detect whether The historical information on You Mou road is identical with the extraction address of real time information, if identical, enter read-write and judges;If no With then entrance caching reads (cacheline read) judgement.
(4) judgment means are read and write
Whether on the basis of the matching judgment of address, judging that the Current bus that bus resolver is sent access is write operation, If it is, initiating interrupt requests to related main equipment, to notify this main equipment to process current Data Consistency in time, Meanwhile, by corresponding bus historical information, remove from storage device;If it is not, then not processing.
(5) caching reads judgment means
Whether judge that the Current bus that bus resolver is sent access on the basis of address matching judgment device is caching Read operation, if it is, notifying bus resolver, the real time information that Current bus are accessed, is stored in the storage of correspondence position In device, if it is not, then not processing.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all essences in the present invention Within god and principle, any modification, equivalent substitution and improvement made etc., should be included within the scope of the present invention.

Claims (4)

1. a kind of method for monitoring bus for solving data consistency between main equipment it is characterised in that: specifically include following step Rapid:
(1) receive the signal that bus sends, bus signals are carried out parsing, extract, pack and storing, judges the ground of real-time Transmission Location information whether there is identical address information in the address information of bus historical information;
(2) if there is identical address information, then enter read-write and judge, whether be write operation, such as if judging that Current bus access Fruit is yes, then initiate interrupt requests, corresponding bus historical information is removed meanwhile;If not, not processing;
(3) if there is no identical address information, then enter caching and read (cacheline read) judgement, judge Current bus Whether access is caching read operation, if it is, the real time information that storage Current bus access;If not, not processing.
2. a kind of method for monitoring bus for solving data consistency between main equipment according to claim 1, its feature It is: in described step (1), the information after bus parsing includes address information, reading writing information, main equipment number information, and Caching opening imformation.
3. a kind of bus guardian for solving data consistency between main equipment it is characterised in that: include
Receive the signal that bus sends, the bus resolver that bus signals are parsed for parsing;
Information for storing and resolving and the storage device of bus historical information;
For judging the address of bus real time information and multiple bus historical information address whether identical address matching judgment dress Put;
For judge Current bus access be whether write operation read-write judgment means;
Whether it is that the caching caching read operation reads judgment means for judging that Current bus access.
4. a kind of bus guardian for solving data consistency between main equipment according to claim 3, its feature It is: in described bus resolver, also include address screening depositor.
CN201610780725.6A 2016-08-31 2016-08-31 For solving the method for monitoring bus and device of data consistency between main equipment Active CN106371972B (en)

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Cited By (4)

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CN107454072A (en) * 2017-07-28 2017-12-08 中国人民解放军信息工程大学 A kind of control methods of multichannel data content and device
CN108694181A (en) * 2017-04-06 2018-10-23 上海寒武纪信息科技有限公司 A kind of data screening device and method
CN110361979A (en) * 2019-07-19 2019-10-22 北京交大思诺科技股份有限公司 A kind of safety computer platform in railway signal field
US11010338B2 (en) 2017-04-06 2021-05-18 Shanghai Cambricon Information Technology Co., Ltd Data screening device and method

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CN101676887A (en) * 2008-08-15 2010-03-24 北京北大众志微***科技有限责任公司 Bus monitoring method and apparatus based on AHB bus structure
CN102609380A (en) * 2012-02-14 2012-07-25 福州瑞芯微电子有限公司 SDRAM (synchronous dynamic random access memory) controller data writing quick response method based on AXI (advanced extensible interface) bus

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US5987571A (en) * 1996-04-24 1999-11-16 Hitachi, Ltd. Cache coherency control method and multi-processor system using the same
CN1932783A (en) * 2005-09-16 2007-03-21 松下电器产业株式会社 Memory control apparatus
CN101135993A (en) * 2007-09-20 2008-03-05 华为技术有限公司 Embedded system chip and data read-write processing method
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CN101676887A (en) * 2008-08-15 2010-03-24 北京北大众志微***科技有限责任公司 Bus monitoring method and apparatus based on AHB bus structure
CN102609380A (en) * 2012-02-14 2012-07-25 福州瑞芯微电子有限公司 SDRAM (synchronous dynamic random access memory) controller data writing quick response method based on AXI (advanced extensible interface) bus

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Publication number Priority date Publication date Assignee Title
CN108694181A (en) * 2017-04-06 2018-10-23 上海寒武纪信息科技有限公司 A kind of data screening device and method
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