CN106371957A - PCIe bus determining method, verifying board and verifying system - Google Patents
PCIe bus determining method, verifying board and verifying system Download PDFInfo
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- CN106371957A CN106371957A CN201610767511.5A CN201610767511A CN106371957A CN 106371957 A CN106371957 A CN 106371957A CN 201610767511 A CN201610767511 A CN 201610767511A CN 106371957 A CN106371957 A CN 106371957A
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
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Abstract
The invention provides a PCIe bus determining method, a verifying board and a verifying system. The verifying board comprises at least one laminate layer and at least one line group, wherein at least one line group corresponds to at least one actual PCIe bus one by one; each line group in at least one line group comprises at least two test PCIe buses; at least two test PCIe buses of each line group are arranged on at least one laminate layer; at least two test PCIe buses of each line group correspond to different lengths; the attributes of at least two test PCIe buses of each line group are same as those of the actual PCIe bus corresponding to the line group; and one end of each test PCIe bus is connected with an external signal transmission board and receives a test signal input by the signal transmission board, and the other end of each test PCIe bus is connected with external signal test equipment and outputs the test signal to the signal test equipment. According to the scheme, the length of the PCIe bus can be determined so as to guarantee the signal integrity.
Description
Technical Field
The present invention relates to the field of test technologies, and in particular, to a method for determining a Peripheral component interconnect Express (PCIe) bus, a verification board, and a verification system.
Background
With the advent of the cloud computing era, the development of the server rises rapidly, the signal rate is higher and higher in the design of a mainboard of the server, and the requirement of a high-speed signal on the integrity of the signal is also continuously improved.
In the design of a server mainboard, the length of a PCIe bus is generally required to be guaranteed to be within a SPEC range, so that the requirement of signal integrity can be met when signals are transmitted on the PCIe bus.
However, in the actual design of the boards such as the motherboard, the backplane, the network card, etc., it is often necessary that the length of the PCIe bus exceeds the SPEC range, and how to determine the length of the PCIe bus, so that the PCIe bus can ensure the integrity of signals, which becomes a problem to be solved urgently.
Disclosure of Invention
The embodiment of the invention provides a PCIe bus determining method, a verification board and a verification system, which are used for determining the length of a PCIe bus so as to ensure the integrity of signals.
A verification board comprising: at least one stack and at least one wire set;
the at least one wire group corresponds to at least one actual PCIe bus on an external board card to be built one by one;
each of the at least one wire set, comprising: at least two test PCIe buses;
at least two test PCIe buses included in each wire set are arranged on the at least one laminated layer;
at least two PCIe testing buses included in each wire group correspond to different lengths;
the attributes of at least two tested PCIe buses included in each wire group are the same as the attributes of the actual PCIe buses corresponding to the wire group;
one end of each PCIe bus is used for connecting an external signal transmitting board and receiving the test signal input by the signal transmitting board, and the other end of each PCIe bus is used for connecting external signal testing equipment and outputting the test signal to the signal testing equipment.
Preferably, the first and second electrodes are formed of a metal,
the number of the at least one lamination is the same as that of the lamination of the board card to be created;
the arrangement mode of at least two test PCIe buses included in each wire group on the at least one laminated layer is the same as the arrangement mode of the actual PCIe bus corresponding to the wire group on the board to be created.
Preferably, the lengths of the at least two PCIe buses included in each wire group are distributed in a gradient according to the corresponding length threshold.
Preferably, the first and second electrodes are formed of a metal,
when the actual PCIe bus corresponds to a differential trace pair, the attributes include: the line width of the differential routing line pair and the line distance of the differential routing line pair;
when the actual PCIe bus corresponds to a single trace, the attribute includes: the line width of the single trace.
A verification system, comprising: a signal emitting board, a signal testing device and a verification board as described in any of the above; wherein,
the signal transmitting board is connected with a target test PCIe bus on the verification board and used for generating a test signal and outputting the generated test signal to the target test PCIe bus;
the signal test equipment is connected with the target test PCIe bus and used for receiving the test signal output by the target test PCIe bus and testing the signal integrity of the received test signal.
Preferably, the signal testing apparatus includes: an oscilloscope; wherein,
the oscilloscope is connected with the target test PCIe bus and used for receiving the test signal output by the target test PCIe bus and generating a corresponding eye pattern according to the received test signal.
Preferably, the signal testing apparatus includes: a comparator; wherein,
the comparator is connected with the target test PCIe bus and the signal transmitting board and is used for receiving the test signal output by the target test PCIe bus, receiving the test signal output by the signal transmitting board, comparing the test signal output by the target test PCIe bus with the test signal output by the signal transmitting board and outputting a comparison result.
Preferably, the authentication system further comprises: a display device; wherein,
the display equipment is connected with the signal testing equipment and used for receiving the testing result output by the signal testing equipment and displaying the testing result.
A method for determining a PCIe bus based on any one of the above authentication systems, comprising:
s1: determining the attribute of a target actual PCIe bus to be arranged in a board card to be constructed;
s2: determining a corresponding target line group in the verification board according to the attribute of the target actual PCIe bus, and selecting a target test PCIe bus in the target line group;
s3: connecting the target test bus with the signal transmitting board and the signal test equipment;
s4: generating a test signal by using the signal transmitting board, outputting the generated test signal to the target test PCIe bus, outputting the received test signal to the signal test equipment by using the target test PCIe bus, and testing the signal integrity of the received test signal by using the signal test equipment;
s5: according to the test result of the signal test equipment, reselecting a test PCIe bus in the target line group, taking the reselected test PCIe bus as a target test PCIe bus, and continuing to execute S3 until a final test PCIe bus is determined and executing S6, wherein the length of the final test PCIe bus is the maximum length which meets the signal integrity in the target line group;
s6: and determining the maximum length corresponding to the target actual PCIe bus according to the length of the final test PCIe bus.
Preferably, when the signal transmitting board includes a connection PCIe bus connected to the target test PCIe bus, the determining the maximum length corresponding to the target actual PCIe bus according to the length of the final test PCIe bus includes: calculating the corresponding maximum length of the target actual PCIe bus by utilizing a first formula;
the first formula includes:
Lmax＝L1+L2
wherein L ismaxFor characterizing the target actual PCIe bus correspondencesThe maximum length of (d); l is1For characterizing the length of the final test PCIe bus; l is2For characterizing the length of the connected PCIe bus.
The embodiment of the invention provides a determination method of a PCIe bus, a verification board and a verification system, wherein at least one wire set is arranged in the verification board, the at least one wire set corresponds to at least one actual PCIe bus to be arranged on a board card to be constructed one by one, each wire set comprises at least two tested PCIe buses with different lengths, when the length of a target actual PCIe bus to be arranged in the board card to be constructed is determined, a test signal output by a signal transmitting board can be transmitted according to at least two tested PCIe buses which are arranged in a target wire set corresponding to the target actual PCIe bus, so that signal integrity of the test signal can be tested by using signal test equipment, and a final tested PCIe bus which is arranged in the target wire set can be determined according to a test result, so that the target actual PCIe bus to be arranged on the board card to be constructed can be determined on the premise of meeting the signal integrity according to the length of the final tested PCIe bus, the maximum length can be selected.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic plan view of a verification board provided in accordance with an embodiment of the present invention;
FIG. 2 is a block diagram of a verification system provided in accordance with an embodiment of the present invention;
FIG. 3 is a block diagram of another authentication system provided by one embodiment of the present invention;
FIG. 4 is a block diagram of yet another authentication system provided by one embodiment of the present invention;
FIG. 5 is a block diagram of yet another authentication system provided by one embodiment of the present invention;
FIG. 6 is a flow chart of a method provided by one embodiment of the present invention;
fig. 7 is a flow chart of another method provided by an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer and more complete, the technical solutions in the embodiments of the present invention will be described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention, and based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the scope of the present invention.
An embodiment of the present invention provides a verification board, including: at least one stack and at least one wire set;
the at least one wire group corresponds to at least one actual PCIe bus on an external board card to be built one by one;
each of the at least one wire set, comprising: at least two test PCIe buses;
at least two test PCIe buses included in each wire set are arranged on the at least one laminated layer;
at least two PCIe testing buses included in each wire group correspond to different lengths;
the attributes of at least two tested PCIe buses included in each wire group are the same as the attributes of the actual PCIe buses corresponding to the wire group;
one end of each PCIe bus is used for connecting an external signal transmitting board and receiving the test signal input by the signal transmitting board, and the other end of each PCIe bus is used for connecting external signal testing equipment and outputting the test signal to the signal testing equipment.
Wherein, this integrated circuit board to be built can include at least: at least one of a motherboard, a backplane, and a network card.
In the prior art, in order to determine that the length of an actual PCIe bus arranged on a board card to be constructed can ensure that the signal integrity of a transmitted signal meets requirements when the actual PCIe bus transmits the signal after the board card to be constructed is constructed, the board cards corresponding to actual PCIe buses with different lengths need to be constructed respectively, and a signal transmission test is performed on each constructed board card, and the length of the actual PCIe bus corresponding to the board card with a test result meeting the signal integrity is taken as the determined length, so that the cost in the prior art is high.
By utilizing the verification board provided by the embodiment of the invention, only one verification board is required to be manufactured, the lengths of all the actual PCIe buses required to be arranged on the board card to be built can be verified, only the corresponding target line groups on the verification board are determined according to the attributes of the target actual PCIe buses required to be arranged on the board card to be built, one PCIe bus to be tested can be selected from the target line group to be used as a target PCIe bus to be tested, the target PCIe bus to be tested is connected with an external signal transmitting board and an external signal testing device, the testing signal output by the signal transmitting board can be output to the signal testing equipment, the selectable maximum length corresponding to the target actual PCIe bus is determined by utilizing the integrity testing result of the signal testing equipment on the testing signal, the length of the target actual PCIe bus can be rapidly determined, the cost can be reduced, and the accuracy of length determination is improved.
Please refer to fig. 1, which is a schematic plan view of a verification board. Assuming that the actual PCIe buses to be arranged on the board to be built are 4 and the attribute of each actual PCIe bus is different, for example, the 4 actual PCIe buses are the actual PCIe bus 1, the actual PCIe bus 2, the actual PCIe bus 3, and the actual PCIe bus 4, respectively, so in fig. 1, the verification board includes 4 wire groups, which are: the PCIe bus comprises an A wire group, a B wire group, a C wire group and a D wire group, wherein each wire group corresponds to an actual PCIe bus. Each wire group comprises n PCIe buses to be tested, and n is an integer not less than 2.
In fig. 1, each PCIe test bus included in each wire group corresponds to an input interface and an output interface, where the input interface is used to connect to an external signal transmitting board, and the output interface is used to connect to an external signal testing device.
In order to ensure that the verification workload can be reduced as much as possible in the verification process, the corresponding input interfaces in each line group may be integrated into one connector, or the output interfaces in each line group may be integrated into one connector. For example, in this embodiment, the corresponding input interface in each line group is integrated into one connector, so in the verification process, the determined connector of the target line group may be connected to an external signal transmitting board, and the output interface of the target test PCIe bus selected in the target line group is connected to an external signal testing device. Therefore, the workload of disconnecting the input end interface of the current target test PCIe bus from the signal transmitting board and connecting the input end interface of the next target test PCIe bus to the signal transmitting board can be reduced.
In an embodiment of the present invention, the number of stacked layers of the verification board may be at least one, for example, the verification board includes a stacked layer, the PCIe buses to be tested included in each line group are all arranged on the stacked layer, and the lengths of the actual PCIe buses to be arranged on the board to be built are verified by using each line group.
In an embodiment of the present invention, since the signal transmission effect of the PCIe bus disposed on the same stack is different from the signal transmission effect of the PCIe bus disposed on different stacks, in order to improve the accuracy of the verification of the actual PCIe bus length, the number of the at least one stack is the same as the number of stacks of the board card to be created; for example, if the number of stacked layers of the board to be built is 8, the verification board includes 8 stacked layers.
In order to further improve the accuracy of the verification of the length of the actual PCIe bus, the arrangement manner of the at least two test PCIe buses included in each line group on the at least one overlay is the same as the arrangement manner of the actual PCIe bus corresponding to the line group on the board to be created.
For example, the arrangement manner of the actual PCIe bus 1 on the board to be built is arranged at the first layer of the board to be built, and then the arrangement manner of the n test PCIe buses on the line group a corresponding to the actual PCIe bus 1 is also arranged at the first layer of the verification board. Since the signal transmission effect of the PCIe bus arranged on the first layer and the signal transmission effect of the PCIe bus arranged on the bottom layer are the same, the n PCIe buses under test on the wire group a may also be arranged on the bottom layer of the verification board.
For another example, the actual PCIe bus 2 is arranged on the second layer of the board card to be built, and is further arranged on the fifth layer of the board card to be built through the via hole, so that the arrangement of the n test PCIe buses on the line group B corresponding to the actual PCIe bus 2 is also arranged on the second layer of the verification board, and is further arranged on the fifth layer of the verification board through the via hole.
In an embodiment of the present invention, in order to determine the maximum length of the actual PCIe bus, the lengths of at least two test PCIe buses included in each line group in the verification board may be distributed in a gradient manner according to corresponding length thresholds.
The corresponding length thresholds in different line groups may be equal or unequal. The present embodiment is described with the same as an example.
The length threshold may be set prior to the fabrication of the verification board. The larger the length threshold is set, the faster the speed of obtaining the maximum length of the actual PCIe bus in verification is; the smaller the length threshold is set, the more accurate the maximum length of the actual PCIe bus is obtained during verification. For example, the length threshold is 1 mil.
Taking the example that the wire group a includes 20 PCIe test buses, in order to ensure that the maximum length of the actual PCIe bus can be determined according to the 20 PCIe test buses, the length range of the 20 PCIe test buses needs to include a SPEC range. For example, the SPEC range specifies that the lengths of PCIe buses on boards such as a motherboard, a backplane, and a network card need not be greater than 15 mils, and then the lengths corresponding to the 20 test PCIe buses may be: 10mil, 11mil, 12mil, … … mil, 29 mil.
In an embodiment of the present invention, in order to further improve the accuracy of the length verification of the actual PCIe bus, it is necessary to ensure that the attribute of each tested PCIe bus in the wire group is the same as the attribute of the corresponding actual PCIe bus. The bus arranged on the board card can include two types: the first type is a differential wire pair and the second type is a single wire. Wherein:
when the actual PCIe bus corresponds to a differential trace pair, the attributes include: the line width of the differential routing line pair and the line distance of the differential routing line pair;
when the actual PCIe bus corresponds to a single trace, the attribute includes: the line width of the single trace.
For example, the accuracy of length determination is further improved, and the thickness, shape and size of the laminated layer of the verification board and the used material can be the same as those of the board card to be built.
Referring to fig. 2, an embodiment of the present invention provides a verification system, which may include: a signal emitting board 201, a signal testing device 202 and a verification board 203 as described in any of the above; wherein,
the signal transmitting board 201 is connected with a target test PCIe bus on the verification board 203, and is configured to generate a test signal and output the generated test signal to the target test PCIe bus;
the signal testing device 202 is connected to the target test PCIe bus, and configured to receive a test signal output by the target test PCIe bus and test signal integrity of the received test signal.
Therefore, according to the verification system provided by the embodiment of the invention, the signal transmitting board can be used for generating the test signal, the target test PCIe bus connected with the signal transmitting board and the signal test equipment in the verification board is used for transmitting the test signal, the signal test equipment is used for testing the integrity of the transmitted test signal, and the maximum length of the actual PCIe bus can be determined according to the test result.
Wherein, after the target test PCIe bus of the verification board is connected with the signal transmitting board and the signal test equipment, a complete signal loop can be formed.
In one embodiment of the present invention, to achieve signal integrity of the test signal, at least two ways are available as follows:
mode 1: the test was performed using an oscilloscope.
Mode 2: the test was performed using a comparator.
The following describes the verification system provided in the embodiment of the present invention with respect to the above two modes, respectively.
With respect to the mode 1:
in the mode 1, referring to fig. 3, the signal testing apparatus may include: an oscilloscope 2021. The oscilloscope 2021 is connected to the target test PCIe bus, and is configured to receive a test signal output by the target test PCIe bus and generate a corresponding eye diagram according to the received test signal.
The eye diagram is a graph formed by overlapping each symbol waveform obtained by scanning due to afterglow of an oscilloscope, and refers to a graph observed on an oscilloscope when the performance of a transmission system is estimated and improved (by adjustment) by using an experimental method. The eye pattern contains rich information, the influence of intersymbol interference and noise can be observed from the eye pattern, the integral characteristic of the digital signal is reflected, and the quality degree of the system can be estimated, so that whether the signal transmitted by the target test PCIe bus meets the integrity requirement or not can be judged according to the eye pattern generated by the oscilloscope.
With respect to the mode 2: in the mode 2, referring to fig. 4, the signal testing apparatus may include: a comparator 2022. The comparator 2022 is connected to the target test PCIe bus, connected to the signal transmitting board, and configured to receive the test signal output by the target test PCIe bus, receive the test signal output by the signal transmitting board, compare the test signal output by the target test PCIe bus with the test signal output by the signal transmitting board, and output a comparison result.
If the intensity difference between the test signal 1 output by the signal transmitting board to the comparator and the test signal 2 output by the target test PCIe bus to the comparator is greater than the comparison threshold, outputting a comparison result with the integrity of the signal which does not meet the requirement; and if the intensity difference is not greater than the comparison threshold, outputting a comparison result with the signal integrity meeting the requirement.
In an embodiment of the present invention, in order to obtain the test result of the signal testing apparatus, referring to fig. 5, the verification system may further include: a display device 501; wherein,
the display device 501 is connected to the signal testing device, and is configured to receive the test result output by the signal testing device and display the test result.
When the display device is connected with the oscilloscope, the display device also needs to determine whether the test signal meets the test result of the requirement of signal integrity according to the eye pattern. When the display device is connected to the comparator, the display device may directly display the test result including the comparison result.
Referring to fig. 6, an embodiment of the present invention further provides a method for determining a PCIe bus based on any one of the above verification systems, where the method may include the following steps:
step 601: determining the attribute of a target actual PCIe bus to be arranged in a board card to be constructed;
step 602: determining a corresponding target line group in the verification board according to the attribute of the target actual PCIe bus, and selecting a target test PCIe bus in the target line group;
step 603: connecting the target test bus with the signal transmitting board and the signal test equipment;
step 604: generating a test signal by using the signal transmitting board, outputting the generated test signal to the target test PCIe bus, outputting the received test signal to the signal test equipment by using the target test PCIe bus, and testing the signal integrity of the received test signal by using the signal test equipment;
step 605: according to the test result of the signal test equipment, reselecting a test PCIe bus in the target line group, taking the reselected test PCIe bus as a target test PCIe bus, and continuing to execute the step 603 until a final test PCIe bus is determined, and executing the step 606, wherein the length of the final test PCIe bus is the maximum length which meets the signal integrity in the target line group;
step 606: and determining the maximum length corresponding to the target actual PCIe bus according to the length of the final test PCIe bus.
It can be seen that, according to the above embodiment of the present invention, by setting at least one line group in the verification board, where the at least one line group corresponds to at least one actual PCIe bus to be arranged on the board to be built one by one, and each line group includes at least two test PCIe buses with different lengths, when determining the length of the target actual PCIe bus to be arranged in the board to be built, the test signal output by the signal transmitting board may be transmitted according to the at least two test PCIe buses included in the target line group corresponding to the target actual PCIe bus, so as to test the signal integrity of the test signal by using the signal testing device, and determine the final test PCIe bus included in the target line group according to the test result, so that on the premise that the target actual PCIe bus to be arranged on the board to be built satisfies the signal integrity can be determined according to the length of the final test PCIe bus, the maximum length can be selected.
In an embodiment of the present invention, when a target PCIe bus is connected to a signal transmitting board, the target PCIe bus may be directly connected to a signal transmitting end of the signal transmitting board, and if an input port of each line group on the verification board is integrated into one connector, a PCIe bus may be led out from the signal transmitting end of the signal transmitting board, and the PCIe bus is connected to the connector, so that, when a PCIe bus connected to the target PCIe bus is included in the signal transmitting board, the maximum length corresponding to the target PCIe bus is determined according to the length of the final PCIe bus to be tested, which includes: calculating the corresponding maximum length of the target actual PCIe bus by using a formula (1);
Lmax＝L1+L2(1)
wherein L ismaxThe maximum length corresponding to the target actual PCIe bus is characterized; l is1For characterizing the length of the final test PCIe bus; l is2For characterizing the length of the connected PCIe bus.
The following further describes the method for determining the PCIe bus provided in the embodiment of the present invention by taking a signal testing device as an oscilloscope and verifying an integrated connector of an input port of a line group on a board as an example, with reference to fig. 7, where the method may include:
step 701: determining the number of actual PCIe buses to be arranged in the board card to be built, and manufacturing a verification board according to the board card to be built.
For example, the number of actual PCIe buses of the required arrangement is 4. Namely: real PCIe bus 1, real PCIe bus 2, real PCIe bus 3, and real PCIe bus 4.
Step 702: among the several actual PCIe buses whose lengths are not determined, one actual PCIe bus is selected as the target actual PCIe bus.
The selection may be made in order, for example, selecting the actual PCIe bus 1 first, selecting the actual PCIe bus 2, selecting the actual PCIe bus 3, and finally selecting the actual PCIe bus 4.
Step 703: determining the attribute of a target actual PCIe bus, determining a corresponding target line group in a verification board according to the attribute of the target actual PCIe bus, and connecting a connector of the target line group with the PCIe bus of the signal emission board; one of the tested PCIe buses in the target line set is selected as a target tested PCIe bus.
Taking the differential wire pairs corresponding to the actual PCIe bus as an example, the attribute includes: the line width of the differential routing and the distance between the differential routing pairs.
For example, the real PCIe bus 1 corresponds to the wire group a, the real PCIe bus 2 corresponds to the wire group B, the real PCIe bus 3 corresponds to the wire group C, and the real PCIe bus 4 corresponds to the wire group D.
In this embodiment, when the PCIe bus to be tested is selected from the target line group for the first time, the PCIe bus to be tested may be selected according to the maximum length specified in the SPCE range, for example, the maximum length specified in the SPEC range of the PCIe bus on the motherboard is 15 mils, and when the PCIe bus to be tested is selected from the target line group, the PCIe bus to be tested that is close to or equal to 15 mils may be selected as the PCIe bus to be tested.
Step 704: and connecting an output end interface of the target test PCIe bus with an oscilloscope.
Step 705: and generating a test signal by using a signal transmitting end of the signal transmitting board, outputting the generated test signal to the target test PCIe bus, and outputting the received test signal to the signal test equipment by using the target test PCIe bus.
Step 706: testing the signal integrity of the received test signal by using the signal test equipment, if the test result is that the signal integrity does not meet the requirement, selecting a test PCIe bus with the length smaller than that of the target test PCIe bus in the target line group, and executing step 704 by taking the selected test PCIe bus as the target test PCIe bus until the final test PCIe bus is determined; if the test result is that the signal integrity meets the requirement, a test PCIe bus with the length larger than that of the target test PCIe bus is selected from the target line group, and the selected test PCIe bus is taken as the target test PCIe bus to execute step 704 until the final test PCIe bus is determined.
Wherein the final test PCIe bus is a maximum length that enables the integrity of the transmitted signal to meet the integrity requirement.
Step 707: and determining the maximum length corresponding to the target actual PCIe bus according to the length of the final test PCIe bus and the length of the PCIe bus connected to the signal transmitting board, executing step 702 until the maximum lengths of the actual PCIe buses to be arranged in the board card to be built are determined, and executing step 708.
Wherein, the maximum length corresponding to the target actual PCIe bus is: the sum of the length of the final test PCIe bus and the length of the connection PCIe bus.
Step 708: and constructing a corresponding board card according to the determined maximum length of each practical PCIe bus.
In summary, the embodiments of the present invention have at least the following advantages:
1. in the embodiment of the invention, by arranging at least one wire group in the verification board, wherein the at least one wire group corresponds to at least one actual PCIe bus to be arranged on the board card to be built one by one, and each wire group comprises at least two test PCIe buses with different lengths, when the length of a target actual PCIe bus to be arranged in the board card to be built is determined, a test signal output by the signal transmitting board can be transmitted according to the at least two test PCIe buses included in a target wire group corresponding to the target actual PCIe bus, so that the signal integrity of the test signal is tested by using the signal test equipment, and the final test PCIe bus included in the target wire group is determined according to the test result, so that the target actual PCIe bus to be arranged on the board card to be built can be determined according to the length of the final test PCIe bus under the premise of meeting the signal integrity, the maximum length can be selected.
2. In the embodiment of the invention, the lengths of all the actual PCIe buses required to be arranged on the board card to be constructed can be verified only by manufacturing one verification board, and the verification board can not only quickly determine the length of the target actual PCIe bus, but also reduce the cost and improve the accuracy of length determination.
3. In the embodiment of the invention, by integrating the corresponding input end interface in each wire group into one connector, or integrating the output end interface in each wire group into one connector, when the change of the PCIe bus is tested in the verification process, only one end which is not the connector needs to be plugged and pulled, thereby reducing the verification workload.
4. In the embodiment of the invention, the number of the laminated layers of the verification board is set to be the same as that of the laminated layers of the board to be built, and the arrangement mode of at least two PCIe test buses included in the wire group on the laminated layers of the verification board is the same as that of the corresponding actual PCIe buses of the wire group on the board to be built, so that the accuracy rate of determining the length of the actual PCIe buses can be improved.
5. In the embodiment of the invention, the lengths of at least two PCIe buses to be tested in each wire group are set in a gradient manner according to the corresponding length threshold value, so that the length determination result can be ensured to be more accurate.
Because the information interaction, execution process, and other contents between the units in the device are based on the same concept as the method embodiment of the present invention, specific contents may refer to the description in the method embodiment of the present invention, and are not described herein again.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a" does not exclude the presence of other similar elements in a process, method, article, or apparatus that comprises the element.
Those of ordinary skill in the art will understand that: all or part of the steps for realizing the method embodiments can be completed by hardware related to program instructions, the program can be stored in a computer readable storage medium, and the program executes the steps comprising the method embodiments when executed; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
Finally, it is to be noted that: the above description is only a preferred embodiment of the present invention, and is only used to illustrate the technical solutions of the present invention, and not to limit the protection scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.
Claims (10)
1. A verification board, comprising: at least one stack and at least one wire set;
the at least one wire group corresponds to at least one actual PCIe bus on an external board card to be built one by one;
each of the at least one wire set, comprising: at least two test PCIe buses;
at least two test PCIe buses included in each wire set are arranged on the at least one laminated layer;
at least two PCIe testing buses included in each wire group correspond to different lengths;
the attributes of at least two tested PCIe buses included in each wire group are the same as the attributes of the actual PCIe buses corresponding to the wire group;
one end of each PCIe bus is used for connecting an external signal transmitting board and receiving the test signal input by the signal transmitting board, and the other end of each PCIe bus is used for connecting external signal testing equipment and outputting the test signal to the signal testing equipment.
2. Verification board according to claim 1,
the number of the at least one lamination is the same as that of the lamination of the board card to be created;
the arrangement mode of at least two test PCIe buses included in each wire group on the at least one laminated layer is the same as the arrangement mode of the actual PCIe bus corresponding to the wire group on the board to be created.
3. The verification board of claim 1, wherein the lengths of the at least two PCIe under test buses included in each wire set are distributed in a gradient according to a respective length threshold.
4. Verification board according to any of claims 1-3,
when the actual PCIe bus corresponds to a differential trace pair, the attributes include: the line width of the differential routing line pair and the line distance of the differential routing line pair;
when the actual PCIe bus corresponds to a single trace, the attribute includes: the line width of the single trace.
5. An authentication system, comprising: a signal emitting board, a signal testing device and a verification board according to any one of claims 1-4; wherein,
the signal transmitting board is connected with a target test PCIe bus on the verification board and used for generating a test signal and outputting the generated test signal to the target test PCIe bus;
the signal test equipment is connected with the target test PCIe bus and used for receiving the test signal output by the target test PCIe bus and testing the signal integrity of the received test signal.
6. The verification system according to claim 5, wherein the signal testing apparatus comprises: an oscilloscope; wherein,
the oscilloscope is connected with the target test PCIe bus and used for receiving the test signal output by the target test PCIe bus and generating a corresponding eye pattern according to the received test signal.
7. The verification system according to claim 5, wherein the signal testing apparatus comprises: a comparator; wherein,
the comparator is connected with the target test PCIe bus and the signal transmitting board and is used for receiving the test signal output by the target test PCIe bus, receiving the test signal output by the signal transmitting board, comparing the test signal output by the target test PCIe bus with the test signal output by the signal transmitting board and outputting a comparison result.
8. The authentication system according to any one of claims 5-7, wherein the authentication system further comprises: a display device; wherein,
the display equipment is connected with the signal testing equipment and used for receiving the testing result output by the signal testing equipment and displaying the testing result.
9. A method for determining a PCIe bus based on the authentication system of any one of claims 5 to 8, comprising:
s1: determining the attribute of a target actual PCIe bus to be arranged in a board card to be constructed;
s2: determining a corresponding target line group in the verification board according to the attribute of the target actual PCIe bus, and selecting a target test PCIe bus in the target line group;
s3: connecting the target test bus with the signal transmitting board and the signal test equipment;
s4: generating a test signal by using the signal transmitting board, outputting the generated test signal to the target test PCIe bus, outputting the received test signal to the signal test equipment by using the target test PCIe bus, and testing the signal integrity of the received test signal by using the signal test equipment;
s5: according to the test result of the signal test equipment, reselecting a test PCIe bus in the target line group, taking the reselected test PCIe bus as a target test PCIe bus, and continuing to execute S3 until a final test PCIe bus is determined and executing S6, wherein the length of the final test PCIe bus is the maximum length which meets the signal integrity in the target line group;
s6: and determining the maximum length corresponding to the target actual PCIe bus according to the length of the final test PCIe bus.
10. The method of claim 9, wherein when the signal transmitter board includes a connection PCIe bus connected to the target test PCIe bus, the determining the maximum length corresponding to the target actual PCIe bus according to the length of the final test PCIe bus includes: calculating the corresponding maximum length of the target actual PCIe bus by utilizing a first formula;
the first formula includes:
Lmax＝L1+L2
wherein L ismaxThe maximum length corresponding to the target actual PCIe bus is characterized; l is1For characterizing the final test PCLength of Ie bus; l is2For characterizing the length of the connected PCIe bus.
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