CN106371943A - LDPC (low density parity check) decoding optimization method based on flash programming interference error perception - Google Patents

Abstract

The invention discloses an LDPC (low density parity check) decoding optimization method based on flash programming interference error perception. Along with the increase of NAND flash-memory storage density, more bit information is stored in each unit; the coupling interference along the units is high; the serious programming interference errors are caused, so that the traditional BCH code cannot ensure the data reliability; the LDPC code has error-correcting performance superior to that of the BCH code, and is applied to an NAND flash-memory storage system. The used optimized LDPC decoding algorithm has important significance. Through observation, the programming interference errors have value correlative characters; when the LDPC decoding is performed, the value correlative characters of the programming interference errors can be blended into the LDPC decoding process; the additional information is provided for bit judgment, so that the bit judgment precision is improved; the decoding convergence speed is accelerated; the LDPC decoding delay is reduced.

Description

A kind of ldpc decoding optimization method programming interference false perception based on flash

Technical field

The invention belongs to solid-state disk technical field of memory, more particularly, to a kind of based on flash programming interference mistake sense The ldpc decoding optimization method known.

Background technology

Solid-state disk (solid state disk, abbreviation ssd) based on nand flash memory has high-performance, Large Copacity, antidetonation Dynamic, low-power consumption and non-volatile the advantages of be widely used in computer memory system.Solid-state disk ssd is with nand flash memory (nand Flash) as storage medium, with the lifting of nand flash memory making technology, each unit stores more bit information, such as Mlc each unit of nand flash memory stores dibit information, stores the distance between less electric charge and unit relatively closely in unit, Coupled interference between unit is more strong, in nand flash memory during some page execution programming operation, can be to neighbouring page Interfere, cause the memory element threshold voltage of neighbouring page to change, threshold voltage transfers to another from a state State, when executing read operation, there are bit-errors in the impact due to programming interference, the reliability of data is destroyed.In order to Ensure data reliability, error correcting code (error correction code, abbreviation ecc) is applied to the controller of nand flash memory In, such as bch code and ldpc code, traditional method adopts bch code to ensure data reliability.But, the storage of nand flash memory is held Amount is increasing, and the Capacitance Coupled between memory element is more strong, the bit error rate more and more higher that programming interference causes, Bch code is not enough to competent guarantee data reliability, at this time, it may be necessary to using the higher error correcting code of correction capability, ldpc code is to be better than The error-correcting performance of bch code is applied to nand flash memory.

Ldpc code is a kind of linear block codes, and its error correction property is determined by a kind of referred to as openness test matrix, So-called sparse test matrix is exactly in matrix 0 quantity far more than 1 for the quantity, and the every a line in matrix corresponds to an inspection party Journey (also referred to as checks node), and every a line corresponds to a bit node (corresponding with each bit in code word), test matrix It is capable of the represented (as depicted in figs. 1 and 2) by tanner figure of image, the c of tanner in figure_i(1≤i≤m) and test matrix In row corresponding, the v of tanner in figure_j(1≤j≤m) is corresponding with the row in test matrix, if in test matrix I row and jth row are 1, then tanner in figure c_iAnd v_jBetween have a line be connected.When carrying out ldpc decoding, these sides are used for Reliability information (probabilistic information of bit correctness) required for transmission decoding.

Ldpc decoding is the process that a kind of reliability information is propagated, and is a kind of Soft decision decoding, has complex translating Code structure, if directly can bring larger decoding latency expense using ldpc code if it is possible to wrong mould by nand flash memory During formula is fused to ldpc decoding, is provided for ldpc decoding using the nand flash media error characteristic of itself and judge bit just The really extraneous information of property, then, so can lift judgement precision and the convergence rate of ldpc decoding, reduce decoding latency and open Pin.In addition, we learn that the programming interference mistake of nand flash memory has numerical lineardependence feature, that is, in mlc nand flash cell The bit data of the different conditions of storage can show different error rates (as shown in Figure 3) in the presence of having programming interference, main The programming interference mistake wanted is 11 → 10 and 10 → 01, and their ratio is 70% and 24% respectively, and other programming interference are wrong It is 10 → 00,11 → 01 and 01 → 00, their relative ratios are 2.2%, 1.5% and 0.4% respectively by mistake.Translate when carrying out ldpc During code, these features are dissolved into decoding process, provide extra information to improve decoding precision reduction with this for bit decision and translate Code delay.Existing ldpc decoding algorithm has probability domain belief propagation algorithm, Min-Sum decoding algorithm etc..

There is following clearly disadvantageous part in existing ldpc decoding algorithm: 1, existing ldpc decoding algorithm is only examined Information transmission within considering does not make full use of the error pattern feature of flash itself, has higher decoding complexity and relatively Big decoding latency expense；2nd, existing ldpc decoding algorithm does not account for programming the shadow of the numerical lineardependence feature of interference mistake Ring, this favorable characteristics are not dissolved into ldpc decoding information renewal process；3rd, existing ldpc decoding algorithm is not extra Discriminative information provide, the characteristic that simple dependence decodes mechanism itself carries out information updating.

Content of the invention

Disadvantages described above for prior art or Improvement requirement, the invention provides a kind of wrong based on flash programming interference The ldpc decoding optimization method that false sense is known, it is intended that by being dissolved into the numerical lineardependence feature of programming interference mistake During ldpc decoding, provide extra information for bit decision, effectively raise ldpc decoding accuracy and reduce decoding Postpone expense, and then improve the reading performance of system and the life-span extending ssd.

For achieving the above object, according to one aspect of the present invention, there is provided a kind of programming based on flash disturbs mistake sense The ldpc decoding optimization method known, comprises the following steps:

(1) random generation test matrix h, its element is 0 or 1, and code check is between 0.75 to 0.9, and there is not becate Phenomenon；Line number m of wherein test matrix is to be obtained by (ssd page-size/(ssd page-size+m))=code check, checks square The columns of battle array is ssd page-size+m；

(2) column vector (code word) is generated according to the test matrix h generatingSo that it is met Wherein column vectorIn rear m be designated as redundancy function, remaining be designated as information bit；

(3) according to the check matrix h generating and column vectorConstruct corresponding tanner figure, it embodies inspection equation c₁, c₂,…,c_mWith column vectorBetween mapping relations；

(4) use 0 and 1 pair of column vectorIn element v₁To v_n-mCarry out random assignment, and use formulaCalculate The column vector obtainingIn element v_n-mTo v_nValue, thus generating multiple column vectors, and the column vector that these are generated includesIt is stored in the way of sequential write successively in the page of ssd up to the page is filled with；

(5) the multiple column vectors in the page being written to ssd are sequential read out and carry out error correction, wherein note makes a mistake Column vector isThis column vector is

(6) obtain column vectorIn each element initial reliability information, and according to reliability information, each element is turned Be changed to binary system, will reliability information be negative value element be converted to 1, by reliability information be on the occasion of element be converted to 0, Thus obtaining new column vector

(7) by check matrix h and column vectorBe multiplied, and judge be multiplied after generate each inspection equation whether be zero Vector, if it is by column vectorExport to user, process terminates, otherwise proceed to step (8)；

(8) according to the column vector obtaining in step (6)In each element initial reliability information i_j, to each code word ratio Spy carries out initialization and is entered asWherein when entering row decoding first time iteration, the variable node reliability information of acquisition is For initial value i_j,

$v_{ij}^{\′k}=i_j(1\≤i\≤m,1\≤j\≤n,i\&element;r(j),j\&element;q(i\left)\right)$

Wherein i ∈ r (j) represents and variable node v_jConnected all inspection node c_iSet, j ∈ q (i) represent with inspection Test node c_iConnected all variable node v_jSet；

(9) enumerator k=1 is set；

(10) judge k whether less than default maximum iteration time t_max, if it is, proceeding to step (11), if it is not, then Process terminates, and by final codeword vector output, and prompts the user with decoding failure；

(11) according to step (8) to initializaing variable node valuationAnd test node using below equation can By property information updating:

$c_{ij}^k=\underset{m\&element;q\left(i\right)\backslash j}{\π}\mathrm{sgn}\left(v_{im}^{\′k}\right)\·min\left\{\right|v_{im}^{\′k}|:m\&element;q\left(i\right)\backslash j\}$

Wherein be sign function, q (i) j represent with inspection node c_iV is excluded in connected all bit nodes_jSet.

(12) judge inspection node in step (11)Update and whether terminate, if it is not, then return to step (11), if It is then to enter step (13)；

(14) according to the inspection node reliability information being updated in step (12)Become using below equation Amount node reliability information updates:

$v_{ij}^{\′k}=y_j+\underset{n\&element;r\left(j\right)\backslash i}{\σ}{c}_{nj}^k+a_j,$

Wherein a_jIt is the additional bit discriminative information being provided by the numerical lineardependence of flash programming interference mistake, incorporated To variable node reliability information renewal process, wherein r (j) i represent and v_jC is excluded in connected all inspection nodes_iCollection Close, the reliability information of variable node is expressed as: the variable node being attached thereto when this inspection equation is set up is equal to 0 or 1 Probability；

(14) judge the variable node reliability information in step (13)Update and whether terminate, if it is not, then returning step Suddenly (13), if it is, entering step (15)；

(15) use below equation to inspection nodeEnter row decoding to adjudicate:

$v_j^{\′k}=y_j+\underset{i\&element;r\left(j\right)}{\σ}{c}_{ij}^k+a_j$

(16) reliability information corresponding to each code word bits is obtained according to the result of step (15) decoding judgement

(17) hard decision is carried out to the reliability information obtaining in step (16), that is, determine whether If it is 0 is assigned to a_j, then proceed to step (18), be otherwise assigned to a by 1_j, then proceed to step (18)；

(18) codeword vector adjudicated according to the result acquisition of hard decision in step (17)

(19) whether the codeword vector generating in testing sequence (18) meets inspection equationWherein h is raw in (1) The test matrix becoming, if it is satisfied, then direct output codons vectorProcess terminates, if be unsatisfactory for, Iterationses k is gradually added 1, and return to step (10) continues iterative operation, till meeting.

Preferably, step (6) is specifically, the reliability information of each element is the threshold value of the unit being stored by element Voltage compares acquisition with predetermined reference voltage；Obtain reliability formula beWherein v_tvBe through with ginseng Examine the threshold voltage of each unit of voltage ratio relatively acquisition, v_iIt is the column vector reading from unitIn element and each The threshold voltage Normal Distribution of flash unit.

Preferably, maximum iteration time t_maxSpan 20 to 50.

Preferably, the reliability information of inspection node is expressed as: when variable node information is judged as 0 or 1 with its phase The probability that inspection equation even is set up.

Preferably, step (15) is specifically, change each element according to the reliability information that step (14) has been updated over For binary system, will reliability information be that the element of negative value be converted to 1, by reliability information be on the occasion of element be converted to 0.

In general, by the contemplated above technical scheme of the present invention compared with prior art, can obtain down and show Beneficial effect:

(1) present invention takes into full account the nand flash memory error property of itself, well by the numerical value phase of programming interference mistake Close property characteristic use arrive ldpc decoding among because ldpc decode process transmit be exactly a kind of probabilistic information, if with regard to than The extra discriminative information of special correctness can be dissolved into decoding information process, and decoding correctness can be greatly improved, and this is right Improve decoding handling capacity and nand flash memory reading performance is of great benefit to.

(2) present invention analyzes the programming of nand flash memory and disturbs the numerical lineardependence feature of error pattern that ldpc decoded Impact, obtains the observation of some valuable property using this numerical lineardependence feature, is translated into and can be incorporated into ldpc decoding In Related Mathematical Models, lifted using this characteristic decoding accuracy rate reduce decoding circulation.

(3) present invention, by the programming interference numerical lineardependence Feature Fusion of nand flash memory among ldpc decoding, is equivalent to Increase the judgement dimension of bit correctness, reduce information updating circulation, lifting nand flash memory reading performance and then lifting storage system The corresponding time of system.

Brief description

Fig. 1 and Fig. 2 is the test matrix corresponding tanner structure chart of existing ldpc code.

Fig. 3 is the numerical lineardependence scattergram of existing nand flash memory programming interference mistake.

Fig. 4 is that the present invention is based on flash misprogrammed pattern reduction ldpc decoding latency algorithm design structure diagram.

Fig. 5 is that the present invention programs, based on flash, the flow chart that interference error pattern reduces the method for ldpc decoding latency.

Specific embodiment

In order that the objects, technical solutions and advantages of the present invention become more apparent, below in conjunction with drawings and Examples, right The present invention is further elaborated.It should be appreciated that specific embodiment described herein is only in order to explain the present invention, and It is not used in the restriction present invention.As long as additionally, involved technical characteristic in each embodiment of invention described below The conflict of not constituting each other just can be mutually combined.

The structural design drawing of the present invention as shown in figure 4, when decoder receives a ldpc code word, each bit node v_jInitial reliability information p_i,i_kCan be obtained, based on the obtained initial reliability information of bit node, with this bit The inspection node c that node is connected_iThe reliability information of (seeing Fig. 1 and Fig. 2) can be calculated.These calculated inspection nodes Reliability information is used for updating acquisition bit node initial information, and the reliability information of this two classes node circulates on tanner figure Update so that disturbed ldpc codeword information can quickly be corrected.It is true that ldpc decoding information transmittance process is Calculate the maximum a posteriori probability of each code word bits correctness, be, when all of inspection equation is all set up, each code word ratio Top grade is in 0 or 1 correct probability.

The numerical lineardependence feature programming interference mistake is converted into corresponding mathematical model by the present invention, using inside programming Interference error pattern incorporates the mode of ldpc decoding node renewal, the precision of lifting decision bits correctness, translates when carrying out ldpc During code, bit node v_jRenewal can receive and program, from based on nand flash memory itself, the extra judgement letter that interference error characteristic provides Breath a_jIt is considered to the impact to decoding for the programming interference mistake, when ldpc decoder makes optimal judgement to bit, also can consider to compile The impact of journey interference, to improve decoding accurately by during the ldpc decoding of the numerical lineardependence Feature Fusion of programming interference with this Property, reduce decoding latency and then improve performance.

Ldpc decoding to lift decoding precision by the way of message loop iteration updates, and transmission is bit correctness Probabilistic information, is a kind of soft decision information, as shown in figure 5, the present invention is based on flash programming interference error pattern reduction ldpc translating The method of code delay comprises the following steps:

(1) random generation test matrix h, its element is 0 or 1, and code check is between 0.75 to 0.9, and there is not becate Phenomenon；According to this code check, and according to (ssd page-size/(ssd page-size+m))=code check, you can the m value of acquisition, m is inspection Test the line number (the redundant bit number for generating simultaneously) of matrix, the columns of test matrix is ssd page-size+m；

For example, the h matrix of generation isM=3；

(2) column vector (code word) is generated according to the test matrix h generatingSo that it is met Wherein column vectorIn rear m be designated as redundancy function, remaining be designated as information bit；

(3) according to the check matrix h generating and column vectorConstruct corresponding tanner figure tg, it embodies inspection equation c With column vectorBetween mapping relations；

Specifically, by h andLaunch after multiplication, m inspection equation can be obtained, be designated as c₁,c₂,…,c_m；

For example, using above-mentioned example, that is, have:

v₁+v₄=0 (i.e. c₁)

v₃+v₄=0 (i.e. c₂)

v₁+v₂=0 (i.e. c₃).

From the above it can be seen that v₁And v₄Take part in inspection equation c respectively₁Inspection, i.e. v₁And v₄Respectively with c₁It is connected, v₃And v₄Point Not take part in inspection equation c₂Inspection, i.e. v₃And v₄Respectively with c₂It is connected, v₁And v₂Take part in inspection equation c respectively₃Inspection, I.e. v₁And v₂Respectively with c₃It is connected (as shown in Figure 1), wherein column vectorIn each element v_iReferred to as variable node, checks equation c_i(1≤i≤m) is referred to as checking node.

(4) use 0 and 1 pair of column vectorIn element v₁To v_n-mCarry out random assignment, and use formulaCalculate The column vector obtainingIn element v_n-mTo v_nValue, according to above-mentioned method can generate multiple such column vectors and by this A little column vectors generating include(code word bits of as generation) are stored in the page of ssd always successively in the way of sequential write To the page is filled with；

(5) the multiple column vectors in the page being written to ssd are sequential read out and carry out error correction, when the column vector to storageWhen being read out, due to being affected by ssd channel programming interference noise, column vector therefore nowMay have occurred and that Mistake, the column vector being designated as making a mistake isThis column vector isIt should be noted thatEasily send out Raw bit-errors, i.e. the column vector of storage beforeIn each element it may happen that bit reversal；

(6) obtain column vectorIn each element initial reliability information (be each element correctness probability letter Breath, includes the channel characteristic information of solid-state disk in initial reliability information), and according to reliability information, each element is changed For binary system, will reliability information be that the element of negative value be converted to 1, by reliability information be on the occasion of element be converted to 0, from And obtain new column vectorSpecifically, the reliability information of each element is the threshold value of the unit being stored by element Voltage compares acquisition with predetermined reference voltage；Obtain reliability formula be(in order to reduce amount of calculation, this is public Probabilistic information can be converted into log-likelihood ratio information by formula), wherein v_tvIt is each list through comparing acquisition with reference voltage The threshold voltage of unit, v_iIt is the column vector reading from unitIn element and each flash unit threshold voltage obey Normal distribution；

(7) by check matrix h and column vectorBe multiplied, and judge be multiplied after generate each inspection equation whether be zero Vector, if it is by column vectorExport to user, process terminates, otherwise proceed to step (8)；

(8) according to the column vector obtaining in step (6)In the initial reliability information i of each element (code word bits)_j, right Each code word bits (variable node) carry out initialization and are entered asWherein when entering row decoding first time iteration, acquisition Variable node reliability information is initial value i_j,

$v_{ij}^{\′k}=i_j(1\≤i\≤m,1\≤j\≤n,i\&element;r(j),j\&element;q(i\left)\right)$

Wherein i ∈ r (j) represents and variable node v_jConnected all inspection node c_iSet, j ∈ q (i) represent with inspection Test node c_iConnected all variable node v_jSet；

(9) enumerator k=1 is set；

(10) judge k whether less than default maximum iteration time t_max, if it is, proceeding to step (11), if it is not, then Process terminates, and by final codeword vector output, and prompts the user with decoding failure；Specifically, maximum iteration time t_max's Span 20 to 50；

(11) according to step (8) to initializaing variable node valuationAnd test node using below equation can By property information updating:

$c_{ij}^k=\underset{m\&element;q\left(i\right)\backslash j}{\π}\mathrm{sgn}\left(v_{im}^{\′k}\right)\·min\left\{\right|v_{im}^{\′k}|:m\&element;q\left(i\right)\backslash j\}$

Wherein be sign function, q (i) j represent with inspection node c_iV is excluded in connected all bit nodes_jSet； The reliability information of inspection node is expressed as: the inspection equation coupled when variable node information is judged as 0 or 1 is set up Probability；

(12) judge inspection node in step (11)Update and whether terminate (to be each inspection being connected with variable node Whether equation is all examined), if it is not, then return to step (11), if it is, entering step (13)；

(15) according to the inspection node reliability information being updated in step (12)Become using below equation Amount node reliability information updates:

$v_{ij}^{\′k}=y_j+\underset{n\&element;r\left(j\right)\backslash i}{\σ}{c}_{nj}^k+a_j,$

Wherein a_jIt is the additional bit discriminative information being provided by the numerical lineardependence of flash programming interference mistake, incorporated To variable node reliability information renewal process, wherein r (j) i represent and v_jC is excluded in connected all inspection nodes_iCollection Close, the reliability information of variable node is expressed as: the variable node being attached thereto when this inspection equation is set up is equal to 0 or 1 Probability；

(14) judge the variable node reliability information in step (13)Update and whether terminate, if it is not, then returning step Suddenly (13), if it is, entering step (15)；

(15) use below equation to inspection node(i.e. the method according to step (6), according to step to enter row decoding judgement (14) be updated over reliability information each element is converted to binary system, will reliability information be negative value element conversion For 1, by reliability information be on the occasion of element be converted to 0):

$v_j^{\′k}=y_j+\underset{i\&element;r\left(j\right)}{\σ}{c}_{ij}^k+a_j$

(16) reliability information corresponding to each code word bits is obtained according to the result of step (15) decoding judgementIt to be one group of real number value (be each be real number) that this reliability information is corresponding；

(17) hard decision is carried out to the reliability information obtaining in step (16), that is, determine whether If it is 0 is assigned to a_j, then proceed to step (18), be otherwise assigned to a by 1_j, then proceed to step (18)；

(18) codeword vector adjudicated according to the result acquisition of hard decision in step (17)

(19) whether the codeword vector generating in testing sequence (18) meets inspection equationWherein h is raw in (1) The test matrix becoming, if it is satisfied, then direct output codons vectorProcess terminates, if be unsatisfactory for, Iterationses k is gradually added 1, and return to step (10) continues iterative operation, till meeting.

As it will be easily appreciated by one skilled in the art that the foregoing is only presently preferred embodiments of the present invention, not in order to Limit the present invention, all any modification, equivalent and improvement made within the spirit and principles in the present invention etc., all should comprise Within protection scope of the present invention.

Claims (5)

1. a kind of programming based on flash disturbs the ldpc decoding optimization method of false perception it is characterised in that walking below including Rapid:

(1) random generation test matrix h, its element is 0 or 1, and code check is between 0.75 to 0.9, and there is not becate phenomenon； Line number m of wherein test matrix is to be obtained by (ssd page-size/(ssd page-size+m))=code check, the row of test matrix Number is ssd page-size+m；

(2) column vector (code word) is generated according to the test matrix h generatingSo that it is metWherein Column vectorIn rear m be designated as redundancy function, remaining be designated as information bit；

(3) according to the check matrix h generating and column vectorConstruct corresponding tanner figure, it embodies inspection equation c₁, c₂,…,c_mWith column vectorBetween mapping relations；

(4) use 0 and 1 pair of column vectorIn element v₁To v_n-mCarry out random assignment, and use formulaCalculate and obtain Column vectorIn element v_n-mTo v_nValue, thus generating multiple column vectors, and the column vector that these are generated includesAccording to Secondary it is stored in the page of ssd until the page is filled with the way of sequential write；

(5) the multiple column vectors in the page being written to ssd are sequential read out and carry out error correction, wherein remember the row that make a mistake to Measure and beThis column vector is

(6) obtain column vectorIn each element initial reliability information, and according to reliability information, each element is converted to Binary system, will reliability information be negative value element be converted to 1, by reliability information be on the occasion of element be converted to 0, thus Obtain new column vector

(7) by check matrix h and column vectorBe multiplied, and judge be multiplied after generate each inspection equation whether be zero to Amount, if it is by column vectorExport to user, process terminates, otherwise proceed to step (8)；

(8) according to the column vector obtaining in step (6)In each element initial reliability information i_j, each code word bits is entered Row initialization is entered asWherein when entering row decoding first time iteration, the variable node reliability information of acquisition is just Initial value i_j,

$v_{ij}^{\′k}=i_j,(1\≤i\≤m,1\≤j\≤n,i\&element;r(j),j\&element;q(i\left)\right)$

Wherein i ∈ r (j) represents and variable node v_jConnected all inspection node c_iSet, j ∈ q (i) represent with inspection section Point c_iConnected all variable node v_jSet；

(9) enumerator k=1 is set；

(10) judge k whether less than default maximum iteration time t_max, if it is, proceeding to step (11), if it is not, then process Terminate, by final codeword vector output, and prompt the user with decoding failure；

(11) according to step (8) to initializaing variable node valuationAnd using below equation test node reliability letter Breath updates:

$c_{ij}^k=\underset{m\&element;q\left(i\right)\backslash j}{\π}sgn\left(v_{im}^{\′k}\right)\·min\left\{\right|v_{im}^{\′k}|:m\&element;q\left(i\right)\backslash j\}$

Wherein be sign function, q (i) j represent with inspection node c_iV is excluded in connected all bit nodes_jSet.

(12) judge inspection node in step (11)Update and whether terminate, if it is not, then return to step (11), if it is, Enter step (13)；

(13) according to the inspection node reliability information being updated in step (12)Variable section is carried out using below equation Point reliability information updating:

$v_{ij}^{\′k}=y_j+\underset{n\&element;r\left(j\right)\backslash i}{\mathrm{\σ}}{c}_{nj}^k+a_j,$

Wherein a_jIt is the additional bit discriminative information being provided by the numerical lineardependence of flash programming interference mistake, be dissolved into variable Node reliability information renewal process, wherein r (j) i represent and v_jC is excluded in connected all inspection nodes_iSet, variable The reliability information of node is expressed as: the probability that the variable node being attached thereto when this inspection equation is set up is equal to 0 or 1；

(14) judge the variable node reliability information in step (13)Update and whether terminate, if it is not, then return to step (13), if it is, entering step (15)；

(15) use below equation to inspection nodeEnter row decoding to adjudicate:

$v_j^{\′k}=y_j+\underset{i\&element;r\left(j\right)}{\mathrm{\σ}}{c}_{ij}^k+a_j$

(16) reliability information corresponding to each code word bits is obtained according to the result of step (15) decoding judgement

(17) hard decision is carried out to the reliability information obtaining in step (16), that is, determine whetherIf It is to be assigned to a by 0_j, then proceed to step (18), be otherwise assigned to a by 1_j, then proceed to step (18)；

(18) codeword vector adjudicated according to the result acquisition of hard decision in step (17)

(19) whether the codeword vector generating in testing sequence (18) meets inspection equationWherein h is to generate in (1) Test matrix, if it is satisfied, then direct output codons vectorProcess terminates, if be unsatisfactory for, will change Generation number k gradually adds 1, and return to step (10) continues iterative operation, till meeting.

2. the ldpc decoding optimization method programming interference false perception based on flash according to claim 1, its feature exists In step (6) is specifically, the reliability information of each element is the threshold voltage of the unit being stored by element and default ginseng Examine voltage ratio relatively to obtain；Obtain reliability formula beWherein v_tvIt is to obtain through comparing with reference voltage The threshold voltage of each unit obtaining, v_iIt is the column vector reading from unitIn element and each flash unit threshold Threshold voltage Normal Distribution.

3. the ldpc decoding optimization method programming interference false perception based on flash according to claim 1, its feature exists In maximum iteration time t_maxSpan 20 to 50.

4. the ldpc decoding optimization method programming interference false perception based on flash according to claim 1, its feature exists In the reliability information of inspection node is expressed as: the inspection equation coupled when variable node information is judged as 0 or 1 The probability set up.

5. the ldpc decoding optimization method programming interference false perception based on flash according to claim 1, its feature exists In step (15), will specifically, each element is converted to binary system according to the reliability information that step (14) has been updated over Reliability information be negative value element be converted to 1, by reliability information be on the occasion of element be converted to 0.