CN106371496A - Ultra-low voltage comparator circuit for maximum power point tracking (MPPT) circuit and MPPT circuit - Google Patents
Ultra-low voltage comparator circuit for maximum power point tracking (MPPT) circuit and MPPT circuit Download PDFInfo
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- CN106371496A CN106371496A CN201610949643.XA CN201610949643A CN106371496A CN 106371496 A CN106371496 A CN 106371496A CN 201610949643 A CN201610949643 A CN 201610949643A CN 106371496 A CN106371496 A CN 106371496A
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- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/66—Regulating electric power
- G05F1/67—Regulating electric power to the maximum power available from a generator, e.g. from solar cell
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Abstract
The invention relates to an ultra-low voltage comparator circuit for a maximum power point tracking (MPPT) circuit and the MPPT circuit. The ultra-low voltage comparator circuit comprises an in-phase input end (Vp), an inverted input end (Vn), an output end (VOUT), a first comparator, a subtracter and a second comparator. The first comparator and the subtracter are electrically connected with the in-phase input end (Vp) and the inverted input end (Vn), the subtracter is further electrically connected with the output end (VOUT), the output end of the first comparator and the second comparator, and the second comparator is electrically connected with the output end (VOUT) to output four modulating signals having different duty cycles. It can be guaranteed that input signals are quickly compared under a low voltage environment to obtain accurate duty ratio signals including adjusting direction and amplitude, it is ensured that the MPPT circuit makes maximized use of obtained input energy under conditions of micro power consumption, and conversion efficiency is improved.
Description
Technical field
The invention belongs to technical field of integrated circuits is and in particular to a kind of ultralow pressure comparator circuit for mppt circuit
And mppt circuit.
Background technology
Maximum power point tracking (maximum power point tracking, abbreviation mppt) circuit is a kind of according to defeated
Enter changed power to adjust output, so that the maximized converter circuit of input energy utilization rate, because it has effect
Rate is high, loss is low, small volume, life-span length the advantages of, and be widely used in energy harvesting technology.
Refer to Fig. 1, a kind of structural representation of mppt circuit that Fig. 1 provides for prior art.This mppt circuit includes:
Multiplier circuit, time-delay unit circuit, comparator circuit (com1), pwm comparator circuit (com2) and pierce circuit.Multiplication
Device circuit is responsible for calculating input power, after the time-lag action of delay unit, by input power p (n+1) of current period and
Input power p (n) in a upper cycle passes to comparator circuit com1 and is compared, and obtains duty cycle modulated signal vce, this tune
The signal deciding processed direction of pwm duty ratio modulation and amplitude；The sawtooth waveforms that modulated signal vce is provided with agitator passes through pwm
Comparator com2 is compared, and obtains pwm control signal.Therefore, comparator circuit have in mppt circuit very important
How effect, particularly when the input power is low, design a kind of ultralow pressure comparator circuit, defeated to adjacent periods to realize
Enter power fast and accurately to be compared, the design to high accuracy mppt circuit is most important.
Content of the invention
In order to solve the above-mentioned problems in the prior art, the invention provides a kind of ultralow pressure for mppt circuit
Comparator circuit and mppt control circuit it is intended to realize Micro Energy Lose input power is quickly compared, thus obtain accurately having
The duty cycle signals modulation direction of effect and amplitude.The technical problem to be solved in the present invention is achieved through the following technical solutions:
An embodiment provides a kind of ultralow pressure comparator circuit for mppt circuit, comprising:
In-phase input end vp；
Inverting input vn；
Outfan vout；
First comparator, is electrically connected to described in-phase input end vpAnd described inverting input vn, for defeated to described homophase
Enter to hold vpAnd described inverting input vnThe signal of input is compared to obtain the first control signal v of subtractoroa；
Described subtractor, electrically connects described in-phase input end vpAnd described inverting input vnState in-phase input end to receive
vpAnd described inverting input vnThe signal of input compares as two input signals of described subtractor, electrical connection described first
The outfan of device is to obtain described first control signal voa, electrically connect described outfan vout to obtain power supply voltage signal, electricity
Connect the second comparator to export the second control signal vobAnd the 3rd control signal voc；
Described second comparator, electrically connects described outfan vout, according to described second control signal vobAnd the described 3rd
Control signal vocThe modulated signal of four kinds of different duty of output.
In one embodiment of the invention, described first comparator include the first transistor m1, transistor seconds m2,
Three transistor m3, the 4th transistor m4；Wherein,
Described the first transistor m1 and described third transistor m3 are sequentially connected in series in described inverting input vnWith earth terminal
Between gnd；
Described transistor seconds m2 and described 4th transistor m4 is sequentially connected in series in described in-phase input end vpWith earth terminal
Between gnd；
The control end of described the first transistor m1 and described transistor seconds m2 is electrically connected to described the first transistor m1
Concatenate at the node a being formed with described third transistor m3, the control of described third transistor m3 and described 4th transistor m4
End is electrically connected to described in-phase input end vp；
Described transistor seconds m2 concatenates the node b being formed as described first comparator with described 4th transistor m4
Outfan is to export described first control signal voa.
In one embodiment of the invention, described the first transistor m1 and described transistor seconds m2 is pmos transistor
And its control end is the grid of pmos transistor, described third transistor m3 and described 4th transistor m4 be nmos transistor and
Its control end is the grid of nmos transistor.
In one embodiment of the invention, described subtraction circuit include the 5th transistor m5, the 6th transistor m6, the 7th
Transistor m7, the 8th transistor m8, the first variable connector and the second variable connector；Wherein,
Described 5th transistor m5 and described 6th transistor m6 is sequentially connected in series in described outfan vout and earth terminal gnd
Between, and its control end is electrically connected to the outfan of described first comparator；
Described 7th transistor m7 and described 8th transistor m8 is sequentially connected in series in described first variable connector and described the
Between two variable connectors, and its control end is respectively electrically connected to described in-phase input end vpWith described inverting input vn, its substrate
End is electrically connected to reference voltage source vdth；
Two inputs of described first variable connector are respectively electrically connected to described outfan vout and earth terminal gnd, its
Outfan is electrically connected to described 7th transistor m7 and its first control end s1 is electrically connected to the outfan of described first comparator,
Second control end s2 is electrically connected to described 5th transistor m5 and is concatenated with described 6th transistor m6 at the node c being formed；
Two inputs of described second variable connector are respectively electrically connected to described outfan vout and earth terminal gnd, its
Outfan is electrically connected to described 8th transistor m8 and its first control end s1 be electrically connected to described 5th transistor m5 with described
At the node c that 6th transistor m6 concatenation is formed, the second control end s2 is electrically connected to the outfan of described first comparator；
Described 5th transistor m5 is concatenated the node c being formed and exports described second control signal with described 6th transistor m6
vob, described 7th transistor m7 concatenate with described 8th transistor m8 formed node d as described subtractor outfan with
Export described 3rd control signal voc.
In one embodiment of the invention, for pmos transistor and its control end is that pmos is brilliant to described 5th transistor m5
The grid of body pipe, described 6th transistor m6, described 7th transistor m7 and described 8th transistor m8 be nmos transistor and
Its control end is the grid of nmos transistor.
In one embodiment of the invention, described first variable connector or described second variable connector include the 20th crystalline substance
Body pipe m20, the 21st transistor m21, the 20th two-transistor m22 and the 23rd transistor m23；Wherein,
Described 20th transistor m20 is electrically connected to described outfan vout and described first variable connector or described second
The outfan v of variable connectorosBetween and its control end is electrically connected to described first variable connector or described second variable connector
First control end s1；
Described 21st transistor m21 is electrically connected to described outfan vout and described first variable connector or described the
The outfan v of two variable connectorsosBetween and its control end is electrically connected to described first variable connector or described second variable connector
The second control end s2；
Described 20th two-transistor m22 is electrically connected to earth terminal gnd and described first variable connector or described more than second
The outfan v of way switchosBetween and its control end is electrically connected to the of described first variable connector or described second variable connector
Two control ends s2；
Described 23rd transistor m23 is electrically connected to earth terminal gnd and described first variable connector or described more than second
The outfan v of way switchosBetween and its control end is electrically connected to the of described first variable connector or described second variable connector
One control end s1.
In one embodiment of the invention, described 21st transistor m21 and described 23rd transistor m23 is
Pmos transistor and its control end are grid, described 20th transistor m20 and described 22nd crystal of pmos transistor
For nmos transistor and its control end is the grid of nmos transistor to pipe m22.
In one embodiment of the invention, described second comparator include the 9th transistor m9, the tenth transistor m10,
11st transistor m11, the tenth two-transistor m12, the 13rd transistor m13, the 14th transistor m14, the 15th transistor
M15, the 16th transistor m16, the 17th transistor m17, the 18th transistor m18, the 19th transistor m19, first resistor
R1, second resistance r2,3rd resistor r3, the first electric capacity c1 and the second electric capacity c2；Wherein,
Described 9th transistor m9 and described tenth two-transistor m12, described first resistor r1, described 16th transistor
M16 and described first electric capacity c1 is sequentially connected in series respectively between the outfan and earth terminal gnd of described subtraction circuit；
Described tenth transistor m10 and described 13rd transistor m13, described 14th transistor m14 and the described tenth
Five transistor m15, described second resistance r2 and described second electric capacity c2 are sequentially connected in series respectively in reference voltage source vdthWith earth terminal
Between gnd；
Described 11st transistor m11 is serially connected with the outfan of described subtraction circuit and described reference voltage source vdthBetween；
Described 17th transistor m17 is serially connected with the node that described second resistance r2 and described second electric capacity c2 concatenation are formed
At i and described outfan vout between；Described 3rd resistor r3 is serially connected between described outfan vout and earth terminal gnd；
Described 18th transistor m18 is serially connected with described 16th transistor m16 and described first electric capacity c1 concatenation is formed
Node h at and described outfan vout between；
Described 19th transistor m19 is serially connected with described reference voltage source vdthAnd described outfan vout between；
The control end of described 9th transistor m9 and described tenth transistor m10 is electrically connected to described 9th transistor m9
Concatenate with described tenth two-transistor m12 at the node e being formed, the control end of described 11st transistor m11 is electrically connected to institute
State the tenth transistor m10 and concatenate with described 13rd transistor m13 at the node f being formed, described tenth two-transistor m12 and institute
The control end stating the 13rd transistor m13 is electrically connected to the outfan of described subtraction circuit, described 14 transistor m14 and institute
The control end stating the 15th transistor m15 is electrically connected to described tenth transistor m10 and is concatenated with described 13rd transistor m13
At the node f being formed, the control end of described 16 transistor m16 and described 17th transistor m17 is electrically connected to described the
14 transistor m14 concatenate at the node g being formed with described 15th transistor m15, the control of described 18th transistor m18
End is electrically connected to described tenth transistor m10 and is concatenated with described 13rd transistor m13 at the node f being formed, and the described 19th
The control end of transistor m19 is electrically connected to described 5th transistor m5 and is concatenated with described 6th transistor m6 at the node c being formed
To input described second control signal vob.
In one embodiment of the invention, described 9th transistor m9, the tenth transistor m10, the 11st transistor
M11, the 14th transistor m14, the 16th transistor m16, the 17th transistor m17, the 18th transistor m18 and the 19th are brilliant
Body pipe m19 is the grid that pmos transistor and its control end are pmos transistor, described tenth two-transistor m12, the described tenth
For nmos transistor and its control end is the grid of nmos transistor to three transistor m13 and described 15th transistor m15.
An alternative embodiment of the invention provides a kind of mppt circuit, comprising: multiplier circuit, time-delay unit circuit,
Comparator circuit, pwm comparator circuit and pierce circuit, wherein, described comparator circuit is institute arbitrary in above-described embodiment
The ultralow pressure comparator circuit stated.
The ultralow pressure comparator circuit of the embodiment of the present invention ensure that under lower pressure environment, realizes fast to input signal
Speed ratio relatively, obtains accurate duty cycle signals, including adjustment direction and amplitude it is ensured that mppt circuit is under the conditions of Micro Energy Lose,
Bigization utilizes acquired input energy, improves conversion efficiency.
Due to adopting technique scheme, compared with prior art, the ultralow pressure comparator circuit of the present invention, Neng Gou
Under lower pressure, input signal is compared fast and accurately, according to comparative result, the pwm adjusting mppt circuit controls
Signal dutyfactor, thus improving the conversion efficiency of integrated circuit, makes capacity usage ratio maximize.The present invention can be used for mppt circuit
In.
Brief description
A kind of structural representation of mppt circuit that Fig. 1 provides for prior art；
Fig. 2 is a kind of principle schematic of ultralow pressure comparator circuit provided in an embodiment of the present invention；
Fig. 3 is a kind of electrical block diagram of first comparator provided in an embodiment of the present invention；
Fig. 4 is a kind of electrical block diagram of subtraction circuit provided in an embodiment of the present invention；
Fig. 5 is a kind of electrical block diagram of variable connector provided in an embodiment of the present invention；
Fig. 6 is a kind of electrical block diagram of second comparator provided in an embodiment of the present invention；
Fig. 7 is a kind of electrical block diagram of ultralow pressure comparator circuit provided in an embodiment of the present invention.
Specific embodiment
With reference to specific embodiment, further detailed description is done to the present invention, but embodiments of the present invention are not limited to
This.
Embodiment one
Refer to Fig. 2, Fig. 2 is a kind of principle schematic of ultralow pressure comparator circuit provided in an embodiment of the present invention.Should
Ultralow pressure comparator circuit includes: in-phase input end vp；Inverting input vn；Outfan vout；First comparator, is electrically connected to
Described in-phase input end vpAnd described inverting input vn, for described in-phase input end vpAnd described inverting input vnDefeated
The signal entering is compared to obtain the first control signal v of subtractoroa；Described subtractor, electrically connects described in-phase input end
vpAnd described inverting input vnState in-phase input end v to receivepAnd described inverting input vnThe signal of input subtracts as described
Two input signals of musical instruments used in a Buddhist or Taoist mass, the outfan electrically connecting described first comparator is to obtain described first control signal voa, it is electrically connected
Meet described outfan vout to obtain power supply voltage signal, electrical connection the second comparator is to export the second control signal vobAnd the 3rd
Control signal voc；Described second comparator, electrically connects described outfan vout, according to described second control signal vobAnd it is described
3rd control signal vocThe modulated signal of four kinds of different duty of output.
Refer to Fig. 3, Fig. 3 is a kind of electrical block diagram of first comparator provided in an embodiment of the present invention.Described
First comparator includes the first transistor m1, transistor seconds m2, third transistor m3, the 4th transistor m4；Wherein, described
One transistor m1 and described third transistor m3 are sequentially connected in series in described inverting input vnAnd earth terminal gnd between；Described
Two-transistor m2 and described 4th transistor m4 is sequentially connected in series in described in-phase input end vpAnd earth terminal gnd between；Described
The control end of one transistor m1 and described transistor seconds m2 is electrically connected to described the first transistor m1 and described 3rd crystal
At the node a that pipe m3 concatenation is formed, the control end of described third transistor m3 and described 4th transistor m4 is electrically connected to institute
State in-phase input end vp；Described transistor seconds m2 concatenates the node b being formed as described first with described 4th transistor m4
The outfan of comparator is to export described first control signal voa.
Refer to Fig. 4, Fig. 4 is a kind of electrical block diagram of subtraction circuit provided in an embodiment of the present invention.Described subtract
Method circuit include the 5th transistor m5, the 6th transistor m6, the 7th transistor m7, the 8th transistor m8, the first variable connector and
Second variable connector；Wherein, described 5th transistor m5 and described 6th transistor m6 is sequentially connected in series in described outfan vout
And earth terminal gnd between, and its control end is electrically connected to the outfan of described first comparator；Described 7th transistor m7 and
Described 8th transistor m8 is sequentially connected in series between described first variable connector and described second variable connector, and its control end is divided
It is not electrically connected to described in-phase input end vpWith described inverting input vn, its substrate terminal is electrically connected to reference voltage source vdth；
Two inputs of described first variable connector are respectively electrically connected to described outfan vout and earth terminal gnd, its outfan electricity
Connect to described 7th transistor m7 and its first control end s1 is electrically connected to the outfan of described first comparator, the second control
End s2 is electrically connected to described 5th transistor m5 and is concatenated with described 6th transistor m6 at the node c being formed；Described second multichannel
Two inputs of switch are respectively electrically connected to described outfan vout and earth terminal gnd, and its outfan is electrically connected to described the
Eight transistor m8 and its first control end s1 is electrically connected to described 5th transistor m5 and concatenates formation with described 6th transistor m6
Node c at, the second control end s2 is electrically connected to the outfan of described first comparator；Described 5th transistor m5 and described the
The node c that six transistor m6 concatenations are formed exports described second control signal vob, described 7th transistor m7 is brilliant with the described 8th
Body pipe m8 concatenates the node d being formed as the outfan of described subtractor to export described 3rd control signal voc.
Refer to Fig. 5, Fig. 5 is a kind of electrical block diagram of variable connector provided in an embodiment of the present invention.Described
One variable connector or described second variable connector include the 20th transistor m20, the 21st transistor m21, the 22nd crystalline substance
Body pipe m22 and the 23rd transistor m23；Wherein, described 20th transistor m20 is electrically connected to described outfan vout and institute
State the first variable connector or the outfan v of described second variable connectorosBetween and its control end is electrically connected to described first multichannel
Switch or the first control end s1 of described second variable connector；Described 21st transistor m21 is electrically connected to described outfan
The vout and outfan v of described first variable connector or described second variable connectorosBetween and its control end be electrically connected to described
First variable connector or the second control end s2 of described second variable connector；Described 20th two-transistor m22 is electrically connected to and connects
Ground terminal gnd and the outfan v of described first variable connector or described second variable connectorosBetween and its control end is electrically connected to institute
State the first variable connector or the second control end s2 of described second variable connector；Described 23rd transistor m23 is electrically connected to
The earth terminal gnd and outfan v of described first variable connector or described second variable connectorosBetween and its control end be electrically connected to
Described first variable connector or the first control end s1 of described second variable connector.
Refer to Fig. 6, Fig. 6 is a kind of electrical block diagram of second comparator provided in an embodiment of the present invention.Described
Second comparator include the 9th transistor m9, the tenth transistor m10, the 11st transistor m11, the tenth two-transistor m12, the tenth
Three transistor m13, the 14th transistor m14, the 15th transistor m15, the 16th transistor m16, the 17th transistor m17,
18th transistor m18, the 19th transistor m19, first resistor r1, second resistance r2,3rd resistor r3, the first electric capacity c1 and
Second electric capacity c2；Wherein, described 9th transistor m9 and described tenth two-transistor m12, described first resistor r1, the described tenth
Six transistor m16 and described first electric capacity c1 are sequentially connected in series respectively between the outfan and earth terminal gnd of described subtraction circuit；
Described tenth transistor m10 and described 13rd transistor m13, described 14th transistor m14 and described 15th transistor
M15, described second resistance r2 and described second electric capacity c2 are sequentially connected in series respectively in reference voltage source vdthAnd earth terminal gnd between；
Described 11st transistor m11 is serially connected with the outfan of described subtraction circuit and described reference voltage source vdthBetween；Described tenth
Seven transistor m17 are serially connected with the node i that described second resistance r2 and described second electric capacity c2 concatenation are formed and described outfan
Between vout；Described 3rd resistor r3 is serially connected between described outfan vout and earth terminal gnd；Described 18th transistor
M18 is serially connected with the node h that described 16th transistor m16 and described first electric capacity c1 concatenation are formed and described outfan vout
Between；Described 19th transistor m19 is serially connected with described reference voltage source vdthAnd described outfan vout between；Described 9th
The control end of transistor m9 and described tenth transistor m10 is electrically connected to described 9th transistor m9 and described 12nd crystal
The node e place that pipe m12 concatenation is formed, the control end of described 11st transistor m11 be electrically connected to described tenth transistor m10 and
At the node f that described 13rd transistor m13 concatenation is formed, described tenth two-transistor m12 and described 13rd transistor m13
Control end be electrically connected to the outfan of described subtraction circuit, described 14 transistor m14 and described 15th transistor m15
Control end be electrically connected to described tenth transistor m10 concatenate with described 13rd transistor m13 formed node f at, institute
The control end stating 16 transistor m16 and described 17th transistor m17 is electrically connected to described 14th transistor m14 and institute
State at the node g that the 15th transistor m15 concatenation is formed, the control end of described 18th transistor m18 is electrically connected to described the
Ten transistor m10 concatenate at the node f being formed with described 13rd transistor m13, the control end of described 19th transistor m19
Be electrically connected to described 5th transistor m5 concatenate with described 6th transistor m6 formed node c sentence input described second control
Signal vob.
The embodiment of the present invention, using ultralow pressure comparator circuit, is capable of 4 kinds of duty ratio modulation amplitudes, effectively improves
The conversion efficiency of mppt circuit is it is ensured that circuit is operated in maximum power point, thus maximizing the utilization rate of input energy.
Embodiment two
Refer to Fig. 7, Fig. 7 is that a kind of circuit structure of ultralow pressure comparator circuit provided in an embodiment of the present invention is illustrated
Figure.The present embodiment, on the basis of above-described embodiment, is described in detail to the ultralow pressure comparator circuit of the present invention as follows:
The ultralow pressure comparator circuit of the present invention includes: first comparator, subtraction circuit, the second comparator, wherein, described
First comparator circuit is to by in-phase input end vpWith inverting input vnThe homophase of input and inversion signal are compared, and obtain
Two control signals v anti-phase each otheroaAnd vob, this two control signals are by controlling the first multi-way switch circuit and more than second
Path switching circuit, the power supply voltage signal (being provided by outfan vout) needed for subtraction circuit offer work and earth signal (by
Earth terminal gnd provides), work as voaFor high level, and vobDuring for low level, (v realized by subtraction circuitp-vn) function, conversely, work as
voaFor low level, and vobDuring for high level, (v realized by subtraction circuitn-vp) function；The output v of subtraction circuitocBy second
Comparator and reference voltage (being provided by reference voltage source) vdthIt is compared, work as voc>vdthWhen, pmos transistor m18 turns on, will
It is stored in the energy (v on electric capacity c1p-vn) or (vn-vp) it is delivered to outfan vout, work as vdth>vocWhen, pmos transistor m17
Conducting, will be stored in the energy v on electric capacity c2dthIt is delivered to outfan vout.Meanwhile, described ultralow pressure comparator circuit is permissible
According to the size of input in-phase signal and inversion signal, control the turn-on and turn-off of pmos transistor m19, thus control flowing through electricity
The size of current of resistance r3, i.e. the magnitude of voltage of control output end vout.The energy being discharged in conjunction with electric capacity c1 or c2, outfan vout
4 kinds of different duty cycle modulated signal finally can be provided, the different duty ratio modulation of different outfan vout level representative
Amplitude, and the output valve of subtraction circuit characterizes different duty ratio modulation directions.
Specifically, described first comparator includes pmos transistor m1 and m2, nmos transistor m3 and m4, wherein, pmos
Transistor m1 and m2 constitutes common gate Differential Input pair, and the homophase of described ultralow pressure comparator circuit and rp input signal are respectively
It is carried in the source of pmos transistor m2 and m1, therefore avoid the restriction of transistor threshold voltage it is adaptable to low pressure applications
Situation；Nmos transistor m3 and m4, as active load, is responsible for for double-width grinding being converted to Single-end output；First comparator adopts
Self-powered structure, required working power voltage comes from the in-phase input end v of first comparatorp, and power supply that need not be extra,
Save power consumption, simplify circuit structure.Common gate Differential Input is to structure, it is to avoid the restriction of threshold voltage, reduces ratio
Compared with the requirement to supply voltage for the device circuit it is adaptable to low-voltage low-power design.
Referring again to Fig. 5, the output signal of first comparator is the first control signal voaIt is used for controlling the first multichannel to open
Pass and the turn-on and turn-off of the second variable connector.Output signal v of first comparatoroaVia pmos transistor m5 and nmos crystal
The inverter that pipe m6 is constituted, obtaining its inverted control signal is the second control signal vob, this two control signals use respectively
To control the first multi-way switch circuit and the second multi-way switch circuit.As (vp>vn) when, voaFor high level, vobFor low level, this
When, m20 the and m21 conducting in the first variable connector, and m22 and m23 disconnects, and input is that outfan vout is electrically connected to the
The outfan of one variable connector, i.e. the drain terminal of nmos transistor m7；Meanwhile, m22 the and m23 conducting in the second variable connector, m20
Disconnect with m21, input is the outfan that earth terminal gnd is electrically connected to the second variable connector, i.e. the public affairs of nmos transistor m8
The source at end altogether；Nmos transistor m7 and m8 constitutes subtraction circuit, and the input of subtraction circuit is described ultralow pressure comparator
In-phase input end vpInput signal and inverting input vnInput signal, now, the output signal of subtractor is the 3rd control
Signal vocFor (vp-vn).
Specifically, as (vp>vn) when, under low supply voltage environment, nmos transistor m7, m8 are operated in saturation region, now
There is ids,7=ids,8, wherein, ids,iFor the drain-source current of nmos transistor mi, then,
Wherein, vgs7/8Gate source voltage for m7/m8, vthFor threshold voltage, μnFor electron mobility, coxFor unit area
Gate oxide capacitance,Breadth length ratio for nmos transistor mi.And because:
vgs7=vp-voc-vth(2)
vgs8=vn-vth(3)
Therefore,
voc=vp-vn(4)
Can derive in the same manner, as (vn>vp) when, voc=(vn-vp).
Require to meet low-voltage low-power design, improve the stability of circuit, in the substrate of nmos transistor m7 and m8
End increased Substrate bias voltage vdth.Now, the lining-source voltage in nmos transistor m7 or m8 is represented by:
vbs=vdth-vs(5)
Wherein vsSource voltage terminal for nmos transistor m7 or m8.Again because the threshold voltage v of nmos transistorthFor:
Wherein, vth0It is nmos transistor in vbsThreshold voltage when=0, φfIt is surface potential, about 0.3v, γsubIt is body
Effector, representative value is about 0.51/2.From formula (6), the v of increasebsValue can reduce the threshold voltage of nmos transistor,
Thus ensure nmos transistor under the conditions of ultralow pressure steady operation in saturation region.
Output signal v of subtraction circuitocIt is electrically connected to the in-phase input end of the second comparator, with reference voltage vdthCarry out
Relatively.Pmos transistor m9 and m10 constitute common gate Differential Input pair, nmos transistor m12 and m13 as active load,
Pmos transistor m11 accelerates the upset of comparator.Work as voc>vdthWhen, voltage signal vodFor low level, through m14 and m15 structure
After the inverter becoming, voeFor high level, pmos switching tube m16 and m17 disconnection, m18 turns on, and the electric charge being stored on c1 leads to
Cross m18 and be discharged into outfan vout, its voltage is ids,18·r3, wherein, ids,18Drain-source current for pmos transistor m18；When
voc<vdthWhen, vodFor high level, voeFor low level, switching tube m16 and m17 conducting, m18 disconnects, and the electric charge being stored on c2 leads to
Cross m17 and be discharged into outfan vout, its voltage is ids,17·r3.In addition, working as vp>vnWhen, vobFor low level, pmos transistor
M19 turns on, from input vdthThere is provided extra electric current to increase outfan vout, its voltage is ids,19·r3；Otherwise, m19 breaks
Open, the output voltage of outfan vout is only determined by the storage electric charge on c1 or c2.
Can analyze in the same manner, as (vn>vp) when, voc=(vn-vp), if voc>vdth, the electric charge being stored on c1 passes through
M18 is discharged into outfan vout, and otherwise, the electric charge being stored on c2 is discharged into outfan vout by m17.Now, due to vn>
vp, pmos transistor m19 disconnects all the time.
As table 1 below, summarize four kinds of output voltages that described ultralow pressure comparator can be provided by.
The output voltage of table 1 ultralow pressure comparator
In the embodiment of the present invention, described first comparator circuit, supply voltage that need not be extra, its running voltage is by first
The in-phase input end v of comparatorpThere is provided, save power consumption；Common gate Differential Input is to structure, it is to avoid the limit of threshold voltage
System, reduces the requirement to supply voltage for the comparator circuit it is adaptable to low-voltage low-power design.In subtraction circuit, variable connector
Different current potentials can be passed to core subtrator by circuit, produce different subtractions.Second comparator being capable of basis
Input signal provides 4 kinds of different output voltages, corresponding 4 kinds of duty ratio modulation amplitudes, effectively improves the conversion effect of mppt circuit
Rate is it is ensured that circuit is operated in maximum power point, thus maximizing the utilization rate of input energy.
Above content is to further describe it is impossible to assert with reference to specific preferred implementation is made for the present invention
Being embodied as of the present invention is confined to these explanations.For general technical staff of the technical field of the invention,
On the premise of present inventive concept, some simple deduction or replace can also be made, all should be considered as belonging to the present invention's
Protection domain.
Claims (10)
1. a kind of ultralow pressure comparator circuit for mppt circuit is it is characterised in that include:
In-phase input end (vp)；
Inverting input (vn)；
Outfan (vout)；
First comparator, is electrically connected to described in-phase input end (vp) and described inverting input (vn), for defeated to described homophase
Enter end (vp) and described inverting input (vn) signal that inputs is compared to obtain the first control signal (v of subtractoroa)；
Described subtractor, electrically connects described in-phase input end (vp) and described inverting input (vn) state in-phase input end to receive
(vp) and described inverting input (vn) signal that inputs, as two input signals of described subtractor, electrically connects described first
The outfan of comparator is to obtain described first control signal (voa), electrically connect described outfan (vout) to obtain supply voltage
Signal, electrical connection the second comparator is to export the second control signal (vob) and the 3rd control signal (voc)；
Described second comparator, electrically connects described outfan (vout), according to described second control signal (vob) and the described 3rd
Control signal (voc) output four kinds of different duty modulated signal.
2. circuit according to claim 1 it is characterised in that described first comparator include the first transistor (m1),
Two-transistor (m2), third transistor (m3), the 4th transistor (m4)；Wherein,
Described the first transistor (m1) and described third transistor (m3) are sequentially connected in series in described inverting input (vn) and earth terminal
(gnd) between；
Described transistor seconds (m2) and described 4th transistor (m4) are sequentially connected in series in described in-phase input end (vp) and earth terminal
(gnd) between；
The control end of described the first transistor (m1) and described transistor seconds (m2) is electrically connected to described the first transistor
(m1) concatenate node (a) place, described third transistor (m3) and described 4th crystal being formed with described third transistor (m3)
The control end of pipe (m4) is electrically connected to described in-phase input end (vp)；
Described transistor seconds (m2) concatenates the node (b) being formed as described first comparator with described 4th transistor (m4)
Outfan to export described first control signal (voa).
3. circuit according to claim 2 is it is characterised in that described the first transistor (m1) and described transistor seconds
(m2) it is grid, described third transistor (m3) and described 4th crystal that pmos transistor and its control end are pmos transistor
For nmos transistor and its control end is the grid of nmos transistor to pipe (m4).
4. circuit according to claim 1 it is characterised in that described subtraction circuit include the 5th transistor (m5), the 6th
Transistor (m6), the 7th transistor (m7), the 8th transistor (m8), the first variable connector and the second variable connector；Wherein,
Described 5th transistor (m5) and described 6th transistor (m6) are sequentially connected in series in described outfan (vout) and earth terminal
(gnd) between, and its control end is electrically connected to the outfan of described first comparator；
Described 7th transistor (m7) and described 8th transistor (m8) are sequentially connected in series in described first variable connector and described the
Between two variable connectors, and its control end is respectively electrically connected to described in-phase input end (vp) and described inverting input (vn), its
Substrate terminal is electrically connected to reference voltage source (vdth)；
Two inputs of described first variable connector are respectively electrically connected to described outfan (vout) and earth terminal (gnd), its
Outfan is electrically connected to described 7th transistor (m7) and its first control end (s1) is electrically connected to the defeated of described first comparator
Go out end, the second control end (s2) is electrically connected to described 5th transistor (m5) and is concatenated the section being formed with described 6th transistor (m6)
Point (c) place；
Two inputs of described second variable connector are respectively electrically connected to described outfan (vout) and earth terminal (gnd), its
Outfan is electrically connected to described 8th transistor (m8) and its first control end (s1) is electrically connected to described 5th transistor (m5)
Concatenate node (c) place being formed with described 6th transistor (m6), the second control end (s2) is electrically connected to described first comparator
Outfan；
Described 5th transistor (m5) is concatenated the node (c) being formed and exports described second control letter with described 6th transistor (m6)
Number (vob), described 7th transistor (m7) concatenates the node (d) being formed as described subtractor with described 8th transistor (m8)
Outfan to export described 3rd control signal (voc).
5. circuit according to claim 4 is it is characterised in that described 5th transistor (m5) is pmos transistor and its control
End processed is the grid of pmos transistor, described 6th transistor (m6), described 7th transistor (m7) and described 8th transistor
(m8) it is the grid that nmos transistor and its control end are nmos transistor.
6. circuit according to claim 4 is it is characterised in that described first variable connector or described second variable connector bag
Include the 20th transistor (m20), the 21st transistor (m21), the 20th two-transistor (m22) and the 23rd transistor
(m23)；Wherein,
Described 20th transistor (m20) is electrically connected to described outfan (vout) and described first variable connector or described second
Outfan (the v of variable connectoros) between and its control end is electrically connected to described first variable connector or described second variable connector
The first control end (s1)；
Described 21st transistor (m21) is electrically connected to described outfan (vout) and described first variable connector or described the
Outfan (the v of two variable connectorsos) between and its control end is electrically connected to described first variable connector or described second multichannel is opened
The second control end (s2) closed；
Described 20th two-transistor (m22) is electrically connected to earth terminal (gnd) and described first variable connector or described more than second
Outfan (the v of way switchos) between and its control end is electrically connected to described first variable connector or described second variable connector
Second control end (s2)；
Described 23rd transistor (m23) is electrically connected to earth terminal (gnd) and described first variable connector or described more than second
Outfan (the v of way switchos) between and its control end is electrically connected to described first variable connector or described second variable connector
First control end (s1).
7. circuit according to claim 6 is it is characterised in that described 21st transistor (m21) and the described 20th
Three transistors (m23) are the grid that pmos transistor and its control end are pmos transistor, described 20th transistor (m20) and
For nmos transistor and its control end is the grid of nmos transistor to described 20th two-transistor (m22).
8. circuit according to claim 1 it is characterised in that described second comparator include the 9th transistor (m9),
Ten transistors (m10), the 11st transistor (m11), the tenth two-transistor (m12), the 13rd transistor (m13), the 14th crystalline substance
Body pipe (m14), the 15th transistor (m15), the 16th transistor (m16), the 17th transistor (m17), the 18th transistor
(m18), the 19th transistor (m19), first resistor (r1), second resistance (r2), 3rd resistor (r3), the first electric capacity (c1) and
Second electric capacity (c2)；Wherein,
Described 9th transistor (m9) and described tenth two-transistor (m12), described first resistor (r1), described 16th crystal
Pipe (m16) and described first electric capacity (c1) are sequentially connected in series respectively between the outfan and earth terminal (gnd) of described subtraction circuit；
Described tenth transistor (m10) and described 13rd transistor (m13), described 14th transistor (m14) and described
15 transistors (m15), described second resistance (r2) and described second electric capacity (c2) are sequentially connected in series respectively in reference voltage source
(vdth) and earth terminal (gnd) between；
Described 11st transistor (m11) is serially connected with the outfan of described subtraction circuit and described reference voltage source (vdth) between；
Described 17th transistor (m17) is serially connected with the section that described second resistance (r2) and described second electric capacity (c2) concatenation are formed
Between point (i) place and described outfan (vout)；Described 3rd resistor (r3) is serially connected with described outfan (vout) and earth terminal
(gnd) between；
Described 18th transistor (m18) is serially connected with described 16th transistor (m16) and described first electric capacity (c1) concatenation shape
Between node (h) place becoming and described outfan (vout)；
Described 19th transistor (m19) is serially connected with described reference voltage source (vdth) and described outfan (vout) between；
The control end of described 9th transistor (m9) and described tenth transistor (m10) is electrically connected to described 9th transistor
(m9) node (e) place being formed, the control end of described 11st transistor (m11) are concatenated with described tenth two-transistor (m12)
It is electrically connected to described tenth transistor (m10) and concatenate node (f) place being formed with described 13rd transistor (m13), described the
The control end of ten two-transistors (m12) and described 13rd transistor (m13) is electrically connected to the outfan of described subtraction circuit,
The control end of described 14 transistors (m14) and described 15th transistor (m15) is electrically connected to described tenth transistor
(m10) node (f) place being formed, described 16 transistors (m16) and the described tenth are concatenated with described 13rd transistor (m13)
The control end of seven transistors (m17) is electrically connected to described 14th transistor (m14) and described 15th transistor (m15) string
Meet node (g) place of formation, the control end of described 18th transistor (m18) be electrically connected to described tenth transistor (m10) with
Node (f) place that described 13rd transistor (m13) concatenation is formed, the control end electrical connection of described 19th transistor (m19)
Concatenate, to described 5th transistor (m5), the node (c) being formed with described 6th transistor (m6) and sentence described second control of input
Signal (vob).
9. circuit according to claim 8 it is characterised in that described 9th transistor (m9), the tenth transistor (m10),
11st transistor (m11), the 14th transistor (m14), the 16th transistor (m16), the 17th transistor (m17), the tenth
For pmos transistor and its control end is the grid of pmos transistor for eight transistors (m18) and the 19th transistor (m19), described
Tenth two-transistor (m12), described 13rd transistor (m13) and described 15th transistor (m15) be nmos transistor and
Its control end is the grid of nmos transistor.
10. a kind of mppt circuit, comprising: multiplier circuit, time-delay unit circuit, comparator circuit, pwm comparator circuit and shake
Swing device circuit it is characterised in that described comparator circuit is the ultralow pressure comparator electricity as described in any one of claim 1-9
Road.
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| JP2005251039A (en) * | 2004-03-05 | 2005-09-15 | Japan Science & Technology Agency | Maximum power control method for solar battery and its controller |
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| WO2015020843A1 (en) * | 2013-08-05 | 2015-02-12 | Brass Roots Technologies, LLC | Independent color stretch in color-sequential displays |
| CN104423414A (en) * | 2013-09-04 | 2015-03-18 | 艾默生网络能源***北美公司 | Control method, control device, control circuit and power generating system |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005251039A (en) * | 2004-03-05 | 2005-09-15 | Japan Science & Technology Agency | Maximum power control method for solar battery and its controller |
| CN101741275A (en) * | 2010-01-15 | 2010-06-16 | 南京航空航天大学 | Control method of modular full-bridge grid-connected inverters capable of parallel operation |
| CN102331808A (en) * | 2011-07-19 | 2012-01-25 | 天津光电惠高电子有限公司 | Solar maximum power point tracking system and method for implementing same |
| WO2015020843A1 (en) * | 2013-08-05 | 2015-02-12 | Brass Roots Technologies, LLC | Independent color stretch in color-sequential displays |
| CN104423414A (en) * | 2013-09-04 | 2015-03-18 | 艾默生网络能源***北美公司 | Control method, control device, control circuit and power generating system |
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