CN106357268A - Time delay correction circuit and method for comparator in ADC (analog to digital converter) and ADC - Google Patents
Time delay correction circuit and method for comparator in ADC (analog to digital converter) and ADC Download PDFInfo
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- CN106357268A CN106357268A CN201610871262.4A CN201610871262A CN106357268A CN 106357268 A CN106357268 A CN 106357268A CN 201610871262 A CN201610871262 A CN 201610871262A CN 106357268 A CN106357268 A CN 106357268A
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- 238000006243 chemical reaction Methods 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 8
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/462—Details of the control circuitry, e.g. of the successive approximation register
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Abstract
According to the delay correction circuit of the comparator in the ADC, a logic circuit connected with a latch is arranged in a data register, and the logic circuit controls the latch to output a preset level signal within the initial preset time length of the current ADC clock period; after a preset duration, the output of the latch depends on the comparator output. Therefore, the latch of the corresponding bit can be enabled to forcibly output the level signal which is the same as the input signal at the initial stage of each ADC clock cycle, namely, the latch of the corresponding bit is ensured to output the assumed preset level signal without being influenced by the output delay of the comparator of the previous clock cycle, namely, the next bit conversion of the ADC is not influenced by the output delay of the comparison result of the previous bit, thereby ensuring the normal work of the ADC.
Description
Technical field
The application is related to analog-digital converter technical field, more particularly to a kind of adc (analog-to-
Digital converter, A-D converter) comparator delay correction circuit, method and adc.
Background technology
Adc extensively applies in fields such as Industry Control, medical apparatus and instruments and microprocessor submodule translation interfaces, for inciting somebody to action
Analogue signal is converted to digital signal.
Comparator is the important module in adc, the transmission delay of comparator be determine whole adc conversion speed important
One of factor.
For example, sar (successive approximation register) type adc is to be compared by turn, i.e. each clock cycle can only compare one
Secondary, n position then needs to compare n time.When the voltage infinite approach of two inputs of comparator, comparator output time delay is more than one
Clock cycle, it will lead to adc the output of correct comparator cannot be detected, and then lead to the adc cannot normal work.
Refer to Fig. 1, be a kind of circuit structure schematic diagram of prior art sar adc, pa is the anti-phase input of comparator
End, the output of input dac (digital-to-analog converter, digital-to-analog converter)；Pb is the homophase input of comparator
End, inputs analogue signal to be converted；Sar adc gradually comparand register highest will put 1 first, and instruction dac output is corresponding
Voltage signal, to the inverting input of comparator, is carried out with the analog voltage signal vi to be converted of comparator in-phase input end input
Relatively, if vi is more than the voltage signal of dac output, comparator is output as binary number " 1 ", conversely, comparator output two
System number " 0 ".Compare to the last one successively, now, final latch data simultaneously exports, the data of final output is that vi corresponds to
Digital signal.
Refer to Fig. 2, show the oscillogram of each key point in circuit shown in Fig. 1, adc_clk is the clock week of adc
Phase, only compare once in each clock cycle；Pa is the oscillogram of the inverting input of comparator；Pb is that the homophase of comparator is defeated
Enter the oscillogram at end；Comp is the oscillogram of the outfan of comparator；Cap_pulse is the control clock signal of trigger d1；
Latch_pulse is the control clock signal of latch d2, when rising edge in latch_pulse pulse, triggers latch
Latch the data of the q0 output of d1；As shown in Fig. 2 comp=1 in the upper clock cycle, in this clock cycle, the voltage at pa end
Slightly larger than the voltage at pb end, and the voltage of pa and pb is closely, and in this case, the output of comparator should be comp=
0, but, comparator compares pa end and the size of pb terminal voltage took long enough more than a clock cycle；Now, d1 triggering
Device detect comparator output actual when a upper clock cycle output comp=1, when latch_pulse pulse appearance rising
Along when, d1 trigger by the data input of a upper clock cycle in latch d2, lead to latch d2 latch error in data,
And then lead to the adc cannot normal work.
Content of the invention
In view of this, the application provides comparator delay correction circuit, method and adc in a kind of adc, is compared with solving to work as
During the voltage infinite approach of two inputs input of device, analog digital conversion converting machine cannot normal work technical problem, this
The application following technical scheme of offer:
In a first aspect, the present invention provides comparator delay correction circuit in a kind of analog-digital converter adc, described adc includes
Digital to analog converter dac, comparator data depositor, described data register includes multistage latch；The first of described dac is defeated
Enter the outfan that end connects described data register, the second input input reference voltage signal, outfan connects described comparison
The inverting input of device, the in-phase input end of described comparator inputs voltage signal to be converted, comparator time delay school in described adc
Positive circuit includes: logic circuit and clock generation circuit, and wherein, every grade of described latch connects a described logic circuit；
The outfan of the first input end described comparator of connection of each described logic circuit, the second of described logic circuit
Input connects the first outfan of described clock generation circuit, and the outfan described logic circuit of connection of described logic circuit is same
The control end of the described latch of one-level；The input input predetermined level signal of described latch, the clock of described latch
Control end connects the second outfan of described clock generation circuit；
Described logic circuit, for controlling described latch to export in initial preset duration of current adc clock cycle
Predetermined level signal, and after described preset duration, control the output of comparator described in described latches；
The input input adc clock cycle signal of described clock generation circuit, during described first outfan output first
Clock signal, described second outfan output second clock signal.
Alternatively, described predetermined level signal is high level signal.
Alternatively, described latch is d trigger；
The input of described d trigger is the input of described latch, for inputting described predetermined level signal；Described
The outfan of d trigger is the outfan of described latch, and the Clock control end of described d trigger is the clock of described latch
Control end, the reset terminal of described d trigger is the control end of described latch.
Alternatively, described logic circuit includes NOR logic circuit；
The first input end of described NOR logic circuit is the first input end of described logic circuit, described NOR-logic electricity
Second input on road is the second input of described logic circuit, and the outfan of described NOR logic circuit is described logic electricity
The outfan on road.
Alternatively, described clock generation circuit includes pulse-generating circuit, and be connected with described pulse-generating circuit
Delay circuit；
The input of described pulse-generating circuit is the input of described clock generation circuit, described pulse-generating circuit
Outfan is the first outfan of described clock generation circuit, and the outfan of described delay circuit is described clock generation circuit
Second outfan；
Described pulse-generating circuit, for producing the pulse signal of one fixed width according to described adc clock cycle signal；
Described delay circuit, for the pulse delay signal Preset Time output exporting described pulse-generating circuit.
Second aspect, the present invention provides a kind of analog-digital converter adc, comprising: digital to analog converter dac, comparator, data are posted
Storage and logic circuit, described data register includes multistage latch, and every grade of described latch connects a described logic electricity
Road；
The first input end of described dac connects the outfan of described data register, the second input input reference voltage
Signal, outfan connects the inverting input of described comparator；The in-phase input end input voltage to be converted letter of described comparator
Number；
The outfan of the first input end described comparator of connection of each described logic circuit, the second of described logic circuit
Input connects the first outfan of described clock generation circuit, and the outfan described logic circuit of connection of described logic circuit is same
The control end of the described latch of one-level；The input input predetermined level signal of described latch, the clock of described latch
Control end connects the second outfan of described clock generation circuit；
Described logic circuit, for controlling described latch to export in initial preset duration of current adc clock cycle
Predetermined level signal, and after described preset duration, control the output of comparator described in described latches；
The input input adc clock cycle signal of described clock generation circuit, during described first outfan output first
Clock signal, described second outfan output second clock signal.
The third aspect, the present invention provides comparator time delay correction method in a kind of analog-digital converter adc, is applied in adc,
Described adc includes digital to analog converter dac, comparator, data register and logic circuit, and described data register includes multistage lock
Storage, every grade of described depositor corresponds to a described logic circuit；Methods described includes:
In initial preset duration within the current adc clock cycle, described logic circuit produces the first level signal, and will
Described first level signal is supplied to the latch being in same one-level in described data register with described logic circuit, so that institute
State latch and export predetermined level signal in described preset duration；
After initial preset duration of current adc clock cycle, described logic circuit is according to the output of described comparator
Signal output second electrical level signal, and described second electrical level signal is supplied to described latch, so that described latch is in institute
The output signal of described comparator is latched after stating preset duration.
Alternatively, described predetermined level signal is high level signal.
Alternatively, in described initial preset duration within the current adc clock cycle, described logic circuit produces the first electricity
Ordinary mail number, comprising:
In initial preset duration of current adc clock cycle, the height that described logic circuit inputs according to first input end
Level signal exports low level signal；
After the described preset duration initial in the current adc clock cycle, described logic circuit is according to described comparator
Output signal exports second electrical level signal, comprising:
After initial preset duration of current adc clock cycle, when described comparator output high level signal, described
Logic circuit exports low level signal；
After initial preset duration of current adc clock cycle, when described comparator output low level signal, described
Logic circuit exports high level signal.
Alternatively, the output signal of described logic circuit inputs to the reset terminal of described latch, and methods described also includes:
After initial preset duration of current adc clock cycle, when described logic circuit output high level signal, control
Make described latch output low level signal；When described logic circuit output low level signal, control described latch output
High level signal.
Understand via above-mentioned technical scheme, compared with prior art, comparator time delay correction in the adc that the application provides
Circuit, arranges the logic circuit being connected with latch in data register, and logic circuit is initial in the current adc clock cycle
In preset duration, control latch output predetermined level signal；After preset duration, the output of latch depends on comparator
Output.So, the starting stage in each adc clock cycle can make the latch of corresponding positions force output and input signal phase
Same level signal, i.e. ensure that the latch of corresponding positions is output as the predetermined level signal of hypothesis and is not subject to a clock cycle
Comparator export time delay impact, that is, adc next bit conversion by upper one bit comparison result output time delay do not affected,
Thus ensureing adc normal work.
Brief description
In order to be illustrated more clearly that the embodiment of the present application or technical scheme of the prior art, below will be to embodiment or existing
Have technology description in required use accompanying drawing be briefly described it should be apparent that, drawings in the following description be only this
The embodiment of application, for those of ordinary skill in the art, on the premise of not paying creative work, can also basis
The accompanying drawing providing obtains other accompanying drawings.
Fig. 1 shows a kind of circuit structure schematic diagram of existing sar adc；
Fig. 2 illustrates the oscillogram of each key point of circuit shown in Fig. 1；
Fig. 3 shows the schematic diagram of the comparator delay correction circuit in a kind of adc of the embodiment of the present application；
Fig. 4 shows a kind of specific adc circuit theory schematic diagram of the embodiment of the present invention；
Fig. 5 shows the corresponding waveform diagram of each key point of circuit shown in Fig. 4；
The flow chart that Fig. 6 shows comparator time delay correction method in a kind of adc of the embodiment of the present invention.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present application, the technical scheme in the embodiment of the present application is carried out clear, complete
Site preparation describes it is clear that described embodiment is only some embodiments of the present application, rather than whole embodiments.It is based on
Embodiment in the application, it is every other that those of ordinary skill in the art are obtained under the premise of not making creative work
Embodiment, broadly falls into the scope of the application protection.
Refer to Fig. 3, show the schematic diagram of the comparator delay correction circuit in a kind of adc of the embodiment of the present application, should
Circuit is applied in sar adc, as shown in figure 3, this circuit includes digital analog converter (dac) 100, comparator 200, data
Depositor 300 and clock generation circuit 400, each data register 300 includes multi-level register, and every grade of depositor all includes patrolling
Collect circuit 310 and latch 320.
Data register 300, latches the output knot of comparator for being produced as the binary data of dac input, meanwhile
Really；The flip flop number comprising in data register 300 is identical with the digit of adc.
Dac100, for the reference voltage v according to inputref, and the binary data of input, output is corresponding to simulate
Voltage signal simultaneously inputs to the inverting input of comparator 200.
The in-phase input end of comparator 200 inputs voltage signal to be converted, and the voltage signal with inverting input input
It is compared, obtain comparative result, the corresponding positions of data register 300 in comparative result latch.
Following is a brief introduction of the operation principle of adc:
First, it is assumed that highest order is binary one in data register 300, other positions are binary number " 0 ", and should
Binary data is supplied to dac, so that dac exports corresponding analog voltage signal according to reference voltage.
For example, for 8 adc, assume that the highest order of data register 300 is " 1 " for the first time, then this latch
In data be " 1,000 0000 " be supplied to dac100, if the reference voltage of dac100 input is vref, then dac100 is defeated
The analog voltage going out is vref/2.
The voltage signal of dac100 output transmits to the inverting input of comparator 200, comparator 200 relatively electricity to be converted
Pressure signal and the voltage signal of inverting input input, if voltage signal to be converted is more than the voltage signal of dac output, compare
It is output as high level compared with device 200, and this high level is latched into the highest order of data register 300, i.e. data register is
High-order is finally " 1 "；Whereas if voltage signal to be converted be less than dac output voltage signal, then comparator 200 export low
Level, and this low level signal is latched into the highest order of data register 300, i.e. the highest order of data register 300 is final
For " 0 ".
Then it is assumed that a time high position for data register 300 is " 1 ", repeat the process that above-mentioned highest order is " 1 ", finally
Obtain time actual value of a high position.Repeat above-mentioned process by turn, the data in final data depositor is voltage pair to be converted
The digital signal answered.
The present invention is that data register is improved, and when gradually comparing, when gradually comparing a certain position, this position is posted
Storage is output as " 1 " in the preset duration of adc clock cycle, i.e. total energy ensures the input starting stage of next bit register
Inside remain " 1 ", and be not subject to the comparative result delay of.
As shown in figure 3, every grade of depositor of data register 300 all includes a latch 320 and a logic circuit
310.
The outfan of comparator 200 connects the first input end of logic circuit 310, the second input of logic circuit 310
Input the first clock signal, the outfan of logic circuit 310 connects the control end of latch 320.The input of latch 320 is defeated
Enter predetermined level signal, Clock control end inputs second clock signal.Latch 320 is used for providing preset number letter for dac100
Number, then, the output result of latched comparator.
Clock generation circuit 400 input inputs adc clock cycle signal, and the first outfan exports the first clock signal,
Second outfan output second clock signal.
The corresponding logic circuit of present bit 310 exports corresponding level letter in adc clock cycle initial preset duration
Number it is supplied to latch 320, so that latch 320 is output as predetermined level signal in preset duration；And, in preset duration
Afterwards, the output of latch 400 depends on the output of described comparator 200.
In a kind of possible implementation of the present invention, predetermined level signal is high level signal, i.e. latch 320
Input input high level signal, makes the adc clock cycle after controlling clock to arrive for the latch 320 by logic circuit 300
Output high level signal in initial preset duration.After preset duration, the output of latch 320 depends on comparator 200
Output, if comparator 200 is output as high level signal, latch 320 exports high level signal；If comparator 200 is defeated
Go out for low level signal, then latch 320 output low level signal.
Comparator delay correction circuit in the adc that the present embodiment provides, is arranged in data register and is connected with latch
Logic circuit, logic circuit makes to export in adc clock cycle initial preset duration after controlling clock to arrive for the latch
Input identical level signal with latch；After preset duration, the output of latch depends on comparator and exports.So,
The latch that corresponding positions can be made in the starting stage of each adc clock cycle forces output and input signal identical level letter
Number, i.e. ensure that the comparator that the latch of corresponding positions is output as the predetermined level signal assumed and is not subject to a clock cycle is defeated
Go out the impact of time delay, that is, the next bit conversion of adc is not affected by a upper bit comparison result output time delay, thus ensureing adc
Normal work.
Refer to Fig. 4, show a kind of specific adc circuit theory schematic diagram of the embodiment of the present invention, in the present embodiment, patrol
Collecting circuit can make latch force to export high level signal in adc starting stage clock cycle.
As shown in figure 4, logic circuit is NOR logic circuit, latch is d trigger.
The outfan of dac connects the inverting input pa of comparator c, and the in-phase input end pb input of comparator c is to be converted
Voltage signal, the outfan of comparator c connects an input of NOR logic circuit.
Another input input of NOR logic circuit has the first clock signal, and the outfan of NOR logic circuit connects
The reset terminal clr of d trigger.This first clock signal is the pulse in the initial preset duration of adc clock cycle for high level
Signal.
The input input high level signal vdd of d trigger, outfan q are the output of a certain position of adc；D trigger when
Clock control end inputs second clock signal.
Preferably, clock generation circuit includes pulse-generating circuit 410 and delay circuit 420, pulse-generating circuit 410
Input input has adc clock cycle signal, and the outfan of pulse-generating circuit 410 connects the input of delay circuit 420, with
When, the outfan of pulse-generating circuit 410 exports the first clock signal；The outfan output second clock letter of delay circuit 420
Number.That is, second clock signal than the first clock signal delayed a period of time.
Refer to Fig. 5, show the corresponding waveform diagram of each key point of circuit shown in Fig. 4, this Figure only shows one
Each signal waveform of individual adc clock cycle.
Adc_clk is the clock cycle of adc, only compares once in each clock cycle；Pa is the anti-phase input of comparator c
The oscillogram at end；Pb is the oscillogram of the in-phase input end of comparator c；Comp is the oscillogram of the outfan of comparator c；cap_
Pulse is the control clock signal of d trigger, and cap_pulse0 is the first clock signal of NOR logic circuit input；
In conjunction with Fig. 4 and Fig. 5, between adc_clk is for high period, t0-t2 time period cap_pulse0 is high level, even
One input of logical not component is " 1 ", and now, no matter comp is high level or low level, and NOR logic circuit exports
It is always low level；Now, the clr of d trigger inputs as low level, wherein, the clr end of d trigger be high level effectively (i.e.,
When clr end input high level, d trigger outfan is output as " 0 "), therefore, the outfan q of d trigger remains input
Level signal vdd, i.e. within the t0-t2 time period, regardless of the output of comparator, the output of d trigger is all vdd.
After instant t 2, cap_pulse0 is low level, and that is, NOR logic circuit a input is " 0 ", now,
The output of NOR logic circuit depends on another input (comp)；If comp is high level, NOR logic circuit is defeated
Go out for low level, clr end inputs as low level, d trigger outfan is identical with its input, is high level vdd；If comp
For low level, then NOR logic circuit is output as high level, the level of the clr end input of d trigger effectively, therefore, d trigger
It is output as " 0 ".It can be seen that after the t2 moment, the output of d trigger depends on the output comp of comparator, if comp is high electricity
Flat, then d trigger output high level；If comp is low level, d trigger exports low level, i.e. using d trigger lock
Deposit the output result of comparator.
Preferably, cap_pulse than cap_pulse0 delayed a period of time (that is, t1-t0), this lag time difference in order to
Ensure that the output signal of NOR logic circuit is transferred to d trigger.
Comparator delay correction circuit in the adc that the present embodiment provides, controls latch in adc clock using logic circuit
In cycle initial preset duration, output and latch input identical level signal；After preset duration, latch defeated
Go out depending on comparator output.So, the starting stage in each adc clock cycle can make the latch pressure of corresponding positions defeated
Go out and input signal identical level signal, i.e. ensure that the latch of corresponding positions is output as the predetermined level signal assumed, and not
Comparator output time delay by a upper clock cycle is affected, that is, the next bit conversion of adc is not subject to a bit comparison result defeated
Go out the impact of time delay, thus ensureing adc normal work.
Corresponding to comparator delay correction circuit embodiment in above-mentioned adc, present invention also offers comparator prolongs in adc
When bearing calibration embodiment.
Refer to Fig. 6, the flow chart showing comparator time delay correction method in a kind of adc of the embodiment of the present invention, the party
Method is applied in comparator delay correction circuit in above-mentioned adc, and described adc includes dac, comparator, data register and patrols
Collect circuit, described data register includes multistage latch, every grade of described depositor corresponds to a described logic circuit；Described side
Method includes:
S110, in initial preset duration within the current adc clock cycle, described logic circuit produces the first level letter
Number, and described first level signal is supplied to the latch being in same one-level in described data register with described logic circuit
Device, so that described latch exports predetermined level signal in described preset duration.
In a kind of possible implementation of the present invention, described predetermined level signal is high level signal.
In initial preset duration of current adc clock cycle, the height that described logic circuit inputs according to first input end
Level signal exports low level signal.
S120, after initial preset duration of current adc clock cycle, described logic circuit is according to described comparator
Output signal exports second electrical level signal, and described second electrical level signal is supplied to described latch, so that described latch
The output signal of described comparator is latched after described preset duration.
After initial preset duration of current adc clock cycle, when described comparator output high level signal, described
Logic circuit exports low level signal, and described latch exports high level signal；When described comparator output low level signal,
Described logic circuit exports high level signal, and described latch exports low level signal.
Comparator time delay correction method in the adc that the present embodiment provides, is arranged in data register and is connected with latch
Logic circuit, in initial preset duration of current adc clock cycle, logic circuit controls latch output predetermined level letter
Number；After preset duration, the output of latch depends on comparator and exports.So, in the initial rank of each adc clock cycle
Duan Douneng makes the latch of corresponding positions force output and input signal identical level signal, i.e. ensure the latch of corresponding positions
It is output as the predetermined level signal of hypothesis and do not affected by the comparator output time delay of a upper clock cycle, that is, under adc
One conversion is not affected by a upper bit comparison result output time delay, thus ensureing adc normal work.
For aforesaid each method embodiment, in order to be briefly described, therefore it is all expressed as a series of combination of actions, but
It is that those skilled in the art should know, the application is not limited by described sequence of movement, because according to the application, certain
A little steps can be carried out using other orders or simultaneously.Secondly, those skilled in the art also should know, is retouched in description
The embodiment stated belongs to preferred embodiment, necessary to involved action and module not necessarily the application.
In this specification, each embodiment is described by the way of going forward one by one, and what each embodiment stressed is and other
The difference of embodiment, between each embodiment identical similar portion mutually referring to.For device disclosed in embodiment
For, because it corresponds to the method disclosed in Example, so description is fairly simple, say referring to method part in place of correlation
Bright.
Last in addition it is also necessary to explanation, herein, such as first and second or the like relational terms be used merely to by
One entity or operation are made a distinction with another entity or operation, and not necessarily require or imply these entities or operation
Between there is any this actual relation or order.And, term " inclusion ", "comprising" or its any other variant meaning
Covering comprising of nonexcludability, so that including a series of process of key elements, method, article or equipment not only include that
A little key elements, but also include other key elements being not expressly set out, or also include for this process, method, article or
The intrinsic key element of equipment.In the absence of more restrictions, the key element being limited by sentence "including a ...", does not arrange
Remove and also there is other identical element in the process including described key element, method, article or equipment.
For convenience of description, it is divided into various units to be respectively described with function when describing apparatus above.Certainly, implementing this
The function of each unit can be realized in same or multiple softwares and/or hardware during application.
As seen through the above description of the embodiments, those skilled in the art can be understood that the application can
Mode by software plus necessary general hardware platform to be realized.Based on such understanding, the technical scheme essence of the application
On in other words prior art is contributed partly can be embodied in the form of software product, this computer software product
Can be stored in storage medium, such as rom/ram, magnetic disc, CD etc., include some instructions use so that a computer equipment
(can be personal computer, server, or network equipment etc.) executes some of each embodiment of the application or embodiment
Partly described method.
Described above to the disclosed embodiments, makes professional and technical personnel in the field be capable of or uses the application.
Multiple modifications to these embodiments will be apparent from for those skilled in the art, as defined herein
General Principle can be realized in the case of without departing from spirit herein or scope in other embodiments.Therefore, the application
It is not intended to be limited to the embodiments shown herein, and be to fit to and principles disclosed herein and features of novelty phase one
The scope the widest causing.
Claims (10)
1. comparator delay correction circuit in a kind of analog-digital converter adc, described adc include digital to analog converter dac, comparator and
Data register, described data register includes multistage latch；The first input end of described dac connects described data register
Outfan, the second input input reference voltage signal, outfan connect described comparator inverting input, described comparison
The in-phase input end of device inputs voltage signal to be converted it is characterised in that comparator delay correction circuit includes in described adc:
Logic circuit and clock generation circuit, wherein, every grade of described latch connects a described logic circuit；
The first input end of each described logic circuit connects the outfan of described comparator, the second input of described logic circuit
End connects the first outfan of described clock generation circuit, and the outfan of described logic circuit connects the same one-level of described logic circuit
Described latch control end；The input input predetermined level signal of described latch, the clock control of described latch
End connects the second outfan of described clock generation circuit；
Described logic circuit, for controlling the output in initial preset duration of current adc clock cycle of described latch default
Level signal, and after described preset duration, control the output of comparator described in described latches；
The input input adc clock cycle signal of described clock generation circuit, described first outfan output the first clock letter
Number, described second outfan output second clock signal.
2. circuit according to claim 1 is it is characterised in that described predetermined level signal is high level signal.
3. circuit according to claim 2 is it is characterised in that described latch is d trigger；
The input of described d trigger is the input of described latch, for inputting described predetermined level signal；Described d touches
The outfan sending out device is the outfan of described latch, and the Clock control end of described d trigger is the when clock of described latch
End processed, the reset terminal of described d trigger is the control end of described latch.
4. circuit according to claim 2 is it is characterised in that described logic circuit includes NOR logic circuit；
The first input end of described NOR logic circuit is the first input end of described logic circuit, described NOR logic circuit
Second input is the second input of described logic circuit, and the outfan of described NOR logic circuit is described logic circuit
Outfan.
5. circuit according to claim 2 is it is characterised in that described clock generation circuit includes pulse-generating circuit, with
And the delay circuit being connected with described pulse-generating circuit；
The input of described pulse-generating circuit is the input of described clock generation circuit, the output of described pulse-generating circuit
End is the first outfan of described clock generation circuit, and the outfan of described delay circuit is the second of described clock generation circuit
Outfan；
Described pulse-generating circuit, for producing the pulse signal of one fixed width according to described adc clock cycle signal；
Described delay circuit, for the pulse delay signal Preset Time output exporting described pulse-generating circuit.
6. a kind of analog-digital converter adc is it is characterised in that include: digital to analog converter dac, comparator, data register and logic
Circuit, described data register includes multistage latch, and every grade of described latch connects a described logic circuit；
The outfan of the first input end described data register of connection of described dac, the second input input reference voltage signal,
Outfan connects the inverting input of described comparator；The in-phase input end of described comparator inputs voltage signal to be converted；
The first input end of each described logic circuit connects the outfan of described comparator, the second input of described logic circuit
End connects the first outfan of described clock generation circuit, and the outfan of described logic circuit connects the same one-level of described logic circuit
Described latch control end；The input input predetermined level signal of described latch, the clock control of described latch
End connects the second outfan of described clock generation circuit；
Described logic circuit, for controlling the output in initial preset duration of current adc clock cycle of described latch default
Level signal, and after described preset duration, control the output of comparator described in described latches；
The input input adc clock cycle signal of described clock generation circuit, described first outfan output the first clock letter
Number, described second outfan output second clock signal.
7. in a kind of analog-digital converter adc comparator time delay correction method it is characterised in that being applied in adc, described adc bag
Include digital to analog converter dac, comparator, data register and logic circuit, described data register includes multistage latch, every grade
Described depositor corresponds to a described logic circuit；Methods described includes:
In initial preset duration within the current adc clock cycle, described logic circuit produces the first level signal, and will be described
First level signal is supplied to the latch being in same one-level in described data register with described logic circuit, so that described lock
Storage exports predetermined level signal in described preset duration；
After initial preset duration of current adc clock cycle, described logic circuit is according to the output signal of described comparator
Output second electrical level signal, and described second electrical level signal is supplied to described latch, so that described latch is described pre-
If latching the output signal of described comparator after duration.
8. method according to claim 7 is it is characterised in that described predetermined level signal is high level signal.
9. method according to claim 8 it is characterised in that
In described initial preset duration within the current adc clock cycle, described logic circuit produces the first level signal, bag
Include:
In initial preset duration of current adc clock cycle, the high level that described logic circuit inputs according to first input end
Signal output low level signal；
After the described preset duration initial in the current adc clock cycle, described logic circuit is according to the output of described comparator
Signal output second electrical level signal, comprising:
After initial preset duration of current adc clock cycle, when described comparator output high level signal, described logic
Circuit output low level signal；
After initial preset duration of current adc clock cycle, when described comparator output low level signal, described logic
Circuit output high level signal.
10. method according to claim 8 is it is characterised in that the output signal of described logic circuit inputs to described lock
The reset terminal of storage, methods described also includes:
After initial preset duration of current adc clock cycle, when described logic circuit output high level signal, control institute
State latch output low level signal；When described logic circuit output low level signal, control the high electricity of described latch output
Ordinary mail number.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610871262.4A CN106357268B (en) | 2016-09-29 | 2016-09-29 | Time delay correction circuit and method for comparator in ADC (analog to digital converter) and ADC |
| PCT/CN2017/076301 WO2018058900A1 (en) | 2016-09-29 | 2017-03-10 | Comparer delay correction circuit in adc, method and adc |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610871262.4A CN106357268B (en) | 2016-09-29 | 2016-09-29 | Time delay correction circuit and method for comparator in ADC (analog to digital converter) and ADC |
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| CN106357268A true CN106357268A (en) | 2017-01-25 |
| CN106357268B CN106357268B (en) | 2019-08-23 |
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| WO (1) | WO2018058900A1 (en) |
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| WO2018058900A1 (en) * | 2016-09-29 | 2018-04-05 | 珠海格力电器股份有限公司 | Comparer delay correction circuit in adc, method and adc |
| CN107907173A (en) * | 2017-12-14 | 2018-04-13 | 湖北天禹环保科技有限公司 | A kind of analog-digital converter for ultrasonic gas flowmeter |
| CN113497619A (en) * | 2020-04-03 | 2021-10-12 | 龙芯中科技术股份有限公司 | Trigger circuit, control circuit and chip |
| CN110535470B (en) * | 2019-08-26 | 2022-06-14 | 中国电子科技集团公司第二十四研究所 | Comparator clock generation circuit and high-speed successive approximation type analog-to-digital converter |
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| CN109257023B (en) * | 2018-08-24 | 2022-10-14 | 中国电子科技集团公司第三十六研究所 | Power amplifier protection circuit and method |
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| WO2018058900A1 (en) | 2018-04-05 |
| CN106357268B (en) | 2019-08-23 |
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