CN106330394B - Configurable interleaver and de-interleaver with cyclic characteristic - Google Patents
Configurable interleaver and de-interleaver with cyclic characteristic Download PDFInfo
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Abstract
The invention provides a configurable interleaver and a de-interleaver with cyclic characteristics, wherein the interleaver comprises: the interleaving unit segmentation device is used for performing interleaving unit segmentation on the data stream to be interleaved; the interleaving time delay module is used for performing interleaving operation on the interleaving unit flow; the interleaving delay module comprises a plurality of delay branch groups, each group comprises a specified number of delay branches, the number of the delay branch groups and the number of the delay branches in each group are dynamically configured by physical layer signaling, and the configuration modes of the delay branch groups are the same; the branch selection and counter is used for adjusting the number of delay branches actually used by the interweaving delay module; and the transmission frame mapper is used for mapping the interleaved data to respective time division multiplexing channels in the actual transmission frame. The de-interleaver is used for de-interleaving the interleaved unit flow after interleaving by the interleaver. The interleaver provided by the invention has the advantages of performance meeting the actual application requirements, less resource consumption and less signaling overhead.
Description
Technical Field
The present invention relates to an interleaver in the field of communication technology, and in particular, to a configurable interleaver with cyclic characteristics, and a corresponding deinterleaver.
Background
In a digital communication system, a series of random errors and burst errors occur in a finally received signal due to various interferences during transmission. Error control coding techniques are commonly used to detect and correct errors in received signals, and in particular, have good error correction performance for random errors. However, for a long burst error, the large continuous error caused by the burst error often exceeds the error correction capability of the error control coding, and at this time, the corresponding error control coding cannot correct the error and may introduce more errors.
In order to solve this problem, an interleaver is used to break up the order between symbols and destroy the correlation between symbols, thereby scattering long burst errors and improving the error correction performance of the system without increasing the coding overhead.
The interleaver plays an important role in a communication system, and particularly for a mobile receiving scenario, the interleaver can effectively help a receiver to resist signal fading and burst errors caused by a dynamic channel, and the robustness of the system is improved through time diversity.
The existing interleaver can not be well adapted to the mobile application scene of the communication system, can not make good balance between interleaving gain and resource consumption aiming at specific situations, and has large signaling overhead.
Through retrieval, the publication number is CN105490776A, the application number is CN201510849339.3, the invention discloses an interleaving method and an interleaver, the method comprises the following steps: acquiring data to be interleaved, and mapping two-dimensional serial numbers of the data to be interleaved according to a preset rule to obtain an interleaving matrix, wherein each element in the interleaving matrix corresponds to one data in the data to be interleaved one by one; dividing the interleaving matrix into at least two interleaving blocks according to rows; respectively writing data corresponding to elements in each interleaving block into an interleaving memory according to a first operation mode by taking the interleaving block as a unit; reading out data corresponding to the interleaving blocks from the interleaving memory according to a second operation mode by taking the interleaving blocks as units; the first operation mode is a row writing mode, and the second operation mode is a column reading mode; or the first operation mode is a column writing mode and the second operation mode is a row reading mode.
However, in principle, the interleaving method used in the above patent belongs to packet interleaving, which consumes large memory resources and causes a high time delay. Moreover, the interleaving mode of the interleaver in the above patent is fixed, and in practical use, parameters such as interleaving depth and time delay are fixed and unchanged. Therefore, the method cannot be well adapted to complex and variable channel environments, and cannot balance factors such as interleaving depth and system delay according to actual requirements. In addition, the interleaving design of the interleaver in the above patent is independent, and does not take into account the characteristic difference of different data streams, so it is difficult to achieve better interleaving performance and better compatibility with different systems.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a configurable interleaver and deinterleaver with cyclic characteristics, which, in combination with a mobile application scenario and a three-state channel of a communication system, have performance meeting practical application requirements, and have low resource consumption and low signaling overhead.
According to an aspect of the present invention, there is provided a configurable interleaver having a cyclic characteristic, comprising:
the interleaving unit segmenter is used for segmenting an Interleaving Unit (IU) of a data stream to be interleaved so as to change the data stream into the IU stream, and the IU stream output by the interleaving unit segmenter enters an interleaving delay module controlled by a branch selection and counter;
the interleaving delay module is used for enabling the IU flow to enter each delay branch group for interleaving operation and outputting the interleaved IU flow; the interleaving delay module comprises a plurality of delay branch groups, each group comprises a specified number of delay branches, the number of the delay branch groups and the number of the delay branches in each group are dynamically configured by physical layer signaling, the delay amount configuration of the delay branches has a cycle characteristic, and the cycle is carried out by taking the delay branch groups as units, the delay amount of each delay branch in one delay branch group is flexibly set by the physical layer signaling according to the actual performance requirement, but the configuration mode of each delay branch group is the same, so that the signaling overhead is reduced;
the branch selection and counter is used for adjusting the number of delay branches of the actually used interleaving delay module so as to realize the balance of interleaving performance and system delay;
and a transmission frame mapper for mapping the interleaved unit streams to respective time division multiplexing channels in the actual transmission frame.
Preferably, the data stream to be interleaved is composed of error control coded codewords of a specified code length, and each codeword is sliced into a certain number of interleaved units by an interleaved unit slicer.
More preferably, the number of interleaved units that are sliced out for each codeword is preferably selected for error control coding of different code lengths based on the actual channel characteristics modeled by the three-state channel model.
Preferably, the interleaving delay module is composed of a plurality of delay branches, the interleaving unit stream sequentially enters each delay branch through a branch selection and counter, and in each clock cycle, the shift register of each branch shifts once, that is, one interleaving unit.
Preferably, the delay amount configuration of the delay branches has a cyclic characteristic, and the cycle is performed by taking the delay branch group as a unit, and the physical layer signaling only needs to transmit the delay amount configuration of one group of delay branch groups to the receiver, so that the deinterleaving of all the delay branches can be realized.
Preferably, the interleaving delay module includes a delay branch, a storage unit, and a multiplexer; the interleaving unit is the minimum operation unit of the interleaving delay module, and each storage unit in the interleaving delay module stores one interleaving unit; the interleaving unit stream enters a delay branch through a multiplexer, and in each clock period, the multiplexer firstly inputs one interleaving unit into the delay branch which is pointed to currently, and then the multiplexer points to the next branch; the memory group in each branch circuit is a shift register, and in each clock period, all the shift registers shift to the right by one bit, namely an interleaving unit; all the multiplexers operate synchronously and output the interleaved elementary streams.
The interleaver is suitable for multi-service transmission based on physical layer pipelines, each physical layer pipeline is used for transmitting one path of service data, the data in each physical layer pipeline is independently interleaved, and interleaving parameters can be independently set.
Aiming at the condition that the code length of the error control code is variable in practical application, the number of the delay branches which are actually used can be dynamically adjusted through branch selection and a counter.
According to a second aspect of the present invention, there is provided a configurable deinterleaver having a cyclic characteristic, for deinterleaving a stream of interleaved units interleaved by the interleaver, the deinterleaver comprising:
a transmission frame demapper for demapping the actual transmission frame received by the receiver into interleaved unit streams carried by the physical layer pipes;
the branch selection and counter is used for adjusting the number of delay branches of the de-interleaving delay module which is actually used, and the number of the delay branches of the de-interleaving delay module which is actually used is the same as the number of the delay branches of the corresponding interleaving delay module in corresponding time;
a de-interleaving delay module for performing de-interleaving operation on the interleaved unit flow and outputting the de-interleaved unit flow; the de-interleaving delay module comprises a plurality of delay branch groups, each group comprises a specified number of delay branches, the number of the delay branch groups and the number of the delay branches in each group are dynamically configured by physical layer signaling, the delay amount of each delay branch in one delay branch group is flexibly set by the physical layer signaling according to the actual performance requirement, but the configuration mode of each delay branch group is the same, and in addition, the delay amount configuration of each delay branch is opposite to the corresponding branch in the interleaving delay module;
and the interleaving unit combiner is used for combining the interleaving units subjected to de-interleaving so as to recover the interleaving unit flow into the data flow.
Compared with the prior art, the invention has the following beneficial effects:
the design of the interleaver of the invention considers the characteristic difference of different data streams, and the corresponding interleaving unit segmentation is carried out on the different data streams through the interleaving unit segmenter, so that the targeted interleaving mode can be implemented on the different data streams, and further the better performance can be realized under the different data streams. This makes the interleaver of the present invention more compatible with systems using different data streams and better adaptable to systems with variable code length.
The interleaver of the invention can dynamically configure the number of the delay branch groups, the number of the delay branches in each group, the delay amount of each delay branch in a delay branch group and the actually used delay branch through physical layer signaling, thereby dynamically adjusting system parameters such as interleaving depth, time delay and the like. The interleaver of the invention can adapt to complex and changeable channel environment, can dynamically and timely balance among system parameter indexes, and has higher flexibility.
The delay amount configuration of the delay branch in the interleaver has a cyclic characteristic, and the cyclic characteristic is performed by taking the delay branch group as a unit. The physical layer signaling only needs to transmit the delay amount configuration information of one group of delay branches to the receiver, and the de-interleaving of all the delay branches can be realized. Compared with the prior mode of transmitting all the configuration information, the interleaver of the invention has smaller signaling overhead.
The interleaver of the present invention can map the interleaved unit streams carrying different services to respective time division multiplexing channels in the actual transmission frame through the transmission frame mapper. This makes the interleaver of the present invention applicable to multi-service transmission based on physical layer pipe.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
FIG. 1 is a block diagram of an interleaver in an embodiment of the present invention;
in fig. 1: 11 is interleaving unit slicer, 12 is branch selecting and counter, 13 is interleaving delay module, 14 is transmission frame mapper;
FIG. 2 is a block diagram of a corresponding deinterleaver in an embodiment of the invention;
in fig. 2: 21 is a transmission frame demapper, 22 is a branch selection and counter, 23 is a deinterleaving delay module, and 24 is an interleaving unit combiner;
fig. 3 is a schematic diagram of an interleaving delay module and a corresponding de-interleaving delay module in an embodiment of the present invention;
in fig. 3: 31 is a delay branch, 32 is a memory unit, 33 is a multiplexer, and 34 is a channel.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that variations and modifications can be made by persons skilled in the art without departing from the spirit of the invention. All falling within the scope of the present invention.
The interleaver shown in fig. 1 includes an interleaving unit slicer 11, a tributary selection and counter 12, an interleaving delay module 13, and a transmission frame mapper 14.
An interleaving unit slicer 11 for performing interleaving unit slicing on the data stream to be interleaved according to the channel condition and the data stream characteristics to convert the data stream into an interleaving unit stream, and the interleaving unit stream output by the interleaving unit slicer enters an interleaving delay module controlled by the branch selection and counter;
an interleaving delay module 13, which performs interleaving operation on the interleaved unit stream and outputs an interleaved unit stream; the interleaving delay module comprises a plurality of delay branch groups, each group comprises a specified number of delay branches, the number of the delay branch groups and the number of the delay branches in each group are dynamically configured by physical layer signaling, the delay amount of each delay branch in one delay branch group is flexibly set by the physical layer signaling according to actual performance requirements, but the configuration modes of each delay branch group are the same;
a branch selection and counter 12 for adjusting the number of delay branches of the actually used interleaving delay module to realize the balance of interleaving performance and system delay;
and a transmission frame mapper 14 for mapping the interleaved unit streams to the respective time division multiplexing channels in the actual transmission frame.
Specifically, the data stream to be interleaved consists of error control coding codewords of specified code length, each codeword is partitioned into a certain number of Interleaving Units (IU) by an interleaving unit slicer as shown in table 1, a preferred example of IU is given based on the NGB-S system, for an error control coding codeword of a specific length, the number of IU in the corresponding single codeword is preferably selected based on the actual channel characteristics simulated by the three-state channel model, where K _ L ength is the information bit length, CR is the coding rate, CW _ L ength is the codeword length, and CW _ IU is the number of IU in each codeword.
TABLE 1
The IU stream output by the interleave unit slicer 11 enters an interleave delay module 13 controlled by a tributary select and counter 12.
As shown in fig. 2, a configurable deinterleaver having a cyclic characteristic for deinterleaving an interleaved unit stream interleaved by the interleaver, the deinterleaver comprising:
a transmission frame demapper 21, configured to demap an actual transmission frame received by the receiver into interleaved unit streams carried by each physical layer pipe;
a branch selection and counter 22 for adjusting the number of delay branches of the de-interleaving delay module actually used, wherein the number of delay branches of the de-interleaving delay module actually used is the same as the number of delay branches of the corresponding interleaving delay module in the corresponding time;
a deinterleaving delay module 23, configured to perform deinterleaving operation on the interleaved elementary stream, and output the deinterleaved interleaved elementary stream; the de-interleaving delay module 23 includes a plurality of delay branch groups, each group includes a specified number of delay branches, the number of the delay branch groups and the number of the delay branches in each group are dynamically configured by physical layer signaling, the delay amount of each delay branch in a delay branch group is flexibly set by physical layer signaling according to actual performance requirements, but the configuration mode of each delay branch group is the same, and in addition, the delay amount configuration of each delay branch is opposite to the corresponding branch in the interleaving delay module;
and an interleaving unit combiner 24 for combining the deinterleaved interleaving units to restore the interleaving unit stream to a data stream.
As shown in fig. 3, a schematic diagram of the structure of the interleaving delay module and the corresponding de-interleaving delay module includes a delay branch 31, a storage unit 32, a multiplexer 33, and a channel 34. IU is the minimum unit of operation of the interleaving delay module 13, and each memory unit in the interleaving delay module 13 can store one IU. The data stream enters the delay branch via the first multiplexer S1. at each clock cycle, the first multiplexer S1 first enters one IU into the delay branch currently pointed to, and then the first multiplexer S1 points to the next branch. The memory banks in each branch are shift registers, all shifted to the right by one bit (i.e., one IU) per clock cycle. The second multiplexer S2 operates in synchronization with the first multiplexer S1 and outputs an interleaved IU stream.
The IU stream then goes through mapping, channel (tri-state channel) and demapping, and enters the de-interleaving delay module of the receiver, which is similar in structure and operation to the interleaving delay module. The IU stream enters the delay branch via multiplexer S3, and at each clock cycle, the third multiplexer S3 first inputs one IU into the delay branch currently pointed to, and then S3 points to the next branch. The memory banks in each branch are shift registers, all shifted to the right by one bit (i.e., one IU) per clock cycle. The third multiplexer S3 operates in synchronization with the fourth S4 to finally restore the original order of the data.
An example of the configuration of the interleaving delay module 13 is given below in conjunction with the actual channel environment (tri-state channel) and performance requirements. Preferably, the interleaving delay module 13 has 120 delay branches, and each 60 delay branches are a group, and there are two groups. In actual use, the number of delay branch groups may be dynamically configured by physical layer signaling according to CW _ IU and performance requirements. The delay amount of the 60 delay branches in a group can be flexibly set according to actual performance requirements. The configuration modes of the delay branches of the two groups are the same to reduce the signaling overhead. Fig. 1 shows a typical delay branch configuration, where a group includes 60 delay branches, the first branch has no delay, and then each branch adds 1 IU of delay (i.e. 1 memory location).
The number of the delay branches used in practice can be dynamically adjusted for the case that the code length of the error control code is variable in practical application. For example, in the above example, 120 branches need not be used in their entirety, and only a portion of them may be used to reduce latency. The number of delay branches actually used is controlled by the branch selection and counter. In one embodiment, the delay branch usage is shown in table 2 according to the code length, where BR _ ID is the branch number used. After the number of delay branches actually used is determined, the value of the counting mechanism in the branch selection and counter is increased by 1 every time the direction of the multiplexer is changed. When the count value reaches the sequence number of the last delay branch used, the direction of the multiplexer is reset to the first delay branch. In addition, the delay branch configuration mode takes 60 branches as a cycle, and the signaling overhead is reduced.
TABLE 2
Compared with the interleaving mode of the patent in the background art, the interleaving mode of the invention can save half of memory resources and reduce nearly one time of time delay on the premise of the same interleaving depth.
The interleaver of the present invention can dynamically configure the number of delay branch groups, the number of delay branches in each group, the delay amount of each delay branch in a delay branch group, and the actually used delay branch through physical layer signaling. Therefore, the method is suitable for complex and variable channel environments, can dynamically and timely balance among system parameter indexes, and has high flexibility.
The interleaver provided by the invention can implement a targeted interleaving mode on different data streams by using different interleaving unit segmentation, thereby realizing better performance under different data streams. This makes the interleaver proposed by the present invention better compatible with systems using different data streams and also better adaptable to systems with variable code length.
The interleaver is suitable for multi-service transmission based on a physical layer pipeline. Each physical layer pipe may be used to transmit one path of traffic data. The data in each physical layer pipe is interleaved independently, and interleaving parameters can be set independently. The data output by the interleaving delay module is mapped to the time division multiplexing channels in the actual transmission frame through the transmission frame mapper according to the physical layer pipeline to which the interleaving delay module belongs.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes and modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention.
Claims (10)
1. A configurable interleaver having a cyclic characteristic, comprising:
the interleaving unit slicer is used for interleaving unit slicing on a data stream to be interleaved so that the data stream is converted into an interleaving unit stream, and the interleaving unit stream output by the interleaving unit slicer enters an interleaving delay module controlled by a branch selection and counter;
the interleaving delay module performs interleaving operation on the interleaving unit flow and outputs the interleaved interleaving unit flow; the interleaving delay module comprises a plurality of delay branch groups, each group comprises a specified number of delay branches, the number of the delay branch groups and the number of the delay branches in each group are dynamically configured by physical layer signaling, the delay amount of each delay branch in one delay branch group is flexibly set by the physical layer signaling according to actual performance requirements, but the configuration modes of each delay branch group are the same; the configuration mode refers to the configuration of the number of delay branches in the delay branch group and the configuration of the delay amount of each delay branch;
the branch selection and counter is used for adjusting the number of delay branches of the interleaving delay module which is actually used so as to realize the balance of interleaving performance and system delay;
and a transmission frame mapper for mapping the interleaved unit streams to respective time division multiplexing channels in the actual transmission frame.
2. The configurable interleaver with round robin feature of claim 1 wherein said data stream to be interleaved is comprised of error control coded codewords of a specified code length, each codeword being sliced into a number of interleaved units by an interleaved unit slicer.
3. The configurable interleaver with cyclic property of claim 2, wherein the interleaver slicer optimizes the number of interleaves that are sliced out per codeword for error control coding of different code lengths based on the actual channel properties modeled by the three-state channel model.
4. The configurable interleaver with cyclic property of claim 3, wherein the interleave unit slicer adopts an interleave unit slicing scheme as follows:
for the information bit length of 34560 bits: 1/2 code rate, 69120bits code length, each code word is divided into 120 interleaving units; 3/5 code rate, 57600bits code length, each code word is divided into 100 interleaving units; 2/3 code rate, 51840bits code length, each code word is divided into 90 interleaving units; 3/4 code rate, 46080bits code length, each code word is divided into 80 interleaving units; 6/7 code rate, 40320bits code length, each code word is divided into 70 interleaving units;
for the information bit length of 17280 bits: 1/4 code rate, 69120bits code length, each code word is divided into 120 interleaving units; 1/3 code rate, 51840bits code length, each code word is divided into 90 interleaving units; at code rate of 2/5 and code length of 43200bits, each code word is divided into 75 interleaving units.
5. The configurable interleaver with cyclic characteristic of claim 1, wherein the interleaving delay module comprises a delay branch, a memory unit, a multiplexer; the interleaving unit is the minimum operation unit of the interleaving delay module, and each storage unit in the interleaving delay module stores one interleaving unit; the interleaving unit flow is controlled by a branch selection and counter and enters a delay branch through a multiplexer, and in each clock period, the multiplexer firstly inputs one interleaving unit into the delay branch which is pointed to currently, and then the multiplexer points to the next branch; the memory group in each branch circuit is a shift register, and in each clock period, all the shift registers shift to the right by one bit, namely an interleaving unit; all the multiplexers operate synchronously and output the interleaved elementary streams.
6. The interleaver as claimed in claim 1, wherein the delay amount configuration of the delay branches has a cyclic characteristic, and the cyclic configuration is performed in units of delay branch groups, and the physical layer signaling only needs to transmit the delay amount configuration of one delay branch group to the receiver to achieve de-interleaving for all delay branches.
7. The configurable interleaver with round robin feature of claim 1 wherein the number of delay branches actually used is dynamically adjusted by said branch selection and counter.
8. The interleaver according to claim 7, wherein the delay branch is implemented by:
for the information bit length of 34560 bits: when the code rate is 1/2 and the code length is 69120bits, the 1 st to 120 th delay branches are actually used; when the code rate is 3/5 and the code length is 57600bits, the 1 st to 100 th delay branches are actually used; 2/3 code rate and 51840bits code length, actually using the 1 st to 90 th delay branch; when the code rate is 3/4 and the code length is 46080bits, the 1 st to 80 th delay branches are actually used; when the code rate is 6/7 and the code length is 40320bits, the 1 st to 70 th delay branches are actually used;
for the information bit length of 17280 bits: when the code rate is 1/4 and the code length is 69120bits, the 1 st to 120 th delay branches are actually used; 1/3 code rate and 51840bits code length, actually using the 1 st to 90 th delay branch; when the code rate is 2/5 and the code length is 43200bits, the 1 st to 75 th delay branches are actually used.
9. A configurable interleaver with round robin feature as claimed in any of claims 1-8, wherein the interleaver is adapted to multi-service transport based on physical layer pipes, each physical layer pipe is used to transport one traffic data, and the data in each physical layer pipe is interleaved separately and interleaving parameters can be set independently.
10. A configurable deinterleaver for deinterleaving a stream of interleaved units interleaved by the interleaver of any one of claims 1 to 9, having a cyclic characteristic, characterized in that: the deinterleaver includes:
a transmission frame demapper for demapping the actual transmission frame received by the receiver into interleaved unit streams carried by the physical layer pipes;
the branch selection and counter is used for adjusting the number of delay branches of the de-interleaving delay module which is actually used, and the number of the delay branches of the de-interleaving delay module which is actually used is the same as the number of the delay branches of the corresponding interleaving delay module in corresponding time;
a de-interleaving delay module for performing de-interleaving operation on the interleaved unit flow and outputting the de-interleaved unit flow; the de-interleaving delay module comprises a plurality of delay branch groups, each group comprises a specified number of delay branches, the number of the delay branch groups and the number of the delay branches in each group are dynamically configured by physical layer signaling, the delay amount of each delay branch in one delay branch group is flexibly set by the physical layer signaling according to the actual performance requirement, but the configuration mode of each delay branch group is the same, and in addition, the delay amount configuration of each delay branch is opposite to the corresponding branch in the interleaving delay module; the configuration mode refers to the configuration of the number of delay branches in the delay branch group and the configuration of the delay amount of each delay branch;
and the interleaving unit combiner is used for combining the interleaving units subjected to de-interleaving so as to recover the interleaving unit flow into the data flow.
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