CN106328581A - Wafer bonding method and wafer bonding structure - Google Patents
Wafer bonding method and wafer bonding structure Download PDFInfo
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- CN106328581A CN106328581A CN201510381677.9A CN201510381677A CN106328581A CN 106328581 A CN106328581 A CN 106328581A CN 201510381677 A CN201510381677 A CN 201510381677A CN 106328581 A CN106328581 A CN 106328581A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention provides a wafer bonding method and a wafer bonding structure, wherein the wafer bonding method comprises the steps of providing a first wafer and a second wafer; covering metal material layers on the first dielectric layers of the first and second wafers; carrying out the first grinding operation on the metal material layers and the first dielectric layers, forming the second dielectric layers on the surfaces of the first dielectric layers after the surfaces of the first dielectric layers are exposed, carrying out the second grinding operation on the second dielectric layers, the first dielectric layers and metal pads, and exposing the surfaces of the metal pads in the grooves, wherein the speed of removing the metal pads is equal to the speed of removing the first and second dielectric layers. After the second grinding operation, the surfaces of the metal pads at different positions of the first wafer are basically parallel and level with the surfaces of the first dielectric layers, so that after the second grinding operation, the thicknesses at the different positions of the first wafer are more uniform. After a bonding technology is carried out on the first and second wafers, the quality of the electric connection between the metal pads in the wafer bonding structure is improved.
Description
Technical field
The present invention relates to semiconductor applications, be specifically related to a kind of wafer bonding method and wafer bonding structure.
Background technology
Contact-type image sensor (Contact Image Sensor, CIS) is the most common half
Conductor sensor, is widely used in the fields such as mobile phone, panel computer, fingerprint recognition.Use 3D IC technology
Make contact-type image sensor and have become as the focus of this area research.Use the contact of 3D IC fabrication techniques
Formula imageing sensor, generally forms data processing circuit in wafer, is formed in another wafer
The pixel of contact-type image sensor, then by two panels wafer bonding together.This production method excellent
Gesture is that chip not only pixel is smaller, and data process faster.In current wafer bond techniques,
After bonding, having gap between the bonded interface of two wafer, the bonding face of i.e. two wafer can not
Directly against being combined.
Refer to Fig. 1, be the schematic diagram of prior art a kind of contact-type image sensor manufacture method.Wherein
It is formed with multiple the first metal end 11 on first wafer 10, the second wafer 20 is formed multiple second metal
End 21.Multiple the first metal ends 11 and multiple second metal end 21 are bonded together correspondingly so that
It is mutually bonded formation contact-type image sensor between first wafer 10 and the second wafer 20.But due to
On first wafer 10, the homogeneity of multiple the first metal end 11 bulge quantities is poor, on the second wafer 20,
The bulge quantity homogeneity of multiple second metal end 21 is poor, as shown in Fig. 1, dotted line is irised out, when multiple first
When metal end 11 and multiple second metal end 21 are bonded together correspondingly, bulge quantity less first
Metal end 11 and the possible loose contact even short circuit of the second metal end 21, affect contact-type image sensor
Performance.
With reference to Fig. 2, in order to avoid loose contact, before wafer bonding, those skilled in the art would generally
Increase the removal amount of oxide layer on the first wafer 10 and the second wafer 20, make the first metal end 11 and the second gold medal
The bulge quantity belonging to end 21 is bigger, but as in figure 2 it is shown, so may cause adjacent two the first metal end
11 or second metal end 21 the most close to each other so that short circuit.
Therefore, how to make the metal end of the first wafer and the second wafer preferably make electrical contact with, to improve crystalline substance
The bonding quality of circle is technical problem urgently to be resolved hurrily.
Summary of the invention
The problem that the present invention solves is to provide a kind of wafer bonding method and wafer bonding structure, makes first
The metal end of wafer and the second wafer preferably makes electrical contact with, and improves the bonding quality of wafer.
For solving the problems referred to above, the present invention provides a kind of wafer bonding method, including:
The first wafer and the second wafer, described first wafer and the second wafer is provided all to include substrate；
Substrate at described first wafer and the second wafer is respectively formed on first medium layer, is situated between described first
Matter layer is formed groove；
Covering metal material layer on described first medium layer, described metal material layer fills full described groove；
Described metal material layer and first medium layer are carried out the first grinding, exposes described first medium layer table
Face, the metal material layer in described groove is metal gasket；
Second dielectric layer is formed, to described second dielectric layer, first medium on described first medium layer surface
Layer and metal gasket carry out the second grinding, expose the metal gasket surface in described groove, grind described second
Step in, to the removal rate of described metal gasket and the removal rate to described first, second dielectric layer
Ratio suitable；
The metal gasket of described first wafer and the second wafer is oppositely arranged and is mutually aligned, to described first
Wafer and the second wafer carry out wafer bonding technique, form wafer bonding structure.
Optionally, described first is ground to cmp, and the described first step ground includes: right
The ratio of the removal rate of described metal material layer and the removal rate to described first medium layer 10:1 with
On.
Optionally, the described first step ground includes: to the removal rate of metal material layer be
4000～8000 angstrom min.
Optionally, described second is ground to cmp, and the described second step ground includes: right
The removal rate of metal gasket is 1000～2000 angstrom min.
Optionally, the thickness of described second dielectric layer is in the range of 1000 to 10000 angstroms.
Optionally, after the described second step ground, carry out back described first medium layer carving, make
Described metal gasket protrudes from described first medium layer surface.
Optionally, in the described first step ground, it is ground degree detecting to determine that described first grinds
The amount of grinding of mill, described degree of grinding is detected as end point determination.
Optionally, in the described second step ground, it is ground degree detecting to determine that described second grinds
The amount of grinding of mill, described degree of grinding is detected as timing and detects.
Optionally, the step covering metal material layer on described first medium layer includes:
Using copper electroplating technology, cover copper product layer on described first medium layer, the described copper material bed of material is made
For described metal material layer.
Optionally, the step covering metal material layer on described first medium layer includes: make described metal
Material layer is at 1 to 10 times that thickness is described depth of groove of described first medium layer surface.
Optionally, after providing the first wafer and the second wafer, at described first wafer and the second wafer
Substrate on formed before first medium layer, described first wafer is formed data processing circuit, described
Pel array is formed on second wafer.
The present invention also provides for a kind of wafer bonding structure, uses any one wafer bonding that the present invention provides
Method is formed.
Compared with prior art, technical scheme has the advantage that at the crystalline substance that the present invention provides
In circle bonding method, the first medium layer of the first wafer and the second wafer covers metal material layer, institute
State metal material layer and fill full described groove；Described metal material layer and first medium layer are carried out first grind
Mill, after exposing described first medium layer surface, forms second dielectric layer on described first medium layer surface,
Described second dielectric layer, first medium layer and metal gasket are carried out the second grinding, exposes in described groove
Metal gasket surface, in the described second step ground, to the removal rate of described metal material layer with right
The removal rate of described first, second dielectric layer is suitable, say, that during grinding second,
The removal rate of described metal gasket and first, second dielectric layer is suitable, it is not easy to produce metal gasket relative to the
The phenomenon that one dielectric layer removal amount is excessive, therefore, after second grinds, described first medium layer and gold
The thickness belonging to pad more flushes, and on the first wafer and the second wafer, the metal gasket thickness of various location is more
Uniformly.After the first wafer and the second wafer are carried out bonding technology, improve gold in wafer bonding structure
The quality of the electrical connection between genus pad.
Accompanying drawing explanation
Fig. 1 and Fig. 2 is the schematic diagram of prior art a kind of wafer bonding technical process；
Fig. 3 to Figure 10 is the schematic diagram of wafer bonding method one embodiment of the present invention.
Detailed description of the invention
In prior art wafer bonding method, in metal end and the metal end pair of the second wafer of the first wafer
When being bonded together with answering, possible loose contact between the metal end that bulge quantity is less, it is also possible to cause short
Connect, affect the quality of wafer bonding structure.
In order to solve above-mentioned technical problem, the present invention proposes a kind of wafer bonding method, including:
The first wafer and the second wafer, described first wafer and the second wafer is provided all to include substrate；
The substrate of described first wafer and the second wafer forms first medium layer, at described first medium
Groove is formed in Ceng；
Covering metal material layer on described first medium layer, described metal material layer fills full described groove；
Described metal material layer and first medium layer are carried out the first grinding, exposes described first medium layer table
Face；
Second dielectric layer is formed, to described second dielectric layer, first medium on described first medium layer surface
Layer and metal material layer carry out the second grinding, expose the metal material layer surface in described groove, expose institute
Stating the metal material layer in groove is metal gasket, in the described second step ground, to described metal material
The removal rate of the bed of material is suitable with to the removal rate of described second dielectric layer；
The metal gasket of described first wafer and the second wafer is oppositely arranged and is mutually aligned, to described first
Wafer and the second wafer carry out wafer bonding technique, form wafer bonding structure.
The present invention is in the described second step ground, to the removal rate of described metal material layer and to institute
The removal rate stating second dielectric layer is suitable, say, that second grinds described metal material layer and institute
State second dielectric layer removal select ratio close so that second grind after, described second dielectric layer and
The thickness of metal gasket more flushes, and on the first wafer and the second wafer, the metal gasket thickness of various location is relatively
For uniformly.After the first wafer and the second wafer are carried out bonding technology, improve in wafer bonding structure
The quality of the electrical connection between metal gasket.
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The specific embodiment of the present invention is described in detail.
With reference to Fig. 3 to Figure 10, it is shown that the schematic diagram of wafer bonding method one embodiment of the present invention.This reality
Execute example wafer bonding method to include:
Thering is provided the first wafer and the second wafer, described first wafer to include the first substrate 100, described second is brilliant
Circle includes the second substrate 200.In the present embodiment, described first substrate 100 and the second substrate 200 are single
Crystalline silicon substrate, in other embodiments, described substrate can also be multicrystalline silicon substrate, amorphous silicon substrate,
Other Semiconductor substrate such as germanium silicon substrate or silicon-on-insulator substrate, do not do any restriction to this present invention.
It should be noted that in the present embodiment, after providing the first wafer and the second wafer, in institute
State formation data processing circuit (not shown) on the first wafer, described second wafer forms pel array (not
Illustrate).The wafer bonding structure that the most described first wafer and the second wafer are formed is used for forming contact figure
As sensor.But the present invention forms data processing circuit to whether on described first wafer, described the
Form pel array on two wafers not limit, described first wafer and the second wafer key and the wafer of formation
Bonding structure can be also used for other semiconductor device, such as processor, motion sensor, pressure transducer
Deng.
On described first wafer formed data processing circuit, on described second wafer formed pel array it
After, described first substrate 100 and the second substrate 200 form first medium layer respectively, described
One dielectric layer is formed groove.It should be noted that form data processing circuit on described first wafer,
After forming pel array on described second wafer, the technique that described first wafer and the second wafer are carried out
Step is essentially identical, therefore, in Fig. 4 to Fig. 9, illustrate only the processing step to the first wafer.
With reference to Fig. 4, described first substrate 100 forms first medium layer 101, at described first medium
Layer 101 is formed groove 102.
In the present embodiment, the material of described first medium layer 101 is silicon oxide, and forming method is chemistry
Vapour deposition, but material and the forming method of first medium layer 101 are not limited by the present invention.
The quantity forming groove 102 in described first medium layer 101 is multiple, and described groove 102 is used
In forming metal gasket.
In the present embodiment, the degree of depth of described groove 102 is in the range of 1000 to 10000 angstroms.
With reference to Fig. 5, described first medium layer 101 covers metal material layer 103, described metal material
Layer 103 fills full described groove.
Specifically, in the present embodiment, copper electroplating technology is used, in described first medium layer 101 overlying
The lid copper material bed of material, the described copper material bed of material is as metal material layer 103.But the present invention is to covering metal material
The method of layer 103 does not limits, in other embodiments, it is also possible to use physical vaporous deposition to cover
Described metal material layer 103, the concrete material of metal material layer 103 is not limited, at it by the present invention
In his embodiment, described metal material layer 103 can also be aluminum or alloy material.
If the thickness H1 that described metal material layer 103 is on described first medium layer 101 surface is excessive, then
The follow-up speed that described metal material layer 103 is carried out cmp is the slowest, if described metal material
The thickness H1 on described first medium layer 101 surface is too small for the bed of material 103, follow-up to described metal material
The cmp that layer 103 is carried out is not easily controlled.In the present embodiment, at described first medium layer
The step covering metal material layer 103 on 101 includes: make described metal material layer 103 be situated between described first
The thickness H1 on matter layer 101 surface is 1 to 10 times of described groove 102 degree of depth.Specifically, can make
The described metal material layer 103 thickness H1 on described first medium layer 101 surface is 3000 to 100000
In the range of angstrom.
In conjunction with reference to Fig. 6, described metal material layer 103 and first medium layer 101 are carried out the first grinding,
Expose described first medium layer 101 surface.
Specifically, in the present embodiment, described first it is ground to cmp.Grind described first
In the step of mill, to the removal rate of described metal material layer 103 and to described first medium layer 101
The ratio of removal rate is at more than 10:1.Wherein, the removal rate to metal material layer 103 is 4000～8000
Angstrom min.Such be advantageous in that, to the removal rate of described metal material layer 103 with to described first
The comparison of the removal rate of dielectric layer 101 is high, it is possible to remove metal material layer 103 rapidly, and described
First medium layer 101 can be as the first stop-layer ground.
After described first grinds, the metal material layer 103 on described first medium layer 101 surface is gone
Remove, described groove 102 is formed metal gasket 104, is used for carrying out wafer bonding technique.
Owing to first grinds the removal rate to described metal material layer 103 and to described first medium layer 101
The comparison of removal rate high, after first grinds, the metal gasket 104 in the described groove of part 102
Surface is likely lower than described first medium layer 101 surface so that metal gasket 104 thickness on the first wafer
Uneven.
It is ground degree detecting, to determine the described first grinding ground in the described first step ground
Amount.The mode of described degree of grinding detection is end point determination (EPD, End-point Detector).Specifically,
Can be selected for optical end point detection described first medium layer 101 and metal material layer 103 surface are detected,
Optical end point detection be the spectrum utilizing on film layer reflection is measured continuously described first grind described in the
One dielectric layer 101 and the change of metal material layer 103 thickness H1, when described metal material layer 103 is gone
Remove, when exposing described first medium layer 101, the spectrum of described first medium layer 101 reflection and described gold
The spectrum belonging to the reflection of material layer is different, thus points out the first grinding to stop.Due to the described first step ground
In Zhou, the removal rate of described metal material layer 103 and the removal rate to described first medium layer 101
Comparison high, when the surface of described first medium layer 101 is exposed, first medium layer 101 is reflected back
The spectrum change that spectrum first medium layer 101 is reflected back is big, when first medium layer 101 runs out of, adopts
Can relatively quickly react by end point determination mode, thus stop the first grinding in time, make described the
One dielectric layer 101 is not easy to be ground damage by described first.
With reference to Fig. 7, form second dielectric layer 105 at described first medium layer 101 and metal gasket 104 surface.
In the present embodiment, the material of described second dielectric layer 105 is silicon oxide, and forming method is chemistry
Vapour deposition, but material and the forming method of second dielectric layer 105 are not limited by the present invention.
Described second dielectric layer 105 is for providing grinding-material for the second follow-up process of lapping, if institute
The thickness stating second dielectric layer 105 is excessive, then the second speed ground is the slowest, if described second medium
The thickness of layer 105 is too small, then the second process ground is difficult to control to, easily damage metal gasket 104, at this
In embodiment, the thickness of described second dielectric layer 105 is in the range of 1000 angstroms to 10000 angstroms
With reference to Fig. 8, described second dielectric layer 105, first medium layer 101 and metal gasket 104 are carried out the
Two grind, and expose described metal gasket 104 surface, in the described second step ground, to described metal
The removal rate of pad 104 is suitable with to the removal rate of described first medium layer 101, second dielectric layer 105,
It is to say, during grinding second, going of described metal gasket 104 and first, second dielectric layer
Removal rates is suitable, optionally, and the ratio of the removal rate of described metal gasket 104 and first, second dielectric layer
In the range of 1:1.5 to 1.5:1.Second process ground can be regarded as and commaterial is carried out chemistry
Mechanical lapping, it is not easy to produce the phenomenon that relative first medium layer 101 removal amount of metal gasket 104 is excessive.
Therefore, second grind after, on the first wafer metal gasket 104 surface of various location the most all and
The surface of first medium layer 101 flushes so that after second grinds, various location on the first wafer
Metal gasket 104 thickness the most uniform.
It should be noted that owing to second grinds needs guarantee to described metal gasket 104 and described first Jie
Matter layer 101, second dielectric layer 105 removal rate close, the most heretofore described first medium layer
101, second dielectric layer 105 can select same material, or selects under the effect of same lapping liquid,
The material that removal rate is suitable.
In the present embodiment, described second it is ground to cmp.If to going of metal gasket 104
Removal rates is excessive, then easily cause metal gasket 104 and remove excess, causes the metal gasket 104 on the first wafer
In uneven thickness, if too small to the removal rate of metal gasket 104, then the second process of lapping expends the time
Long.In the present embodiment, the removal rate of metal gasket 104 is by the second lapping liquid ground
1000～2000 angstrom min.But the present invention grinds the removal rate to metal gasket 104 to second and does not limits
System.
It is ground degree detecting, to determine grinding of described second grinding in the described second step ground
Mill amount.The mode of described degree of grinding detection is timing detection.Specifically, can grind described second
During, extremely multiple reminder time nodes are set, at each reminder time node, pass through optics
Or the mode of electric current measures the thickness of described second dielectric layer 105.Owing to second grinds described metal gasket
104 and described second dielectric layer 105 removal select ratio close, use end point determination mode may cause
Second amount of grinding ground is too much, and therefore the present embodiment uses the detection mode of timing detection, it can be ensured that
Metal gasket 104 is less by the second damage ground.
With reference to Fig. 9, carry out back described first medium layer 101 carving, make described metal gasket 104 protrude from institute
State first medium layer 101 surface.Such it is advantageous in that, in follow-up wafer bonding technique, improves
Described first wafer and the electrical connection quality of the second wafer.
It should be noted that before wafer bonding, processing step and the first wafer to the second wafer are big
Cause identical, it is also possible to reference to Fig. 4 to Fig. 9, the present invention does not repeats them here.Diverse location in second wafer
The metal gasket thickness at place is the most uniform.
With reference to Figure 10, the second substrate 200 of the second wafer is also correspondingly formed first medium layer 101 He
Metal gasket 104, is oppositely arranged the metal gasket 104 of described first wafer and the second wafer and is mutually aligned,
Described first wafer and the second wafer are carried out wafer bonding technique, forms wafer bonding structure.
Owing on the first wafer and the second wafer, metal gasket 104 thickness of various location is the most uniform.?
After first wafer and the second wafer are carried out bonding technology, in wafer bonding structure between metal gasket 104
The quality of electrical connection higher.
In the present embodiment, described wafer bonding structure comprises data processing circuit and pel array, institute
State wafer bonding structure to may be used for forming contact-type image sensor.The most described wafer bonding structure shape
The contact-type image sensor become has higher quality.
The present invention also provides for a kind of wafer bonding structure, and it uses the wafer bonding method shape that the present invention provides
Becoming, in wafer bonding structure, the quality of electrical connection between metal gasket is higher.In described wafer bonding structure
Data processing circuit and pel array can be comprised, be used for forming contact-type image sensor.Therefore described
The contact-type image sensor that wafer bonding structure is formed has higher quality.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore the guarantor of the present invention
The scope of protecting should be as the criterion with claim limited range.
Claims (12)
1. a wafer bonding method, it is characterised in that including:
The first wafer and the second wafer, described first wafer and the second wafer is provided all to include substrate；
Substrate at described first wafer and the second wafer is respectively formed on first medium layer, at described first medium
Groove is formed in Ceng；
Covering metal material layer on described first medium layer, described metal material layer fills full described groove；
Described metal material layer and first medium layer are carried out the first grinding, expose described first medium layer surface,
Metal material layer in described groove is metal gasket；
Second dielectric layer is formed, to described second dielectric layer, first medium layer on described first medium layer surface
Carry out the second grinding with metal gasket, expose the metal gasket surface in described groove, grind described second
Step in, the removal rate to described metal gasket with to described first, second dielectric layer removal speed
Rate is suitable；
The metal gasket of described first wafer and the second wafer is oppositely arranged and is mutually aligned, brilliant to described first
Circle and the second wafer carry out wafer bonding technique, form wafer bonding structure.
2. the method for claim 1, it is characterised in that described first is ground to cmp,
Described first step ground includes: be situated between the removal rate of described metal material layer with to described first
The ratio of the removal rate of matter layer is at more than 10:1.
3. method as claimed in claim 2, it is characterised in that the described first step ground includes: to gold
The removal rate belonging to material layer is 4000～8000 angstrom min.
4. the method for claim 1, it is characterised in that described second is ground to cmp,
Described second step ground includes: the removal rate to metal gasket is 1000～2000 angstrom min.
5. the method for claim 1, it is characterised in that the thickness of described second dielectric layer is 1000
In the range of 10000 angstroms.
6. the method for claim 1, it is characterised in that after the described second step ground, right
Described first medium layer carries out back carving, and makes described metal gasket protrude from described first medium layer surface.
7. the method for claim 1, it is characterised in that grind in the described first step ground
Mill degree detecting is to determine the described first amount of grinding ground, and described degree of grinding is detected as end point determination.
8. the method for claim 1, it is characterised in that grind in the described second step ground
Mill degree detecting is to determine the described second amount of grinding ground, and described degree of grinding is detected as timing and detects.
9. the method for claim 1, it is characterised in that cover metal material on described first medium layer
The step of the bed of material includes:
Use copper electroplating technology, described first medium layer covers copper product layer, described copper material bed of material conduct
Described metal material layer.
10. the method for claim 1, it is characterised in that cover metal material on described first medium layer
The step of the bed of material includes: it is described for making the described metal material layer thickness on described first medium layer surface
1 to 10 times of depth of groove.
11. the method for claim 1, it is characterised in that after the first wafer and the second wafer are provided,
Before the substrate of described first wafer and the second wafer forms first medium layer, brilliant described first
Form data processing circuit on circle, described second wafer is formed pel array.
12. 1 kinds of wafer bonding structures, it is characterised in that use any one wafer key in claim 1 to 11
Conjunction method is formed.
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Cited By (4)
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| CN110112097A (en) * | 2019-05-21 | 2019-08-09 | 德淮半导体有限公司 | The production method of wafer bonding structure and wafer bonding structure |
| WO2020107316A1 (en) * | 2018-11-29 | 2020-06-04 | 深圳市大疆创新科技有限公司 | Image sensor, method for preparing image sensor, and pixel circuit |
| CN113053806A (en) * | 2018-11-29 | 2021-06-29 | 长江存储科技有限责任公司 | Bonding structure and forming method thereof, wafer bonding structure and wafer bonding method |
| CN113539854A (en) * | 2021-07-16 | 2021-10-22 | 芯知微(上海)电子科技有限公司 | Wafer packaging method and packaging structure |
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