CN106328529B - MOS transistor and forming method thereof - Google Patents
MOS transistor and forming method thereof Download PDFInfo
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- CN106328529B CN106328529B CN201510373347.5A CN201510373347A CN106328529B CN 106328529 B CN106328529 B CN 106328529B CN 201510373347 A CN201510373347 A CN 201510373347A CN 106328529 B CN106328529 B CN 106328529B
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- 238000000034 method Methods 0.000 title claims abstract description 53
- 239000010410 layer Substances 0.000 claims abstract description 381
- 239000004065 semiconductor Substances 0.000 claims abstract description 47
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 239000011229 interlayer Substances 0.000 claims abstract description 39
- 239000000463 material Substances 0.000 claims description 63
- 229910052751 metal Inorganic materials 0.000 claims description 27
- 239000002184 metal Substances 0.000 claims description 27
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 25
- 229910052718 tin Inorganic materials 0.000 claims description 25
- 238000002513 implantation Methods 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 15
- 238000000231 atomic layer deposition Methods 0.000 claims description 15
- 229910008482 TiSiN Inorganic materials 0.000 claims description 14
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 claims description 14
- 229910010038 TiAl Inorganic materials 0.000 claims description 12
- 230000004888 barrier function Effects 0.000 claims description 12
- 229910052799 carbon Inorganic materials 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 239000007943 implant Substances 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 7
- 239000000376 reactant Substances 0.000 claims description 6
- XJDNKRIXUMDJCW-UHFFFAOYSA-J titanium tetrachloride Chemical group Cl[Ti](Cl)(Cl)Cl XJDNKRIXUMDJCW-UHFFFAOYSA-J 0.000 claims description 6
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- 229910004129 HfSiO Inorganic materials 0.000 claims description 4
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 229910008599 TiW Inorganic materials 0.000 claims description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- 229910021529 ammonia Inorganic materials 0.000 claims description 3
- 229910052593 corundum Inorganic materials 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 229910052707 ruthenium Inorganic materials 0.000 claims description 3
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 claims description 3
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 description 37
- 230000008859 change Effects 0.000 description 32
- -1 silicon ion Chemical class 0.000 description 13
- 230000008569 process Effects 0.000 description 11
- 239000013078 crystal Substances 0.000 description 10
- 238000000137 annealing Methods 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 238000002347 injection Methods 0.000 description 7
- 239000007924 injection Substances 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- 229910021332 silicide Inorganic materials 0.000 description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 6
- 239000000126 substance Substances 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 5
- 238000000227 grinding Methods 0.000 description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 4
- 239000004411 aluminium Substances 0.000 description 4
- REDXJYDRNCIFBQ-UHFFFAOYSA-N aluminium(3+) Chemical group [Al+3] REDXJYDRNCIFBQ-UHFFFAOYSA-N 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
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- 229910052906 cristobalite Inorganic materials 0.000 description 2
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- 238000001312 dry etching Methods 0.000 description 2
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- 239000007772 electrode material Substances 0.000 description 2
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- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
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- 239000000969 carrier Substances 0.000 description 1
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- 238000011049 filling Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of MOS transistor and forming method thereof, wherein method includes: offer semiconductor substrate, and the semiconductor substrate surface has interlayer dielectric layer, has the opening through the interlayer dielectric layer thickness in the interlayer dielectric layer；Form the gate dielectric layer for covering the open bottom and side wall；Form the first work-function layer for covering the gate dielectric layer surface；First ion implanting is carried out to first work-function layer, so that first work-function layer is changed into the second work-function layer；The gate electrode layer on covering second work-function layer surface is formed, the gate electrode layer is flushed with the inter-level dielectric layer surface.The forming method of the MOS transistor improves the performance of MOS transistor.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of MOS transistor and forming method thereof.
Background technique
MOS (Metal-oxide-semicondutor) transistor, is one of most important element in modern integrated circuits, and MOS is brilliant
The basic structure of body pipe includes: semiconductor substrate；Positioned at the gate structure of semiconductor substrate surface；Positioned at gate structure two sides
Source-drain area.The gate structure includes: the grid positioned at the gate dielectric layer of semiconductor substrate surface and positioned at gate dielectric layer surface
Electrode layer.The material of the gate dielectric layer is usually oxide, such as SiO2。
As MOS transistor integrated level is higher and higher, the voltage and current of MOS transistor need of work is constantly reduced, brilliant
The speed of body pipe switch is accelerated therewith, increases substantially therewith to requirement in terms of semiconductor technology.Therefore, industry has found substitution
SiO2High dielectric constant material (High-K Material) be used as gate dielectric layer, it is brilliant with better isolated gate structure and MOS
The other parts of body pipe reduce electric leakage.Meanwhile in order to compatible with high K (K is greater than 3.9) dielectric constant material, using metal material
Original polysilicon is substituted as gate electrode layer.The electric leakage of the MOS transistor of high-K gate dielectric layer metal gate electrode further decreases.
MOS transistor with high-K dielectric layer and metal gate structure, comprising: semiconductor substrate；Positioned at semiconductor substrate
The gate structure and dielectric layer on surface, and the top surface of the gate structure is flushed with the dielectric layer surface, the grid
Structure include: the high-K gate dielectric layer positioned at semiconductor substrate surface, the work-function layer positioned at the high-K gate dielectric layer surface and
Metal gate layers positioned at the work-function layer surface；Source-drain area in the gate structure semiconductor substrates on two sides.
Then, the performance of the MOS transistor in the prior art with high-K dielectric layer and metal gate structure is poor.
Summary of the invention
Problems solved by the invention is to provide a kind of MOS transistor and forming method thereof, improves the performance of MOS transistor.
To solve the above problems, the present invention provides a kind of forming method of MOS transistor, comprising: semiconductor substrate is provided,
The semiconductor substrate surface has interlayer dielectric layer, has in the interlayer dielectric layer through the interlayer dielectric layer thickness
Opening；Form the gate dielectric layer for covering the open bottom and side wall；Form the first work content for covering the gate dielectric layer surface
Several layers；First ion implanting is carried out to first work-function layer, so that first work-function layer is changed into the second work function
Layer；The gate electrode layer on covering second work-function layer surface is formed, the gate electrode layer and the inter-level dielectric layer surface are neat
It is flat.
Optionally, second work-function layer has fixed work function.
Optionally, the MOS transistor is PMOS transistor, and the material of first work-function layer is TiN.
Optionally, the MOS transistor is NMOS transistor, and the material of first work-function layer is TiAl.
Optionally, first work-function layer is formed using atomic layer deposition, forerunner's reactant is titanium chloride and ammonia.
Optionally, the ion that uses of the first ion implanting is carried out for silicon ion to the first work-function layer, Implantation Energy is
0.5KeV~3KeV, implantation dosage 1E15atom/cm2~5E18atom/cm2, implant angle is 7 degree~20 degree.
Optionally, first work-function layer is formed using atomic layer deposition, forerunner's reactant is titanium chloride and trimethyl
Aluminium.
Optionally, the ion that uses of the first ion implanting is carried out for carbon ion to the first work-function layer, Implantation Energy is
0.3KeV~2.5KeV, implantation dosage 1E15atom/cm2~5E18atom/cm2, implant angle is 7 degree~20 degree.
Optionally, second work-function layer with a thickness of 10 angstroms~40 angstroms.
Optionally, the MOS transistor is PMOS transistor, and the material of second work-function layer is TiSiN.
Optionally, the MOS transistor is NMOS transistor, and the material of second work-function layer is TiCAl.
Optionally, further includes: before forming the gate dielectric layer, form the interface for covering the open bottom and side wall
Layer.
Optionally, the material of the boundary layer is silica.
Optionally, further includes: before forming the gate electrode layer, form the blocking for covering second work-function layer
Layer.
Optionally, the material on the barrier layer is TiN, TaC, TaN, HfN or ZrN.
Optionally, the gate dielectric layer is high-K gate dielectric layer, and the material of the high-K gate dielectric layer is HfO2、HfSiO、
HfSiON、HfTaO、HfZrO、Al2O3Or ZrO2。
Optionally, the gate electrode layer is metal gate electrode layer, the material of the metal gate electrode layer is Ti, TiW, TiN,
Ti, W, Mo or Ru.
The present invention also provides a kind of MOS transistors formed using above-mentioned any one method, comprising: semiconductor lining
Bottom；Positioned at the interlayer dielectric layer of the semiconductor substrate surface；In the interlayer dielectric layer and run through inter-level dielectric thickness
The opening of degree；Cover the gate dielectric layer of the open bottom and side wall；Second work-function layer on the gate dielectric layer surface is covered,
Second work-function layer has fixed work function；Cover the gate electrode layer on second work-function layer surface, the grid electricity
Pole layer is flushed with the inter-level dielectric layer surface.
Compared with prior art, technical solution of the present invention has the advantage that
The forming method of MOS transistor provided by the invention, due to having carried out the first ion to first work-function layer
Injection, so that first work-function layer is changed into the second work-function layer, so that the second work-function layer in subsequent annealing
Work function will not change, and then not will lead to the change of MOS transistor threshold voltage, improve the performance of MOS transistor.
Further, when MOS transistor to be formed is PMOS transistor, the material of first work-function layer is
TiN carries out the first ion implanting to the first work-function layer, and the ion of first ion implanting is silicon ion, so that the first function
Function is changed into the second work function, and second work function is TiSiN, and TiSiN has non crystalline structure, and there is no the changes of crystal orientation
Change, TiSiN will keep work function constant, and will not cause the change of PMOS transistor threshold voltage in subsequent anneal.
Further, when MOS transistor to be formed is NMOS transistor, the material of first work-function layer is
TiAl carries out the first ion implanting to the first work-function layer, and the ion of first ion implanting is carbon ion, so that the first function
Function is changed into the second work function, and the material of second work-function layer is TiCAl, and carbon ion and aluminium ion form Al-C key,
The diffusion of aluminium can effectively be inhibited, so that the second work-function layer work function is kept fixed, NMOS transistor will not be caused
The change of threshold voltage.
MOS transistor provided by the invention, the second work-function layer have fixed work function, second work-function layer
The value that work function is kept fixed improves the performance of MOS transistor so that the threshold voltage of MOS transistor will not change.
Detailed description of the invention
Fig. 1 to Fig. 4 is the schematic diagram of the section structure of the forming process of MOS transistor in one embodiment of the invention.
Fig. 5 to Figure 11 is the schematic diagram of the section structure of the forming process of MOS transistor in another embodiment of the present invention.
Specific embodiment
The MOS transistor Performance And Reliability formed in the prior art is poor.
Fig. 1 to Fig. 4 is the schematic diagram of the section structure of the forming process of MOS transistor in one embodiment of the invention.
With reference to Fig. 1, semiconductor substrate 100 is provided, there is dummy gate structure 110 and interlayer to be situated between on semiconductor substrate 100 surface
Matter layer 120, the dummy gate structure 110 include pseudo- gate dielectric layer 111 and the pseudo- grid electricity positioned at 111 surface of the pseudo- gate dielectric layer
Pole layer 112, and dummy gate structure 110 runs through the thickness of interlayer dielectric layer 120.
With reference to Fig. 2, dummy gate structure 110 (referring to Fig. 1) is removed, forms opening 113, the 113 exposure semiconductor of opening
The surface of substrate 100.
With reference to Fig. 3, high-K gate dielectric layer 130, the covering height of covering opening 123 (referring to Fig. 2) bottom and side wall are formed
Work-function layer 131, the covering work-function layer 131 and the metal gate electrode for filling full gate mouth 113 on 130 surface of K gate dielectric layer
Layer 132.
When MOS transistor to be formed is N-type MOS transistor, the material of the work-function layer 131 is TiN；When to shape
At MOS transistor be N-type MOS transistor when, the material of the work-function layer 131 is TiAl.
Using depositing operation, such as plasma activated chemical vapour deposition, low-pressure chemical vapor deposition process or atomic layer deposition
Technique etc. forms the work-function layer 131.In the present embodiment, the work-function layer 131 is formed using atom layer deposition process.
With reference to Fig. 4, part high-K gate dielectric layer 130, work-function layer 131 and the metal gate on 120 surface of interlayer dielectric layer are removed
Electrode layer 132.
With interlayer dielectric layer 120 for stop-layer chemical mechanical grinding (CMP) high-K gate dielectric layer 130,131 and of work-function layer
Metal gate electrode layer 132, so that high-K gate dielectric layer 130, work-function layer 131 and metal gate electrode layer 122 and interlayer dielectric layer
120 flush.
It needs to carry out after chemical mechanical grinding high-K gate dielectric layer 130, work-function layer 131 and metal gate electrode layer 132
Hydrogen treat, so that high-K gate dielectric layer 130, work-function layer 131 and 132 surface of metal gate electrode layer have good interfacial state.
Metal silicide layer (not shown) can also be formed on metal gate electrode layer 132 in subsequent, to reduce metal
The contact resistance of gate electrode layer 132.
The study found that the reason that the MOS transistor that the above method is formed still remains Performance And Reliability difference is:
When MOS transistor to be formed is N-type MOS transistor, the material of the work-function layer 131 is TiN, TiN tool
There is polycrystalline structure, TiN crystal orientation during subsequent anneal can change, such as in chemical mechanical grinding high-K gate dielectric layer
130, it needs to carry out hydrogen treat after work-function layer 131 and metal gate electrode layer 132, so that high-K gate dielectric layer 130, work content
Several layers 131 and 132 surface of metal gate electrode layer have good interfacial state, and for another example subsequent needs are in 132 table of metal gate electrode layer
Face forms metal silicide, needs to carry out the high temperature anneal to metal silicide during forming metal silicide, upper
In the annealing process stated, the TiN crystal orientation of polycrystalline structure changes, and can occur in the crystal orientation of the local area of TiN indefinite random
Change, so that the work function of TiN changes, causes the threshold voltage of PMOS transistor to change and PMOS crystalline substance cannot be matched
Body pipe.Especially in the PMOS transistor of static random access memory (SRAM), the Work function Change of work-function layer 131 can be led
Cause the degradation of SRAM device.
When MOS transistor to be formed is N-type MOS transistor, the material of the work-function layer 131 is TiAl, TiAl
Aluminium atom readily diffuse into other media so that the work function of work-function layer 131 changes, cause NMOS transistor
Threshold voltage change and NMOS transistor cannot be matched.It is especially brilliant in the NMOS of static random access memory (SRAM)
In body pipe, the Work function Change of work-function layer 131 will lead to the degradation of SRAM device.
The present invention provides a kind of forming methods of MOS transistor, comprising: provides semiconductor substrate, the semiconductor lining
Bottom surface is formed with interlayer dielectric layer, has the opening through the interlayer dielectric layer thickness in the interlayer dielectric layer；It is formed
Cover the gate dielectric layer of the open bottom and side wall；Form the first work-function layer for covering the gate dielectric layer surface；To institute
It states the first work-function layer and carries out the first ion implanting, so that first work-function layer is changed into the second work-function layer；Formation is covered
The gate electrode layer on second work-function layer surface is covered, the gate electrode layer is flushed with the inter-level dielectric layer surface.
Due to having carried out the first ion implanting to first work-function layer, so that first work-function layer is changed into
Two work-function layers so that the work function of the second work-function layer will not change in subsequent annealing, and then not will lead to MOS
The change of transistor threshold voltage improves the performance of MOS transistor.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
With reference to Fig. 5, semiconductor substrate 200 is provided, there is dummy gate structure 210 and interlayer to be situated between on semiconductor substrate 200 surface
Matter layer 230, dummy gate structure 210 run through the thickness of interlayer dielectric layer 230.
The semiconductor substrate 200 can be monocrystalline silicon, polysilicon or amorphous silicon；Semiconductor substrate 200 be also possible to silicon,
The semiconductor materials such as germanium, SiGe, GaAs；The semiconductor substrate 200 can be body material, be also possible to composite construction,
Such as silicon-on-insulator；The semiconductor substrate 200 can also be other semiconductor materials, no longer illustrate one by one here.This implementation
In example, the material of the semiconductor substrate 200 is silicon.
In the present embodiment, further includes: fleet plough groove isolation structure (not indicating) is formed in semiconductor substrate 200, it is described shallow
Adjacent active area is isolated in groove isolation construction.
The semiconductor substrate 200 can also adulterate different foreign ions according to the type of MOS transistor to be formed,
For adjusting the threshold voltage of MOS transistor.When N-type MOS transistor to be formed, in semiconductor substrate 200 doped p-type from
Son；When N-type MOS transistor to be formed, doped N-type ion in semiconductor substrate 200.
The dummy gate structure 210 includes pseudo- gate dielectric layer 211 and the pseudo- gate electrode layer positioned at pseudo- 211 surface of gate dielectric layer
212。
The material of pseudo- gate dielectric layer 211 is silica, and the material of pseudo- gate electrode layer 212 is polysilicon.
The formation process of the dummy gate structure 210 are as follows: pseudo- grid are deposited using depositing operation on semiconductor substrate 200 and are situated between
The material bed of material and pseudo- layer of gate electrode material；Patterned mask layer, the figure are formed in the pseudo- gate material layer surface
The mask layer of change defines the position for the dummy gate structure 210 to be formed；It is situated between by puppet grid described in mask etching of patterned mask layer
The material bed of material and pseudo- layer of gate electrode material, form dummy gate structure 210.
In the present embodiment, 200 surface of semiconductor substrate of 210 two sides of dummy gate structure is also formed with side wall 220, institute
The material for stating side wall 220 is one of silica, silicon nitride and low-K dielectric material or multiple combinations.
The dummy gate structure 210 defines the position for the gate structure being subsequently formed, and the dummy gate structure 210 is subsequent
It can be removed.
The formation process of the side wall 220 are as follows: the spacer material layer for covering the dummy gate structure 210 is formed, using each
Anisotropy dry etch process etches the spacer material layer, and the side wall in 210 two sides of dummy gate structure forms side wall 220.
The method for forming the interlayer dielectric layer 230 are as follows: formed on 200 surface of semiconductor substrate and cover the dummy grid knot
The interlevel dielectric material layer of structure 210 and side wall 220, and the interlevel dielectric material layer of 210 two sides of dummy gate structure is made to be higher than puppet
The top surface of gate structure 210；The interlevel dielectric material layer is planarized until exposing the top table of dummy gate structure 210
Face forms interlayer dielectric layer 230.The interlayer dielectric layer 230 is flushed with 210 top surface of dummy gate structure.
With reference to Fig. 6, dummy gate structure 210 (referring to Fig. 5) is removed, opening 213 is formed.
After removing the dummy gate structure 210, the part of the surface of semiconductor substrate 200 is exposed, forms opening 213.
The technique for removing the dummy gate structure 210 is etching technics, such as dry etching, wet etching or dry etching and
The combination of wet etching.
With reference to Fig. 7, boundary layer 240, covering 240 table of boundary layer of covering opening 213 (referring to Fig. 6) bottom and side wall are formed
The gate dielectric layer 241 in face.
The boundary layer 240 is to as the transition zone between semiconductor substrate 200 and gate dielectric layer 241, to solve grid
Dielectric layer 241 is directly and semiconductor substrate 200 combines unstable problem.The material of the boundary layer 240 can be silica,
It may be HfSiO or SiON.The formation process of the boundary layer 240 can be atomic layer deposition (ALD), chemical vapor deposition
(CVD), thermal oxide and nitridation or the combination of the above method.In the present embodiment, the material of the boundary layer 240 is silica, is adopted
Boundary layer 240 is formed with chemical vapor deposition process.
It should be noted that in other embodiments, boundary layer 240 can not be formed, but directly at the bottom of opening 213
Portion and side wall form gate dielectric layer 241.
The material of the gate dielectric layer 241 is high-K gate dielectric material, comprising: HfO2、HfSiO、HfSiON、HfTaO、
HfZrO、Al2O3、ZrO2One of or it is a variety of.The formation process of the gate dielectric layer 241 be atomic layer deposition (ALD), etc. from
Daughter chemical vapor deposition (PECVD), Metalorganic chemical vapor deposition (MOCVD) or plasmaassisted atomic layer deposition
(PECVD) etc..In the embodiment of the present invention, the material of the gate dielectric layer 241 is HfO2, form the gate dielectric layer 241
Method is atomic layer deposition (ALD).
With reference to Fig. 8, first work-function layer 242 on covering 241 surface of gate dielectric layer is formed.
When MOS transistor to be formed is N-type MOS transistor, the material of the first work-function layer 242 is TiN.Described
One work-function layer 242 is formed using chemical vapor deposition or atom layer deposition process, and the parameter by adjusting depositing operation makes
First work-function layer 242 does not have stress or has compression stress.In one embodiment, the first function of PMOS transistor
Function layer 242 has compression stress, the mobility in hole in the channel region of PMOS transistor can be improved, to improve PMOS
The performance of transistor.
TiN is formed using atomic layer deposition, forerunner's reactant is titanium chloride (TiCl4) and ammonia (NH3)。
When MOS transistor to be formed is N-type MOS transistor, the material of the first work-function layer 242 is TiAl.It is described
First work-function layer 242 is formed using chemical vapor deposition or atom layer deposition process, and the parameter by adjusting depositing operation makes
First work-function layer 242 is obtained not have stress or there is tensile stress.In one embodiment, the first of NMOS transistor
Work-function layer 242 has tensile stress, the mobility of the channel region carriers of NMOS transistor can be improved, to improve
The performance of NMOS transistor.
TiAl is formed using atomic layer deposition, forerunner's reactant is titanium chloride (TiCl4) and trimethyl aluminium (Tri methyl
Al, MTA).
First work-function layer 242 with a thickness of 10 angstroms~40 angstroms.
The surface of first work-function layer 242 can also be formed barrier layer (not shown), and the barrier layer is subsequent for stopping
Metallic atom in the gate electrode layer of formation is migrated into the first work-function layer 242 and gate dielectric layer 241.
When MOS transistor to be formed is PMOS transistor, the material of first work-function layer 242 is TiN, TiN
With polycrystalline structure, TiN crystal orientation during subsequent anneal can change, and the first work-function layer 242 locally
Indefinite random change can occur for the crystal orientation of side, so that the work function of the first work-function layer 242 changes.
When MOS transistor to be formed is NMOS transistor, the material of first work-function layer 242 is TiAl,
The aluminium atom of TiAl readily diffuses into other media, so that the work function of the first work-function layer 242 changes.
It is subsequent to carry out the first ion implanting using to the first work-function layer 242, so that the first work-function layer 242 is changed into tool
There is the second work-function layer of stable work function, the work function of the second work-function layer will not change in subsequent annealing, no
It can cause the change of MOS transistor threshold voltage.
With reference to Fig. 9, the first ion implanting 243 is carried out to the first work-function layer 242 (referring to Fig. 8), so that the first work function
Layer 242 is changed into the second work-function layer 244.
Second work-function layer 244 has fixed work function.
After carrying out the first ion implanting 243 to the first work function 242, the first work-function layer 242 is changed into the second work function
Layer 244, and the second work-function layer has fixed work function, in the annealing of subsequent technique, the work content of the second work-function layer 244
The value that number is kept fixed, so that the threshold voltage of MOS transistor will not change.
Second work-function layer 244 with a thickness of 10 angstroms~40 angstroms.
In one embodiment, when MOS transistor to be formed is N-type MOS transistor, the first work-function layer 242
Material is TiN, and the technological parameter of the first ion implanting 243 is carried out to the first work-function layer 242 are as follows: injection ion is silicon ion,
Implantation Energy is 0.5KeV~3KeV, implantation dosage 1E15atom/cm2~5E18atom/cm2, implant angle is 7 degree~20
Degree.
Silicon ion is injected in TiN, TiN is changed into the TiSiN of Silicon-rich, and TiSiN has non crystalline structure, and there is no crystal orientation
Variation, TiSiN will keep work function constant, and will not cause the change of PMOS transistor threshold voltage in subsequent anneal.
In another embodiment, when MOS transistor to be formed is N-type MOS transistor, the first work-function layer 242
Material be TiAl, to the first work-function layer 242 carry out the first ion implanting technological parameter are as follows: injection ion be carbon ion,
Implantation Energy is 0.3KeV~2.5KeV, implantation dosage 1E15atom/cm2~5E18atom/cm2, implant angle be 7 degree~
20 degree.
The carbon ion and aluminium ion of injection form Al-C key, can effectively inhibit the diffusion of aluminium, so that the second work content
There is fixed work function several layers 244, the change of the threshold voltage of NMOS transistor will not be caused.
With reference to Figure 10, the gate electrode layer 245 on covering 244 surface of the second work-function layer is formed.
The gate electrode layer 245 be metal gate electrode layer, the material of the gate electrode layer 245 include Ti, TiW, TiN, Ti,
W, Mo or Ru.In the present embodiment, the material of the gate electrode layer 245 is tungsten.
The forming method of the gate electrode layer 245 is physical vapour deposition (PVD) etc..
Before the gate electrode layer 245 is formed, the barrier layer that can form covering 244 surface of the second work-function layer (is not schemed
Show), the barrier layer forms and then is formed the gate electrode layer 245 for covering the barrier layer.It the barrier layer can be more effective
Barrier metal ion be diffused into the second work-function layer 244.
Barrier layer is deposited on 244 surface of the second work-function layer using the methods of atomic layer deposition, sputtering method.The resistance
The material of barrier includes one of TiN, TaC, TaN, HfN, ZrN or a variety of.
With reference to Figure 11, part interface layer 240, the gate dielectric layer 241, the second work function on 230 surface of interlayer dielectric layer are removed
Layer 244 and gate electrode layer 245, make remaining boundary layer 240, gate dielectric layer 241, the second work-function layer 244 and gate electrode layer 245
It is respectively positioned in opening 213, and is flushed with 230 surface of interlayer dielectric layer.
Remove part interface layer 240, gate dielectric layer 241, the second work-function layer 244 and the grid on 230 surface of interlayer dielectric layer
The method of electrode layer 245 is chemical mechanical grinding (CMP) technique.
In the present embodiment, by above-mentioned part interface layer 240, gate dielectric layer 241, the second work-function layer in same step
244 and gate electrode layer 245 remove, effectively save processing step.
It should be noted that in other embodiments of the invention, can also the above-mentioned interlayer that is located at of step removal several times be situated between
Part interface layer 240, gate dielectric layer 241, the second work-function layer 244 and the gate electrode layer 245 on 230 surface of matter layer, such as formed
The part for being located at 230 surface of interlayer dielectric layer is removed after each layer.
After chemical mechanical grinding boundary layer 240, gate dielectric layer 241, the second work-function layer 244 and gate electrode layer 245
It needs to carry out hydrogen treat, so that the surface of boundary layer 240, gate dielectric layer 241, the second work-function layer 244 and gate electrode layer 245
With good interfacial state.
It is subsequent metal silicide layer (not shown) to be formed on gate electrode layer 245, to reduce metal gate electrode layer
132 contact resistance needs to undergo high annealing during forming metal silicide layer.
A kind of MOS transistor is provided in further embodiment of this invention, the MOS transistor is by above-mentioned MOS transistor
Forming method is formed, comprising: semiconductor substrate；Positioned at the interlayer dielectric layer of the semiconductor substrate surface；Positioned at the interlayer
Opening in dielectric layer and through the interlayer dielectric layer thickness；Cover the gate dielectric layer of the open bottom and side wall；Covering
Second work-function layer on the gate dielectric layer surface, second work-function layer have fixed work function；Cover described second
The gate electrode layer on work-function layer surface, the gate electrode layer are flushed with the inter-level dielectric layer surface.
With reference to Fig. 6 and Figure 11, the MOS transistor includes: semiconductor substrate 200；Positioned at 200 surface of semiconductor substrate
Interlayer dielectric layer 230；Opening 213 in interlayer dielectric layer 230 and through 230 thickness of interlayer dielectric layer；Covering opening 213
The gate dielectric layer 241 of bottom and side wall；Cover second work-function layer 244 on 241 surface of gate dielectric layer, the second work-function layer 244
With fixed work function；Cover the gate electrode layer 245 on 244 surface of the second work-function layer, gate electrode layer 245 and interlayer dielectric layer
230 surfaces flush.
Second work-function layer 244 with a thickness of 10 angstroms~40 angstroms.
When MOS transistor to be formed is PMOS transistor, the material of second work-function layer 244 is TiSiN.Shape
At the method for TiSiN are as follows: depositing titanium nitride material layer first, to titanium nitride material layer carry out the first ion implanting, described first
The technological parameter of ion implanting are as follows: the ion used is 0.5KeV~3KeV for Si ion, Implantation Energy, and implantation dosage is
1E15atom/cm2~5E18atom/cm2, implant angle is 7 degree~20 degree.
TiSiN has non crystalline structure, and the non crystalline structure keeps amorphous state constant in subsequent annealing, does not deposit
Change in crystal orientation, so that the work function that the second work-function layer 244 is kept fixed, will not cause the threshold voltage of PMOS transistor
Change.
When MOS transistor to be formed is NMOS transistor, the material of second work-function layer is TiCAl.It is formed
The method of TiCAl are as follows: depositing titanium nitride material layer first, to titanium nitride material layer carry out the first ion implanting, described first from
The technological parameter of son injection are as follows: the ion used is 0.3KeV~2.5KeV for C ion, Implantation Energy, and implantation dosage is
1E15atom/cm2~5E18atom/cm2, implant angle is 7 degree~20 degree.
The carbon ion and aluminium ion of injection form Al-C key, can effectively inhibit the diffusion of aluminium, so that the second work content
Several layers 244 of work function keeps stablizing, and will not cause the change of the threshold voltage of NMOS transistor.
Since the second work-function layer 244 has fixed work function, what the work function of the second work-function layer 244 was kept fixed
Value, so that the threshold voltage of MOS transistor will not change, improves the performance of MOS transistor.
In conclusion the invention has the following advantages that
The forming method of MOS transistor provided by the invention, due to having carried out the first ion to first work-function layer
Injection, so that first work-function layer is changed into the second work-function layer, so that the second work-function layer in subsequent annealing
Work function will not change, and then not will lead to the change of MOS transistor threshold voltage, improve the performance of MOS transistor.
Further, when MOS transistor to be formed is PMOS transistor, the material of first work-function layer is
TiN carries out the first ion implanting to the first work-function layer, and the ion of first ion implanting is silicon ion, so that the first function
Function is changed into the second work function, and second work function is TiSiN, and TiSiN has non crystalline structure, and there is no the changes of crystal orientation
Change, TiSiN will keep work function constant, and will not cause the change of PMOS transistor threshold voltage in subsequent anneal.
Further, when MOS transistor to be formed is NMOS transistor, the material of first work-function layer is
TiAl carries out the first ion implanting to the first work-function layer, and the ion of first ion implanting is carbon ion, so that the first function
Function is changed into the second work function, and the material of second work-function layer is TiCAl, and carbon ion and aluminium ion form Al-C key,
The diffusion of aluminium can effectively be inhibited, so that the work function of the second work-function layer 244 is kept fixed, NMOS crystal will not be caused
The change of the threshold voltage of pipe.
MOS transistor provided by the invention, since the second work-function layer has fixed work function, second work function
The value that the work function of layer is kept fixed improves MOS transistor so that the threshold voltage of MOS transistor will not change
Performance.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (16)
1. a kind of forming method of MOS transistor characterized by comprising
Semiconductor substrate is provided, the semiconductor substrate surface has interlayer dielectric layer, has in the interlayer dielectric layer and run through
The opening of the interlayer dielectric layer thickness；
Form the gate dielectric layer for covering the open bottom and side wall；
Forming the first work-function layer for covering the gate dielectric layer surface, the MOS transistor is PMOS transistor, described first
The material of work-function layer is TiN, and the MOS transistor is NMOS transistor, and the material of first work-function layer is TiAl；
First ion implanting is carried out to first work-function layer, so that first work-function layer is changed into the second work function
Layer, the MOS transistor are PMOS transistor, carry out the ion that uses of the first ion implanting to the first work-function layer as silicon ion
And second work-function layer has non crystalline structure, the MOS transistor is NMOS transistor, carries out the to the first work-function layer
The ion that one ion implanting uses is that diffusion of the Al-C key to inhibit Al is formed in carbon ion and second work-function layer；
The gate electrode layer on covering second work-function layer surface is formed, the gate electrode layer and the inter-level dielectric layer surface are neat
It is flat.
2. the forming method of MOS transistor according to claim 1, which is characterized in that second work-function layer has
Fixed work function.
3. the forming method of MOS transistor according to claim 1, which is characterized in that form institute using atomic layer deposition
The first work-function layer is stated, forerunner's reactant is titanium chloride and ammonia.
4. the forming method of MOS transistor according to claim 1, which is characterized in that Implantation Energy be 0.5KeV~
3KeV, implantation dosage 1E15atom/cm2~5E18atom/cm2, implant angle is 7 degree~20 degree.
5. the forming method of MOS transistor according to claim 1, which is characterized in that form institute using atomic layer deposition
The first work-function layer is stated, forerunner's reactant is titanium chloride and trimethyl aluminium.
6. the forming method of MOS transistor according to claim 1, which is characterized in that Implantation Energy be 0.3KeV~
2.5KeV, implantation dosage 1E15atom/cm2~5E18atom/cm2, implant angle is 7 degree~20 degree.
7. the forming method of MOS transistor according to claim 1, which is characterized in that the thickness of second work-function layer
Degree is 10 angstroms~40 angstroms.
8. the forming method of MOS transistor according to claim 1, which is characterized in that the MOS transistor is PMOS brilliant
Body pipe, the material of second work-function layer are TiSiN.
9. the forming method of MOS transistor according to claim 1, which is characterized in that the MOS transistor is NMOS brilliant
Body pipe, the material of second work-function layer are TiCAl.
10. the forming method of MOS transistor according to claim 1, which is characterized in that further include: forming the grid
Before dielectric layer, the boundary layer for covering the open bottom and side wall is formed.
11. the forming method of MOS transistor according to claim 10, which is characterized in that the material of the boundary layer is
Silica.
12. the forming method of MOS transistor according to claim 1, which is characterized in that further include: forming the grid
Before electrode layer, the barrier layer for covering second work-function layer is formed.
13. the forming method of MOS transistor according to claim 12, which is characterized in that the material on the barrier layer is
TiN, TaC, TaN, HfN or ZrN.
14. the forming method of MOS transistor according to claim 1, which is characterized in that the gate dielectric layer is high K grid
Dielectric layer, the material of the high-K gate dielectric layer are HfO2、HfSiO、HfSiON、HfTaO、HfZrO、Al2O3Or ZrO2。
15. the forming method of MOS transistor according to claim 1, which is characterized in that the gate electrode layer is metal gate
Electrode layer, the material of the metal gate electrode layer are Ti, TiW, TiN, W, Mo or Ru.
16. according to claim 1 to the MOS transistor that 15 any one are formed characterized by comprising semiconductor substrate；Position
In the interlayer dielectric layer of the semiconductor substrate surface；Opening in the interlayer dielectric layer and through interlayer dielectric layer thickness
Mouthful；Cover the gate dielectric layer of the open bottom and side wall；Cover second work-function layer on the gate dielectric layer surface, described
Two work-function layers have fixed work function；Cover the gate electrode layer on second work-function layer surface, the gate electrode layer with
The inter-level dielectric layer surface flushes.
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