CN106328040A - Gip circuit and its driving method and flat panel display device - Google Patents
Gip circuit and its driving method and flat panel display device Download PDFInfo
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- CN106328040A CN106328040A CN201610967567.5A CN201610967567A CN106328040A CN 106328040 A CN106328040 A CN 106328040A CN 201610967567 A CN201610967567 A CN 201610967567A CN 106328040 A CN106328040 A CN 106328040A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The invention discloses a GIP circuit and its driving method and the flat panel display device, which respectively provides initial signals to the driver element of GIP circuit so that the scanning signals of the driver elements are mutually independent.The invention has the advantage of avoiding the abnormal condition due to the abnormality of a certain level signals thereby improving the reliability of the flat panel display device.
Description
Technical field
The present invention relates to technical field of flat panel display, particularly to a kind of GIP circuit and driving method thereof and flat pannel display
Device.
Background technology
In recent years, along with fast development and the application of information technology, radio mobile communication and information household appliances, people are to electronics
The dependency of product grows with each passing day, and more brings the flourish of various Display Technique and display device.Panel display apparatus has
Fully planarize, the feature such as light, thin, power saving, be therefore widely used.
At present, the purpose of narrow frame is realized in order to reduce the manufacturing cost of panel display apparatus using, in manufacture process
In generally use GIP (Gate in Panel, door face board) technology, directly gate driver circuit (i.e. GIP circuit) is integrated in flat
On plate display floater.Panel display board generally includes for showing the viewing area of image and non-display around viewing area
Region, described GIP circuit is generally positioned in non-display area.
Refer to Fig. 1, it is the part-structure schematic diagram of panel display board of prior art.As it is shown in figure 1, it is existing
Panel display board 100 includes multiple pixel (not shown), multi-strip scanning line (S1 to Sn) and GIP arranged in matrix
Circuit (not shown), described GIP circuit is used for producing multilevel scanning signal, and the 1st grade of scanning signal is supplied to the 1st row pixel
Scan line, the 2nd grade of scanning signal is supplied to the scan line of the 2nd row pixel, and so on, n-th grade of scanning signal is supplied to n-th
The scan line of row pixel.
Owing to multiple pixels of described panel display board 100 are all that the scanning signal provided according to scan line gates
, the whether normal display effect that all can directly affect panel display board of scanning signals the most at different levels.Once certain one-level scanning
Signal occurs abnormal, just cannot gate the pixel of correspondence, and described panel display board 100 arises that screen body does not works, shields body
The display of certain a line is abnormal or screen body front portion picture shows normally rear portion picture display these abnormal conditions abnormal.
Refer to Fig. 2, it is the part-structure schematic diagram of GIP circuit of prior art.As in figure 2 it is shown, existing GIP is electric
Road 10 includes first grid polar curve VGH, second gate line VGL, the first clock cable XCK, second clock holding wire CK and many
The individual driver element being sequentially connected with, every grade of driver element include the first transistor T1, transistor seconds T2, third transistor T3,
4th transistor T4 and the 5th transistor T5, the grid of described the first transistor T1 and third transistor T3 is all believed with the first clock
Number line XCK connects, and the drain electrode of described transistor seconds T2 is connected with second clock holding wire CK, the grid of described transistor seconds T2
Pole is connected with the drain electrode of described the first transistor T1, described 4th transistor T4 drain electrode and the 5th transistor T5 source electrode all with
First grid polar curve VGH connects, and the drain electrode of described third transistor T3 is connected with second gate line VGL, described third transistor T3
Source electrode and grid all drain electrodes with the 5th transistor of the 4th transistor T4 be connected, the source electrode of described transistor seconds T2,
The source electrode of four transistor T4 and the grid of the 5th transistor T5 are all connected with an output signal line SCAN, described the first transistor T1
Source electrode and an input signal cable SIN connect.
In described GIP circuit 10, n-th grade of driver element receives n-th grade of input signal by input signal cable SIN, and n-th
Level driver element by output signal line SCAN to scan line output n-th grade of output signal while, described n-th grade of output signal
Input signal as (n+1)th grade of driver element is input to (n+1)th grade of driver element.Owing to the scanning signal of upper level is generally made
For the input of next stage scanning signal, it not separate between scanning signals the most at different levels.When certain one-level scanning signal goes out
Now abnormal, the scanning signal input that can cause its next stage is abnormal so that its follow-up all scanning abnormal signals, shows to flat board
Show bring the worst.
As can be seen here, the reliability of GIP circuit will directly affect the display effect of panel display apparatus.But, in reality
Manufacture and use during find, in existing panel display apparatus, the reliability of GIP circuit is relatively low, it is impossible to meet market need
Want.
Base this, how to solve the problem that in existing panel display apparatus, the reliability of GIP circuit is low, become this area skill
The technical problem that art personnel are urgently to be resolved hurrily.
Summary of the invention
It is an object of the invention to provide a kind of GIP circuit and driving method thereof and panel display apparatus, existing to solve
The problem that in technology middle plateform display device, the reliability of GIP circuit is low.
For solving the problems referred to above, the present invention provides a kind of GIP circuit, and described GIP circuit includes: first grid polar curve, second
Gate line, the first clock cable, second clock holding wire and multiple drive power unit, every grade of driver element includes five crystal
Pipe and two capacitors；
Wherein, the grid of the first transistor, transistor seconds and third transistor is all connected with a control line, first crystal
Pipe, the first electrode of transistor seconds and third transistor are all connected with first grid polar curve, the first electrode of the 4th transistor and
Second gate line connects, the second electrode of the first transistor and one end of the first capacitor C1 all with the grid of the 4th transistor
Connect, the grid of transistor seconds and the second electrode of the 4th transistor and the 5th transistor all with one end of the second capacitor
Connecting, the other end of third transistor and the second electrode of the 5th transistor and the second capacitor is all with an output signal line even
Connect；
In the driver element that ordinal number is odd number, the first electrode of the 5th transistor and the first clock cable connect, the
The other end of one capacitor is connected with second clock holding wire；
In the driver element that ordinal number is even number, the first electrode of the 5th transistor is connected with second clock holding wire, the
The other end of one capacitor and the first clock cable connect.
Optionally, in described GIP circuit, the signal that described first grid polar curve provides always remains as high level, institute
The signal that stating second gate line provides always remains as low level.
Optionally, in described GIP circuit, described first clock cable is for providing first for described GIP circuit
Clock signal, described second clock holding wire is for providing second clock signal for described GIP circuit.
Optionally, in described GIP circuit, described control line is for providing initial signal for described driver element.
Optionally, in described GIP circuit, the conducting of described the first transistor, transistor seconds and third transistor
Controlling by the initial signal of described control line with cut-off, the conducting of described 4th transistor and cut-off are by described first capacitor
The control of Electric potentials of one end, the conducting of described 5th transistor and cut-off are by the control of Electric potentials of one end of described second capacitor.
Optionally, in described GIP circuit, described the first transistor is P-type TFT to the 5th transistor.
Accordingly, present invention also offers the driving method of a kind of GIP circuit, the driving method of described GIP circuit includes:
Scan period includes first time period, the second time period, the 3rd time period and the 4th time period；Wherein,
In first time period, the first clock signal that the first clock cable provides is become low level from high level, and second
The second clock signal that clock cable provides remains high level, and the first initial signal that the first control line provides is low electricity
Flat, open the first transistor of first order driver element to third transistor, the 4th transistor of closedown first order driver element
With the 5th transistor；
In the second time period, the first clock signal that the first clock cable provides remains high level, and second clock is believed
The second clock signal that number line provides is become low level from high level, and the first initial signal that the first control line provides is by low level
Become high level, close the first transistor of first order driver element to third transistor, open the of first order driver element
Four transistors and the 5th transistor；
In the 3rd time period, the first clock signal that the first clock cable provides is become low level from high level, and second
The second clock signal that clock cable provides is become high level from low level, and the first initial signal that the first control line provides is protected
Hold as high level, the 4th transistor of closedown first order driver element；
In the 4th time period, the first clock signal that the first clock cable provides remains high level, and second clock is believed
The second clock signal that number line provides is become low level from high level, and the first initial signal that the first control line provides is by high level
Become low level, open the first transistor of first order driver element to third transistor, close the of first order driver element
Four transistors and the 5th transistor.
Optionally, in the driving method of described GIP circuit, first time period, the second of the second control line offer
Initial signal is low level, and the first transistor opening second level driver element drives single to third transistor, the closedown second level
4th transistor of unit and the 5th transistor；
In the second time period, the second initial signal that the second control line provides remains low level, continues to open the second level
The first transistor of driver element, to third transistor, continues to close the 4th transistor and the 5th crystal of second level driver element
Pipe；
In the 3rd time period, the second initial signal that the second control line provides is become high level from low level, closes second
The first transistor of level driver element, to third transistor, opens the 4th transistor and the 5th crystal of second level driver element
Pipe；
In the 4th time period, the second initial signal that the second control line provides remains high level, continues to close the second level
The first transistor of driver element, to third transistor, simultaneously closes off the 4th transistor of second level driver element.
Accordingly, present invention also offers a kind of panel display apparatus, described panel display apparatus includes as above
GIP circuit.
Optionally, in described panel display apparatus, described panel display apparatus is OLED, liquid crystal
Showing device, plasm display device, vacuum fluorescent display device or flexible display apparatus.
In sum, in the GIP circuit provided in the present invention and driving method and panel display apparatus, by GIP
The driver elements at different levels of circuit provide initial signal respectively so that between the scanning signal of driver elements at different levels output the most solely
Vertical, to avoid certain one-level abnormal signal to cause the situation of follow-up signal exception, thus improve the reliability of panel display apparatus.
Accompanying drawing explanation
Fig. 1 is the part-structure schematic diagram of the panel display board of prior art；
Fig. 2 is the part-structure schematic diagram of the GIP circuit of prior art；
Fig. 3 is the part-structure schematic diagram of the GIP circuit of the embodiment of the present invention；
Fig. 4 is the sequential chart of the driving method of the GIP circuit of the embodiment of the present invention.
Detailed description of the invention
Below in conjunction with the drawings and specific embodiments, the present invention proposed a kind of GIP circuit and driving method thereof and flat pannel display
Device is described in further detail.According to following explanation and claims, advantages and features of the invention will be apparent from.Need
Bright, accompanying drawing all uses the form simplified very much and all uses non-ratio accurately, only in order to facilitate, to aid in illustrating lucidly
The purpose of the embodiment of the present invention.
Refer to Fig. 3, it is the part-structure schematic diagram of GIP circuit of the embodiment of the present invention.As it is shown on figure 3, described GIP
Circuit 20 includes: first grid polar curve VGH, second gate line VGL, the first clock cable XCK, second clock holding wire CK and
Multiple drive power unit；Every grade of driver element includes five transistors and two capacitors, wherein, the first transistor T1, the second crystalline substance
The grid of body pipe T2 and third transistor T3 is all connected with a control line, the first transistor T1, transistor seconds T2 and trimorphism
First electrode of body pipe T3 is all connected with first grid polar curve VGH, and first electrode of the 4th transistor T4 is with second gate line VGL even
Connecing, second electrode of the first transistor T1 and one end of the first capacitor C1 all grids with the 4th transistor T4 are connected, and
The grid of two-transistor T2 and second electrode of the 4th transistor T4 and the 5th transistor T5 all with the one of the second capacitor C2
End connects, and the other end of third transistor and second electrode of the 5th transistor T5 and the second capacitor C2 is all believed with an output
Number line connects；In the driver element that ordinal number is odd number, first electrode of the 5th transistor T5 and the first clock cable XCK are even
Connecing, the other end of the first capacitor C1 is connected with second clock holding wire CK；In the driver element that ordinal number is even number, the 5th is brilliant
First electrode of body pipe T5 is connected with second clock holding wire CK, the other end of the first capacitor C1 and the first clock cable
XCK connects.
Concrete, the first electrode and the second electrode are different electrodes.Such as, when the first electrode is arranged to source electrode,
Second electrode is arranged to drain electrode.
Please continue to refer to Fig. 3, every grade of driver element of described GIP circuit 20 respectively with first grid polar curve VGH, second grid
Line VGL, the first clock cable XCK, second clock holding wire CK and control line connect.Wherein, described first clock signal
Line XCK is for providing the first clock signal for described GIP circuit 20, and described second clock holding wire CK is for electric for described GIP
Road 20 provides second clock signal, and described control line (EM1, EM2------EMn) is used for providing initial signal for driver element,
The signal that described first grid polar curve VGH provides always remains as high level, and the signal that second gate line VGL provides always remains as
Low level.
Wherein, the initial signal of the 1st grade of driver element is provided by the first control line EM1, and the 1st grade of driver element is by output
Holding wire Scan1 exports the 1st grade of scanning signal, and the initial signal of the 2nd grade of driver element is provided by the second control line EM2, the 2nd grade
Driver element exports the 2nd grade of scanning signal by output signal line Scan2.By that analogy, the initial signal of n-th grade of driver element
Being thered is provided by n-th grade of control line EMn, n-th grade of driver element exports n-th grade of scanning signal by output signal line Scan n.Wherein,
N is positive integer.
Please continue to refer to Fig. 3, the first transistor M1, transistor seconds M2 and third transistor M3 in the 1st grade of driver element
Conducting and cut-off by first control line EM1 provide first initial signal control, the first transistor in the 2nd grade of driver element
The second initial signal that M1, transistor seconds M2 and the conducting of third transistor M3 and cut-off are provided by the second control line EM2
Control.By that analogy, in n-th grade of driver element the first transistor M1, transistor seconds M2 and the conducting of third transistor M3 and
The n-th initial signal that ending is provided by the n-th control line EMn controls.
Please continue to refer to Fig. 3, in the 1st grade of driver element, the conducting of the 4th transistor M4 and cut-off are by its first capacitor C1
The control of Electric potentials of one end, the conducting of the 5th transistor M5 and cut-off are by the control of Electric potentials of one end of its second capacitor C2.With
Sample, in the 2nd grade of driver element, the conducting of the 4th transistor M4 and cut-off are by the control of Electric potentials of one end of its first capacitor C1,
The conducting of the 5th transistor M5 and cut-off are by the control of Electric potentials of one end of its second capacitor C2.By that analogy, n-th grade drives single
In unit, the conducting of the 4th transistor M4 and cut-off are by the control of Electric potentials of one end of its first capacitor C1, and the 5th transistor M5 leads
Lead to and cut-off is by the control of Electric potentials of one end of its second capacitor C2.
Preferably, described the first transistor M1 to the 5th transistor M5 is thin film transistor (TFT).Described the first transistor M1
P-type TFT can be selected, it is also possible to select N-type TFT to the 5th transistor M5.Known, p-type thin film is brilliant
Body pipe turns on when signal is low level bit, and N-type TFT turns on when signal is high level position.Therefore,
As long as the transistor types of selection is matched with conducting current potential.
In the present embodiment, described the first transistor M1 to the 5th transistor M5 is P-type TFT.The present embodiment
In, the initial signal that the driver elements at different levels of described GIP circuit 20 are provided by corresponding control line respectively, thus driver sweep letter
Number, the input of the outfan of previous stage driver element and rear stage driver element is also not connected to, and between scanning signals at different levels is
Separate.Therefore, even if certain one-level scanning signal occurs abnormal, the scanning signal of its next stage is also unaffected.
Accordingly, the present invention also provides for the driving method of a kind of GIP circuit.Incorporated by reference to reference to Fig. 3 and Fig. 4, described GIP electricity
The driving method on road includes: when the scan period includes first time period t1, the second time period t the 2, the 3rd time period t 3 and the 4th
Between section t4；Wherein,
In first time period t1, the first clock signal that the first clock cable XCK provides is become low level from high level,
The second clock signal that second clock holding wire CK provides remains high level, the first initial letter that the first control line EM1 provides
Number and the second control line EM2 provide the second initial signal all remain low level, open the first transistor T1 to the 3rd crystal
Pipe T3, closes the 4th transistor T4 and the 5th transistor T5；
In the second time period t 2, the first clock signal that the first clock cable XCK provides remains high level, when second
The second clock signal that clock holding wire CK provides is become low level from high level, the first initial letter that the first control line EM1 provides
Number being become high level from low level, the second initial signal that the second control line EM2 provides remains low level, closes first crystal
Pipe T1, to third transistor T3, opens the 4th transistor T4 and the 5th transistor T5；
In the 3rd time period t 3, the first clock signal that the first clock cable XCK provides is become low level from high level,
The second clock signal that second clock holding wire CK provides is become high level from low level, the first of the first control line EM1 offer
Initial signal remains high level, and the second initial signal that the second control line EM2 provides is become high level from low level, closes the
Four transistor T4；
In the 4th time period t 4, the first clock signal that the first clock cable XCK provides remains high level, when second
The second clock signal that clock holding wire CK provides is become low level from high level, the first initial letter that the first control line EM1 provides
Number being become low level from high level, the second initial signal that the second control line EM2 provides remains high level, opens first crystal
Pipe T1, to third transistor T3, closes the 4th transistor T4 and the 5th transistor T5.
Concrete, for first order driver element, in first time period t1, due to the first control line EM1 offer
First initial signal remains low level, the first transistor T1, the transistor seconds T2 and the 3rd controlled by the first initial signal
Transistor T3 is in conducting state, and the 4th transistor T4 and the 5th transistor T5 is brilliant by the first transistor T1 and second respectively
Body pipe T2 is connected to first grid polar curve VGH, and therefore the 4th transistor T4 and the 5th transistor T5 remains cut-off.Now, output
Holding wire Scan1 is connected to first grid polar curve VGH, the therefore scanning of output signal line Scan1 output by third transistor T3
Signal is high level.
In the second time period t 2, the first initial signal provided due to the first control line EM1 is become high level from low level,
The first transistor T1, transistor seconds T2 and third transistor T3 that are controlled by the first initial signal are become cut-off by conducting.
Simultaneously as the second clock signal that second clock holding wire CK provides is become low level from high level, the 4th transistor T4's
Grid skips to low level under the coupling of the first capacitor C1, and the 4th transistor T4 is become conducting from cut-off, and therefore second
Capacitor C2 starts electric discharge, and the grid potential of the 5th transistor T5 declines, and then the 5th transistor T5 is also become from cut-off
Conducting.Now, output signal line Scan1 is connected to the first clock cable XCK by the 5th transistor T5.Due to the first clock
The first clock signal that holding wire XCK provides remains high level, and therefore the scanning signal of output signal line Scan1 output keeps
For high level.
In the 3rd time period t 3, the second clock signal provided due to second clock holding wire CK is become high electricity from low level
Flat, the grid of the 4th transistor T4 skips to high level under the coupling of the first capacitor C1, therefore the 4th transistor T4 by
Conducting becomes cut-off, simultaneously as the first clock signal that the first clock cable XCK provides is become low level from high level,
Therefore the scanning signal of output signal line Scan1 output is become low level from high level.
In the 4th time period t 4, the first initial signal provided due to the first control line EM1 is become low level from high level,
The first transistor T1, transistor seconds T2 and third transistor T3 that are controlled by the first initial signal are become conducting by cut-off.
Meanwhile, the 4th transistor T4 and the 5th transistor T5 is connected to the first grid by the first transistor T1 and transistor seconds T2 respectively
Polar curve VGH, therefore the 4th transistor T4 and the 5th transistor T5 remains cut-off.Now, output signal line passes through the 3rd crystal
Pipe T3 is connected to first grid polar curve VGH, and therefore the scanning signal of output signal line Scan1 output is high level.
Visible, the first initial signal is low level in first time period t1 and the 4th time period t 4, in the second time period t 2
Being high level with the 3rd time period t 3, the scanning signal of the output signal line Scan1 output of first order driver element is when first
Between section t1, the second time period t 2 and the 4th time period t 4 are high level, are low level in the 3rd time period t 3.
For at second level driver element, in first time period t1, due to second of the second control line EM2 offer
Beginning signal remains low level, the first transistor T1, transistor seconds T2 and the third transistor controlled by the first initial signal
T3 is in conducting state, and the 4th transistor T4 and the 5th transistor T5 is respectively by the first transistor T1 and transistor seconds T2
Being connected to first grid polar curve VGH, therefore the 4th transistor T4 and the 5th transistor T5 remains cut-off.Now, output signal line
Scan2 is connected to first grid polar curve VGH by third transistor T3, and therefore the scanning signal of output signal line Scan2 output is
High level.
In the second time period t 2, the second initial signal provided due to the second control line EM2 continues to keep low level, by the
The first transistor T1, transistor seconds T2 and third transistor T3 that one initial signal controls are still in conducting state, and the 4th is brilliant
Body pipe T4 and the 5th transistor T5 is connected to first grid polar curve VGH by the first transistor T1 and transistor seconds T2 respectively, because of
This 4th transistor T4 and the 5th transistor T5 keeps cut-off state, and output signal line Scan2 is continued by third transistor T3
Being connected to first grid polar curve VGH, therefore the scanning signal of output signal line Scan2 output remains high level.
In the 3rd time period t 3, the second initial signal provided due to the second control line EM2 is become high level from low level,
The first transistor T1, transistor seconds T2 and third transistor T3 that are controlled by the second initial signal are become cut-off by conducting.
Simultaneously as the first clock signal that the first clock cable XCK provides is become low level from high level, the 4th transistor T4's
Grid skips to low level under the coupling of the first capacitor C1, and the 4th transistor T4 is become conducting from cut-off, and therefore second
Capacitor C2 starts electric discharge, and the grid potential of the 5th transistor T5 declines, and then the 5th transistor T5 is also become from cut-off
Conducting.Now, output signal line Scan2 is connected to second clock holding wire CK by the 5th transistor T5.Due to second clock
The second clock signal that holding wire CK provides remains high level, and therefore the scanning signal of output signal line Scan2 output keeps
For high level.
In the 4th time period t 4, the first clock signal provided due to the first clock cable XCK is become high from low level
Level, the grid of the 4th transistor T4 skips to high level under the coupling of the first capacitor C1, therefore the 4th transistor T4
Cut-off is become from conducting, simultaneously as the second clock signal that second clock holding wire CK provides is become low level from high level,
Therefore the scanning signal of output signal line Scan2 output is become low level from high level.
Visible, the second initial signal is low level in first time period t1 and the second time period t 2, in the 3rd time period t 3
Being high level with the 4th time period t 4, the scanning signal of the output signal line Scan2 output of second level driver element is when first
Between section t1, the second time period t 2 and the 3rd time period t 3 are high level, are low level in the 4th time period t 4.
The most only as a example by driving GIP circuit to export scan signal and the second scanning signal, drive the output of GIP circuit
Other scanning signals are similar to therewith, do not repeat at this.
Accordingly, the present invention also provides for a kind of panel display apparatus.Described panel display apparatus includes GIP as above
Circuit 20.Specifically refer to above, here is omitted.
The panel display apparatus that the present embodiment provides is owing to using GIP circuit 20 as above, and reliability is higher.Its
In, described panel display apparatus can be that liquid crystal display (LCD) device, plasma show that (PDP) device, vacuum fluorescence show
(VFD) device, organic light emitting display (OLED) device, flexible display apparatus or other kinds of display device, particular type
This is not restricted.
To sum up, in the GIP circuit provided in the embodiment of the present invention and driving method and panel display apparatus, by
The driver elements at different levels of GIP circuit provide initial signal respectively so that between the scanning signal of driver elements at different levels output mutually
Independent, to avoid certain one-level abnormal signal to cause the situation of follow-up signal exception, thus improve the reliable of panel display apparatus
Property.
Foregoing description is only the description to present pre-ferred embodiments, not any restriction to the scope of the invention, this
Any change that the those of ordinary skill in bright field does according to the disclosure above content, modification, belong to the protection of claims
Scope.
Claims (10)
1. a GIP circuit, it is characterised in that including: first grid polar curve, second gate line, the first clock cable, second time
Clock holding wire and multiple drive power unit, every grade of driver element includes five transistors, two capacitors and a control line；
Wherein, the grid of the first transistor, transistor seconds and third transistor is all connected with described control line, first crystal
Pipe, the first electrode of transistor seconds and third transistor are all connected with first grid polar curve, the first electrode of the 4th transistor and
Second gate line connects, the second electrode of the first transistor and one end of the first capacitor all with the grid of the 4th transistor company
Connecing, the grid of transistor seconds and the second electrode of the 4th transistor and the 5th transistor is all with one end of the second capacitor even
Connecing, the other end of third transistor and the second electrode of the 5th transistor and the second capacitor is all with an output signal line even
Connect；
In the driver element that ordinal number is odd number, the first electrode of the 5th transistor and the first clock cable connect, the first electricity
The other end of container is connected with second clock holding wire；
In the driver element that ordinal number is even number, the first electrode of the 5th transistor is connected with second clock holding wire, the first electricity
The other end of container and the first clock cable connect.
2. GIP circuit as claimed in claim 1, it is characterised in that the signal that described first grid polar curve provides always remains as
High level, the signal that described second gate line provides always remains as low level.
3. GIP circuit as claimed in claim 1, it is characterised in that described first clock cable is used for as described GIP circuit
Thering is provided the first clock signal, described second clock holding wire is for providing second clock signal for described GIP circuit.
4. GIP circuit as claimed in claim 1, it is characterised in that described control line is for providing for described driver element
Beginning signal.
5. GIP circuit as claimed in claim 4, it is characterised in that described the first transistor, transistor seconds and the 3rd crystal
The conducting of pipe and cut-off are controlled by the initial signal of described control line, and the conducting of described 4th transistor and cut-off are by described the
The control of Electric potentials of one end of one capacitor, the conducting of described 5th transistor and cut-off are by the electricity of one end of described second capacitor
Position controls.
6. GIP circuit as claimed in claim 1, it is characterised in that it is thin that described the first transistor to the 5th transistor is p-type
Film transistor.
7. the driving method of the GIP circuit as according to any one of claim 1 to 6, it is characterised in that the scan period wraps
Include first time period, the second time period, the 3rd time period and the 4th time period；Wherein,
In first time period, the first clock signal that the first clock cable provides is become low level, second clock from high level
The second clock signal that holding wire provides remains high level, and the first initial signal that the first control line provides is low level, beats
Open the first transistor of first order driver element to third transistor, the 4th transistor and the 5th of closedown first order driver element
Transistor；
In the second time period, the first clock signal that the first clock cable provides remains high level, second clock holding wire
The second clock signal provided is become low level from high level, and the first initial signal that the first control line provides is become from low level
High level, the first transistor of closedown first order driver element to third transistor, open the 4th crystalline substance of first order driver element
Body pipe and the 5th transistor；
In the 3rd time period, the first clock signal that the first clock cable provides is become low level, second clock from high level
The second clock signal that holding wire provides is become high level from low level, and the first initial signal that the first control line provides remains
High level, closes the 4th transistor of first order driver element；
In the 4th time period, the first clock signal that the first clock cable provides remains high level, second clock holding wire
The second clock signal provided is become low level from high level, and the first initial signal that the first control line provides is become from high level
Low level, opens the first transistor of first order driver element to third transistor, the 4th crystalline substance of closedown first order driver element
Body pipe and the 5th transistor.
8. the driving method of GIP circuit as claimed in claim 7, it is characterised in that in first time period, the second control line carries
Second initial signal of confession is low level, opens the first transistor of second level driver element to third transistor, closedown second
4th transistor of level driver element and the 5th transistor；
In the second time period, the second initial signal that the second control line provides remains low level, continues to open the second level and drives
The first transistor of unit, to third transistor, continues to close the 4th transistor and the 5th transistor of second level driver element；
In the 3rd time period, the second initial signal that the second control line provides is become high level from low level, closes the second level and drives
The first transistor of moving cell, to third transistor, opens the 4th transistor and the 5th transistor of second level driver element；
In the 4th time period, the second initial signal that the second control line provides remains high level, continues to close the second level and drives
The first transistor of unit, to third transistor, simultaneously closes off the 4th transistor of second level driver element.
9. a panel display apparatus, it is characterised in that include the GIP circuit as according to any one of claim 1 to 6.
10. panel display apparatus as claimed in claim 9, it is characterised in that described panel display apparatus is that organic light emission shows
Show device, liquid crystal indicator, plasm display device, vacuum fluorescent display device or flexible display apparatus.
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| CN201610967567.5A CN106328040B (en) | 2016-10-31 | 2016-10-31 | GIP circuit and its driving method and panel display apparatus |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023245602A1 (en) * | 2022-06-24 | 2023-12-28 | 京东方科技集团股份有限公司 | Driving circuit, driving method, display apparatus and display control method |
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| CN101227188A (en) * | 2006-08-08 | 2008-07-23 | 三星Sdi株式会社 | Logic gate, scan driver and organic light emitting diode display using the same |
| CN102760410A (en) * | 2012-06-14 | 2012-10-31 | 友达光电股份有限公司 | Scanning driving device and driving signal generating method thereof |
| US20130235006A1 (en) * | 2012-03-12 | 2013-09-12 | Samsung Display Co., Ltd. | Method of driving a display panel and display apparatus for performing the same |
| CN104464642A (en) * | 2014-12-30 | 2015-03-25 | 昆山国显光电有限公司 | GIP circuit, driving method of GIP circuit and display panel |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101227188A (en) * | 2006-08-08 | 2008-07-23 | 三星Sdi株式会社 | Logic gate, scan driver and organic light emitting diode display using the same |
| US20130235006A1 (en) * | 2012-03-12 | 2013-09-12 | Samsung Display Co., Ltd. | Method of driving a display panel and display apparatus for performing the same |
| CN102760410A (en) * | 2012-06-14 | 2012-10-31 | 友达光电股份有限公司 | Scanning driving device and driving signal generating method thereof |
| CN104464642A (en) * | 2014-12-30 | 2015-03-25 | 昆山国显光电有限公司 | GIP circuit, driving method of GIP circuit and display panel |
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| WO2023245602A1 (en) * | 2022-06-24 | 2023-12-28 | 京东方科技集团股份有限公司 | Driving circuit, driving method, display apparatus and display control method |
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| CN106328040B (en) | 2019-06-28 |
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