CN106326781A - Method and device for protecting chip testing mode - Google Patents
Method and device for protecting chip testing mode Download PDFInfo
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- CN106326781A CN106326781A CN201610703536.9A CN201610703536A CN106326781A CN 106326781 A CN106326781 A CN 106326781A CN 201610703536 A CN201610703536 A CN 201610703536A CN 106326781 A CN106326781 A CN 106326781A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/77—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in smart cards
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
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Abstract
The invention discloses a method for protecting a chip testing mode. The method comprises: when carrying out initialization before testing on a chip, taking a bit string of a pre-set storage position of an electronic programmable fuse E-fuse module in the chip as a protection code; after the initialization before the testing on the chip is finished, reading the protection code from the pre-set storage position of the E-fuse module; when the protection code is not 0, prohibiting the chip from entering the testing mode; when the protection code is 0, allowing the chip to enter the testing mode; if the chip is prohibited from entering the testing mode at the next time, changing the protection code. The method provided by the invention can prevent an attacker from entering the chip testing mode.
Description
Technical field
The present invention relates to chip testing technology field, a kind of method protecting chip test mode and dress
Put.
Background technology
Chip the most all can have a test pattern, and this checking chip during manufacturing chip is used, and is used for
Chip on wafer or after encapsulation performs used by close beta program.Test pattern often allow to use those chip is actual should
The access type strictly forbidden in.Additionally, such as scan chain such test circuit, can make engineer after taking chip
The buffer status of chip internal is controlled, is thus easy to read the data of chip internal.But to chip detection
For, these are again inevitable.Therefore, after chip dispatches from the factory, be necessary for forbidding chip from mode of operation to test pattern
Conversion.
In order to prevent disabled user from entering into test pattern, the holding wire that control chip generally enters test pattern is put into
In scribe line, after chip completes test, encapsulating chip when, by scribing, this holding wire is drawn disconnected, make the chip cannot be again
Enter into test pattern.
Along with developing rapidly of the attack means to intelligent card chip, assailant can navigate to fuse in scribe line
(fuse) position, recycling focused particle beam (Focused Ion beam, FIB) technology reconnects and is drawn disconnected signal
Line, makes chip be again introduced into test pattern, thus obtains the important information in chip.
Therefore, after chip package, how to limit entrance chip test mode, be the problem needing to solve.
Summary of the invention
The technical problem to be solved is to provide a kind of method and apparatus protecting chip test mode, it is possible to anti-
Only assailant enters the test pattern of chip.
The embodiment of the present invention provides a kind of method protecting chip test mode, and the method includes:
During initialization before chip is tested, pre-by the electronic programmable fuse E-fuse module in described chip
Surely the bit bit string of position is stored as protected code；
After initialization before described chip completes test, read described from the predetermined storage location of described E-fuse module
Protected code；When described protected code is not 0, forbid that described chip enters test pattern；When described protected code is 0, it is allowed to institute
State chip and enter test pattern, if chip to be forbidden enters test pattern next time, then change described protected code.
The embodiment of the present invention also provides for a kind of method protecting chip test mode, and the method includes:
During initialization before chip is tested, by of the electronic programmable fuse E-fuse module in described chip
The bit bit string of one storage position is as protected code, at the second storage position write key of described E-fuse module, described
3rd storage position of E-fuse module writes the first ciphertext；
After initialization before described chip completes test, read described from the first storage position of described E-fuse module
Protected code；When described protected code is not 0, forbid that described chip enters test pattern；When described protected code is 0, from described
Described key is read in second storage position of E-fuse module, reads described the from the 3rd of described E-fuse module storage position
One ciphertext, reads in plain text in other memory modules from described chip, utilizes to be encrypted in plain text described in described double secret key and obtains
Obtain the second ciphertext；If described second ciphertext differs with described first ciphertext, then forbid that described chip enters test pattern；As
The most described second ciphertext is identical with described first ciphertext, then allow described chip to enter test pattern, if under chip to be forbidden
Secondary entrance test pattern, then change described protected code, or, change described protected code and described key.
The embodiment of the present invention also provides for a kind of device protecting chip test mode, including:
Initialization module, when being used for the initialization before chip is tested, melts the electronic programmable in described chip
The bit bit string of the predetermined storage location of silk E-fuse module is as protected code；
Test pattern judge module, after the initialization before completing test at described chip, from described E-fuse module
Predetermined storage location read described protected code；When described protected code is not 0, forbid that described chip enters test pattern；?
When described protected code is 0, it is allowed to described chip enters test pattern, if chip to be forbidden enters test pattern, the most more next time
Change described protected code.
The embodiment of the present invention also provides for a kind of device protecting chip test mode, including:
Initialization module, when being used for the initialization before chip is tested, melts the electronic programmable in described chip
The bit bit string of the first storage position of silk E-fuse module is as protected code, in the second storage position of described E-fuse module
Write key, writes the first ciphertext in the 3rd storage position of described E-fuse module；
Test pattern judge module, after the initialization before completing test at described chip, from described E-fuse module
First storage position read described protected code；When described protected code is not 0, forbid that described chip enters test pattern；?
When described protected code is 0, read described key, from described E-fuse module from the second storage position of described E-fuse module
Described first ciphertext is read in 3rd storage position, reads in plain text, utilize described close in other memory modules from described chip
Key is encrypted acquisition the second ciphertext to described plaintext；If described second ciphertext differs with described first ciphertext, then forbid
Described chip enters test pattern；If described second ciphertext is identical with described first ciphertext, then allows described chip to enter and survey
Die trial formula, if chip to be forbidden enters test pattern next time, then changes described protected code, or, change described protected code also
And change described key.
Compared with prior art, a kind of method and apparatus protecting chip test mode that the present invention provides, enters at chip
Row test before initialization time, by the bit of the predetermined storage location of the electronic programmable fuse E-fuse module in described chip
Bit string, as protected code, after the initialization before chip completes test, when described protected code is not 0, forbids that described chip enters
Enter test pattern；When described protected code is 0, it is allowed to described chip enters test pattern, if chip to be forbidden enters next time
Test pattern, then change described protected code.Owing to E-fuse module is integrated in chip internal, assailant is difficult to navigate to its position
Putting, and utilize the bit in E-fuse module once to be changed into 1 by 0, the feature that cannot change 0 again into is provided with protected code,
Or protected code, key and ciphertext, by the test pattern of multiple protective chip, prevent assailant from entering the test mould of chip
Formula.
Accompanying drawing explanation
Fig. 1 is a kind of method flow diagram protecting chip test mode in the embodiment of the present invention.
Fig. 2 is the method flow diagram of another kind of protection chip test mode in the embodiment of the present invention.
Fig. 3 is a kind of device schematic diagram protecting chip test mode in the embodiment of the present invention.
Fig. 4 is the device schematic diagram of another kind of protection chip test mode in the embodiment of the present invention.
Fig. 5 is the method flow diagram protecting chip test mode in example 1 of the present invention.
Fig. 6 is the method flow diagram protecting chip test mode in example 2 of the present invention.
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing to the present invention
Embodiment be described in detail.It should be noted that in the case of not conflicting, in embodiment in the application and embodiment
Feature can mutual combination in any.
E-fuse (electronic programmable fuse) is a kind of non-volatile memory cells, can be programmed by fuse on chip
And store information.The feature of E-fuse module is the bit all 0 of default storage, can be any by need by programming
Bit is changed into 1 by 0, once changes 1 into, cannot change 0 again into, and this process is irreversible.E-fuse module is integrated in
Chip internal, assailant is difficult to navigate to its position, so utilizing E-fuse technology to prevent assailant from entering chip herein
Test pattern.
As it is shown in figure 1, embodiments provide a kind of method protecting chip test mode, the method includes:
S110, during initialization before chip is tested, by the electronic programmable fuse E-fuse mould in described chip
The bit bit string of the predetermined storage location of block is as protected code；
S120, after the initialization before described chip completes test, reads from the predetermined storage location of described E-fuse module
Take described protected code；When described protected code is not 0, forbid that described chip enters test pattern；When described protected code is 0,
Allow described chip to enter test pattern, if chip to be forbidden enters test pattern next time, then change described protected code；
Described method can also include following feature:
Wherein, the bit of E-fuse module default storage all 0；
The feature of E-fuse module is: can be changed, by 0, any bit needed into 1 by programming, once change 1 into,
0 cannot be changed again into；
Alternatively, change described protected code, including: it is 1 by each bit position of described protected code；
Alternatively, the length of described protected code is made an appointment；
As in figure 2 it is shown, embodiments provide a kind of method protecting chip test mode, the method includes:
S210, during initialization before chip is tested, by the electronic programmable fuse E-fuse mould in described chip
The bit bit string of the first storage position of block is as protected code, at the second storage position write key of described E-fuse module,
The first ciphertext is write in the 3rd storage position of described E-fuse module；
S220, after the initialization before described chip completes test, reads from the first storage position of described E-fuse module
Take described protected code；When described protected code is not 0, forbid that described chip enters test pattern；When described protected code is 0,
Read described key from the second storage position of described E-fuse module, read from the 3rd storage position of described E-fuse module
Described first ciphertext, reads in plain text in other memory modules from described chip, utilizes and carries out in plain text described in described double secret key
Encryption obtains the second ciphertext；If described second ciphertext differs with described first ciphertext, then forbid that described chip enters test
Pattern；If described second ciphertext is identical with described first ciphertext, then described chip is allowed to enter test pattern, if to forbid
Chip enters test pattern next time, then change described protected code, or, change described protected code and described key；
Described method can also include following feature:
Wherein, the bit of E-fuse module default storage all 0；
The feature of E-fuse module is: can be changed, by 0, any bit needed into 1 by programming, once change 1 into,
0 cannot be changed again into；
Alternatively, change described protected code, including: it is 1 by each bit position of described protected code；
Alternatively, change described key, including: it is 1 by each bit position of described key；
As it is shown on figure 3, embodiments provide a kind of device protecting chip test mode, including:
Initialization module 301, when being used for the initialization before chip is tested, by the electronic programmable in described chip
The bit bit string of the predetermined storage location of fuse E-fuse module is as protected code；
Test pattern judges and protection module 302, after the initialization before completing test at described chip, from described E-
The predetermined storage location of fuse module reads described protected code；When described protected code is not 0, forbid that described chip enters test
Pattern；When described protected code is 0, it is allowed to described chip enters test pattern, if chip to be forbidden enters test mould next time
Formula, then change described protected code；
Described device can also include following feature:
Alternatively, test pattern protection module 303, it is used for changing described protected code, including: each by described protected code
Individual bit position is 1；
Alternatively, the length of described protected code is made an appointment；
As shown in Figure 4, embodiments provide a kind of device protecting chip test mode, including:
Initialization module 401, when being used for the initialization before chip is tested, by the electronic programmable in described chip
The bit bit string of the first storage position of fuse E-fuse module is as protected code, in the second storage position of described E-fuse module
Put write key, write the first ciphertext in the 3rd storage position of described E-fuse module；
Test pattern judges and protection module 402, after the initialization before completing test at described chip, from described E-
Described protected code is read in first storage position of fuse module；When described protected code is not 0, forbid that described chip enters test
Pattern；When described protected code is 0, read described key, from described E-from the second storage position of described E-fuse module
Described first ciphertext is read in 3rd storage position of fuse module, reads in plain text in other memory modules from described chip,
Utilize and described in described double secret key, be encrypted acquisition the second ciphertext in plain text；If described second ciphertext and described first ciphertext not phase
With, then forbid that described chip enters test pattern；If described second ciphertext is identical with described first ciphertext, then allow described core
Sheet enters test pattern, if chip to be forbidden enters test pattern next time, then changes described protected code, or, change is described
Protected code and described key；
Alternatively, test pattern protection module 403, it is used for changing described protected code, including: each by described protected code
Individual bit position is 1；
Alternatively, test pattern protection module 403, it is used for changing described key, including: by each ratio of described key
Special position is 1；
Example 1
This example 1 provides a kind of method protecting chip test mode, comprises the following steps:
Step S501, during initialization before chip is tested, by 1 ratio of the position of the address 1 of E-fuse module
Special position is as protected code；
Wherein, the bit all 0 of E-fuse module default storage, any bit that will be able to be needed by programming
Changed into 1 by 0, once change 1 into, 0 cannot be changed again into；
Step S502, after the initialization before described chip completes test, if it is desired to enter the test pattern of chip, then
Described protected code is read from the position of the address 1 of described E-fuse module；
Step S503, it is judged that whether described protected code is 0, is then to perform step S504, otherwise, forbids that described chip enters
Test pattern；
Step S504, it is allowed to described chip enters test pattern；
Step S505, tests chip；
Step S506, after test completes, if chip to be forbidden enters back into test pattern next time, then by described protected code
Change to 1.
Wherein, after described protected code is changed to 1, next time reads institute from the position of the address 1 of described E-fuse module
When stating protected code, described protected code, owing to not being 0, therefore cannot be again introduced into test pattern, thus protect the safety of chip.
Example 2
This example 2 provides a kind of method protecting chip test mode, comprises the following steps:
Step S601, during initialization before chip is tested, by 1 ratio of the position of the address 1 of E-fuse module
Special position is as protected code, at the second storage position write key of described E-fuse module, in the 3rd of described E-fuse module
Storage position writes the first ciphertext；
Step S602, after the initialization before described chip completes test, if it is desired to enter the test pattern of chip, then
Described protected code is read from the position of the address 1 of described E-fuse module；
Step S603, it is judged that whether described protected code is 0, is then to perform step S604, otherwise forbids that described chip enters
Test pattern；
Step S604, reads described key, from described E-fuse module from the second storage position of described E-fuse module
The 3rd storage position read described first ciphertext, other memory modules from described chip read in plain text, utilize described
Acquisition the second ciphertext it is encrypted in plain text described in double secret key；
Step S605, it is judged that described second ciphertext is the most identical with described first ciphertext, is then to perform step S606, otherwise
Forbid that described chip enters test pattern；
Step S606, it is allowed to described chip enters test pattern；
Step S607, tests chip；
Step S608, after test completes, if chip to be forbidden enters back into test pattern next time, then by described protected code
Change to 1, and each bit of described key is changed to 1；
Wherein, after described protected code is changed to 1, next time reads institute from the position of the address 1 of described E-fuse module
When stating protected code, described protected code, owing to not being 0, therefore cannot be again introduced into test pattern, thus protect the safety of chip.
Further, since each bit of described key is changed to 1, read out the false key of entirely 1 next time, utilize described
False key is encrypted the second ciphertext of acquisition to plaintext, with the first ciphertext utilizing correct key to obtain before the most not
With, so also cannot be introduced into test pattern, thus protect the safety of chip.
A kind of method and apparatus protecting chip test mode that above-described embodiment provides, at the beginning of before chip is tested
During beginningization, using the bit bit string of the predetermined storage location of the electronic programmable fuse E-fuse module in described chip as protection
Code, after the initialization before chip completes test, when described protected code is not 0, forbids that described chip enters test pattern；?
When described protected code is 0, it is allowed to described chip enters test pattern, if chip to be forbidden enters test pattern, the most more next time
Change described protected code.Owing to E-fuse module is integrated in chip internal, assailant is difficult to navigate to its position, and utilizes E-
Bit in fuse module is once changed into 1 by 0, and the feature of 0 of cannot changing into again is provided with protected code, or protected code, close
Key and ciphertext, by the test pattern of multiple protective chip, prevent assailant from entering the test pattern of chip.
One of ordinary skill in the art will appreciate that all or part of step in said method can be instructed by program
Related hardware completes, and described program can be stored in computer-readable recording medium, such as read only memory, disk or CD
Deng.Alternatively, all or part of step of above-described embodiment can also use one or more integrated circuit to realize, accordingly
Ground, each module/unit in above-described embodiment can realize to use the form of hardware, it would however also be possible to employ the shape of software function module
Formula realizes.The present invention is not restricted to the combination of the hardware and software of any particular form.
It should be noted that the present invention also can have other various embodiments, spiritual and essence without departing substantially from the present invention
In the case of, those of ordinary skill in the art can make various corresponding change and deformation according to the present invention, but these are corresponding
Change and deform the protection domain that all should belong to appended claims of the invention.
Claims (10)
1. the method protecting chip test mode, the method includes:
During initialization before chip is tested, the predetermined of electronic programmable fuse E-fuse module in described chip is deposited
The bit bit string that storage space is put is as protected code；
After initialization before described chip completes test, read described protection from the predetermined storage location of described E-fuse module
Code；When described protected code is not 0, forbid that described chip enters test pattern；When described protected code is 0, it is allowed to described core
Sheet enters test pattern, if chip to be forbidden enters test pattern next time, then changes described protected code.
2. the method for claim 1, it is characterised in that:
Change described protected code, including: it is 1 by each bit position of described protected code.
3. method as claimed in claim 1 or 2, it is characterised in that:
The length of described protected code is made an appointment.
4. the method protecting chip test mode, the method includes:
During initialization before chip is tested, deposit first of the electronic programmable fuse E-fuse module in described chip
The bit bit string that storage space is put is as protected code, at the second storage position write key of described E-fuse module, at described E-
3rd storage position of fuse module writes the first ciphertext；
After initialization before described chip completes test, read described protection from the first storage position of described E-fuse module
Code；When described protected code is not 0, forbid that described chip enters test pattern；When described protected code is 0, from described E-
Described key is read in second storage position of fuse module, reads described first from the 3rd storage position of described E-fuse module
Ciphertext, reads in plain text in other memory modules from described chip, utilizes and is encrypted acquisition in plain text described in described double secret key
Second ciphertext；If described second ciphertext differs with described first ciphertext, then forbid that described chip enters test pattern；If
Described second ciphertext is identical with described first ciphertext, then allow described chip to enter test pattern, if chip to be forbidden is next
Enter test pattern, then change described protected code, or, change described protected code and described key.
5. method as claimed in claim 4, it is characterised in that
Change described protected code, including: it is 1 by each bit position of described protected code；
Alternatively, change described key, including: it is 1 by each bit position of described key.
6. protect a device for chip test mode, including:
Initialization module, when being used for the initialization before chip is tested, by electronic programmable fuse E-in described chip
The bit bit string of the predetermined storage location of fuse module is as protected code；
Test pattern judge module, after the initialization before completing test at described chip, pre-from described E-fuse module
Surely described protected code is read in storage position；When described protected code is not 0, forbid that described chip enters test pattern；Described
When protected code is 0, it is allowed to described chip enters test pattern, if chip to be forbidden enters test pattern next time, then changes institute
State protected code.
7. device as claimed in claim 6, it is characterised in that:
Test pattern protection module, is used for changing described protected code, including: it is 1 by each bit position of described protected code.
Device the most as claimed in claims 6 or 7, it is characterised in that:
The length of described protected code is made an appointment.
9. protect a device for chip test mode, including:
Initialization module, when being used for the initialization before chip is tested, by electronic programmable fuse E-in described chip
The bit bit string of the first storage position of fuse module is as protected code, in the second storage position write of described E-fuse module
Key, writes the first ciphertext in the 3rd storage position of described E-fuse module；
Test pattern judge module, after the initialization before completing test at described chip, from the of described E-fuse module
Described protected code is read in one storage position；When described protected code is not 0, forbid that described chip enters test pattern；Described
When protected code is 0, read described key, from the 3rd of described E-fuse module the from the second storage position of described E-fuse module
Described first ciphertext is read in storage position, reads in plain text, utilize described double secret key in other memory modules from described chip
Described plaintext is encrypted acquisition the second ciphertext；If described second ciphertext differs with described first ciphertext, then forbid described
Chip enters test pattern；If described second ciphertext is identical with described first ciphertext, then described chip is allowed to enter test mould
Formula, if chip to be forbidden enters test pattern next time, then changes described protected code, or, change described protected code and more
Change described key.
10. device as claimed in claim 8, it is characterised in that:
Test pattern protection module, is used for changing described protected code, including: it is 1 by each bit position of described protected code；
Test pattern protection module, is used for changing described key, including: it is 1 by each bit position of described key.
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| CN201610703536.9A CN106326781B (en) | 2016-08-22 | 2016-08-22 | A kind of method and apparatus for protecting chip test mode |
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| CN201610703536.9A CN106326781B (en) | 2016-08-22 | 2016-08-22 | A kind of method and apparatus for protecting chip test mode |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107861047A (en) * | 2017-11-01 | 2018-03-30 | 北京智芯微电子科技有限公司 | The detecting system and detection method of safety test pattern |
| CN108896903A (en) * | 2018-06-13 | 2018-11-27 | 天津大学 | The gradually verifying type security sweep chain apparatus and method of logic-based encryption |
| CN112749419A (en) * | 2020-12-31 | 2021-05-04 | 广州万协通信息技术有限公司 | Protection device and method for security chip test mode |
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|---|---|---|---|---|
| CN1979686A (en) * | 2005-12-06 | 2007-06-13 | 上海华虹Nec电子有限公司 | Safety detecting method for system integrated chip with built-in non-volatile memory |
| CN103187095A (en) * | 2011-12-30 | 2013-07-03 | 联芯科技有限公司 | Efuse module control method and chip with efuse module |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1979686A (en) * | 2005-12-06 | 2007-06-13 | 上海华虹Nec电子有限公司 | Safety detecting method for system integrated chip with built-in non-volatile memory |
| CN103187095A (en) * | 2011-12-30 | 2013-07-03 | 联芯科技有限公司 | Efuse module control method and chip with efuse module |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107861047A (en) * | 2017-11-01 | 2018-03-30 | 北京智芯微电子科技有限公司 | The detecting system and detection method of safety test pattern |
| CN108896903A (en) * | 2018-06-13 | 2018-11-27 | 天津大学 | The gradually verifying type security sweep chain apparatus and method of logic-based encryption |
| CN112749419A (en) * | 2020-12-31 | 2021-05-04 | 广州万协通信息技术有限公司 | Protection device and method for security chip test mode |
| CN112749419B (en) * | 2020-12-31 | 2023-11-21 | 广州万协通信息技术有限公司 | Protection device and method for safety chip test mode |
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| Publication number | Publication date |
|---|---|
| CN106326781B (en) | 2019-04-19 |
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