CN106301353B - Analog voter circuit - Google Patents
Analog voter circuit Download PDFInfo
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- CN106301353B CN106301353B CN201610850626.0A CN201610850626A CN106301353B CN 106301353 B CN106301353 B CN 106301353B CN 201610850626 A CN201610850626 A CN 201610850626A CN 106301353 B CN106301353 B CN 106301353B
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- 239000003990 capacitor Substances 0.000 claims description 6
- 230000003321 amplification Effects 0.000 claims 2
- 238000003199 nucleic acid amplification method Methods 0.000 claims 2
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
- H03K19/23—Majority or minority circuits, i.e. giving output having the state of the majority or the minority of the inputs
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Abstract
The invention provides an analog voter circuit which has high precision, low power consumption and high speed. The power supply circuit comprises an amplifying unit connected between a power supply voltage and an output port, a comparing unit and a tail circuit unit which are sequentially connected with the output port and a grounding port; the comparison unit comprises a first branch and a second branch; the first branch circuit comprises n+1 n-fet transistors, drain ends of the n-fet transistors are all connected with an output port out, source ends of the n-fet transistors are all grounded through a tail circuit unit, wherein the source ends of the n-fet transistors are connected with n-bit input signals, and the source ends of the other n-fet transistors are grounded; the second branch circuit comprises n+1 n-fet transistors, drain ends of the n-fet transistors are all connected with an output port out_n, source ends of the n-fet transistors are all grounded through a tail circuit unit, wherein the source ends of the n-fet transistors are connected with n-bit input inverted signals, and the source ends of the other n-fet transistors are connected with a power supply voltage.
Description
Technical Field
The invention relates to the field of circuit design, in particular to an analog voter circuit.
Background
Computers and various electronic devices are widely used in all aspects of modern life, and the amount of data that needs to be processed and transmitted is increasing. From the earliest 8-bit computer system to the current 64-bit processor. As the system bit width increases, the system power consumption increases. Accordingly, many algorithms have been proposed for reducing power consumption. One of the most common is to calculate the number of "0" s or "1" s in the transmission process, and if "0" s account for most of them, the data is kept unchanged, otherwise, the data is all inverted. And voting circuits are needed to calculate the number of "0" s or "1" s.
Current voting circuits fall into two main categories: digital voter circuitry and analog voter circuitry. An 8-bit analog voting circuit is shown in fig. 1, which is commonly used at present; wherein x0/x1/...x7 is 8 bits that need to be voted, x0_n/x1_n/… x7_n is x0/x1/… x7 inverted, and en is the enable signal of the circuit.
The working principle is as follows: 1. any one of x0/x1/…/x7/x0_n/x1_n/…/x7_n is "1", the transistor to which it is connected is turned on; current flows each time a transistor is turned on; 2. by comparing the current values of the left side and the right side, the number of 1's on the input signals of the left side and the right side can be judged; 3. if the left side is "1" more, it indicates that "1" in x0/x1/…/x7 is the majority; 4. if the right side "1" is more, it indicates that "1" in x0_n/x1_n/…/x7_n is the majority and "0" in x0/x1/…/x7 is the majority.
Usually the data that we need to compare are an even number of data (8 bits/16 bits …/64 bits), so as many as the number of "0" s and "1" s will occur. For this case, the current analog voter is commonly used to change the size of the left or right transistor so that the current is different from the normal current. This will cause the currents on the left and right sides to be different for the same "0", "1" and the desired result.
The above method requires a designer to precisely adjust the size of the transistor and is subject to errors due to the manufacturing process. So that the precision of the current common analog voter is not very high and even errors occur.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides the analog voter circuit which has high precision, low power consumption and high speed.
The invention is realized by the following technical scheme:
an analog voter circuit comprises an amplifying unit connected between a power supply voltage and an output port, and a comparing unit and a tail circuit unit which are sequentially connected with the output port and a grounding port;
the comparison unit comprises a first branch and a second branch;
The first branch circuit comprises n+1 n-fet transistors, drain ends of the n-fet transistors are all connected with an output port out, source ends of the n-fet transistors are all grounded through a tail circuit unit, wherein the source ends of the n-fet transistors are connected with n-bit input signals, and the source ends of the other n-fet transistors are grounded;
The second branch circuit comprises n+1 n-fet transistors, drain ends of the n-fet transistors are all connected with an output port out_n, source ends of the n-fet transistors are all grounded through a tail circuit unit, wherein the source ends of the n-fet transistors are connected with n-bit input inverted signals, and the source ends of the other n-fet transistors are connected with a power supply voltage.
Preferably, the source terminal of each n-fet transistor in the comparing unit for connecting an input signal is connected in series with a capacitor, a resistor or a current source.
Preferably, the source terminal of each n-fet transistor in the comparing unit for connecting the input inverse signal is connected in series with a capacitor, a resistor or a current source.
Preferably, the tail circuit unit comprises a tail circuit n-fet transistor; the gate end of the tail circuit n-fet transistor is connected with an enable signal en of the circuit operation, the source end is grounded, and the drain end is connected with the comparison unit.
Preferably, the comparing unit includes a first amplifying branch and a second amplifying branch;
the first amplifying branch comprises n+1 first p-fet transistors with source ends connected with a power supply voltage, and n+1 second p-fet transistors with drain ends connected with an output port out; the drain end of the first p-fet transistor is connected with the source end of the second p-fet transistor in a one-to-one correspondence manner; the gate ends of the n second p-fet transistors are respectively connected with n-bit input signals, and the gate ends of the other second p-fet transistors are grounded;
The second amplifying branch comprises n+1 third p-fet transistors with source ends connected with the power supply voltage, and n+1 fourth p-fet transistors with drain ends connected with the output port out_n, wherein the drain ends of the third p-fet transistors are correspondingly connected with the source ends of the fourth p-fet transistors one by one; the gate ends of the n third p-fet transistors are respectively connected with n-bit input inverse signals, and the gate ends of the other second p-fet transistors are connected with power supply voltage;
the gate terminals of the first p-fet transistor and the third p-fet transistor are both connected to the output port out.
Preferably, the comparing unit comprises a first, a second, a third and a fourth comparing p-fet transistors and a first and a second comparing n-fet transistors;
the source ends of the first comparison p-fet transistor and the second comparison p-fet transistor are both connected with the power supply voltage, the drain ends of the first comparison p-fet transistor and the second comparison p-fet transistor are both connected with the drain end of the first comparison n-fet transistor, the gate end of the first comparison p-fet transistor is connected with the enable signal en, and the gate end of the second comparison p-fet transistor is connected with the drain end of the second comparison n-fet transistor; the source end of the first comparison n-fet transistor is connected with the output port out, and the gate end of the first comparison n-fet transistor is connected with the drain end of the second comparison n-fet transistor;
the source ends of the third comparison p-fet transistor and the fourth comparison p-fet transistor are connected with the power supply voltage, the drain ends of the third comparison p-fet transistor and the fourth comparison p-fet transistor are connected with the enable signal en, and the gate end of the third comparison p-fet transistor is connected with the drain end of the first comparison n-fet transistor; the source end of the second comparison n-fet transistor is connected with the output port out_n, and the gate end of the second comparison n-fet transistor is connected with the drain end of the first comparison n-fet transistor.
Compared with the prior art, the invention has the following beneficial technical effects:
the invention adds a group of channels on the left and right sides of the existing analog voting circuit, and the added channels are always opened on one side by the control of the gate end, and the other side is always closed, when the number of the input '0' and '1' is the same, the current difference of the channels is left and right because of the added channels; the method can rapidly conduct voting judgment, and is high in precision, low in power consumption and high in speed.
Furthermore, by arranging different amplifying units, only n-fet channels serving as discharge channels can be reserved on the whole circuit, so that the precision is ensured, and meanwhile, the whole volume of the circuit is reduced.
Furthermore, the current of the circuit during operation is reduced by connecting a capacitor, a resistor or a current source in series under the n-fet transistor, so that the operation power consumption of the circuit is reduced.
Drawings
Fig. 1 is a block diagram of an 8-bit analog voting circuit in the prior art.
Fig. 2 is a schematic diagram of the analog voting circuit described in example 1 of the present invention.
Fig. 3 is a schematic diagram of the analog voting circuit described in example 2 of the present invention.
Fig. 4 is a schematic diagram of the analog voting circuit described in example 3 of the present invention.
In the figure: x0/x1 …/x7 is the input signal; x0_n/x1_n/…/x7_n is x0/x1/…/x 7.
Detailed Description
The invention will now be described in further detail with reference to specific examples, which are intended to illustrate, but not to limit, the invention.
Example 1
The present invention is illustrated in fig. 2, taking an 8-bit input signal as an example, i.e., n=8; wherein, the enable signal en is a circuit work switch, en=1 starts to work, and en=0 closes the circuit; the output port out is the output of the circuit comparison result; the output port out_n is out inverted.
Input signal that will require voting:
x0/x1/… x7 connects the gate ports of N-fet N0/N1 … N7 and P-fet P8/P9 …/P15;
the drain ends of the N-fet N0/N1 … N7 and the P-fet P8/P9 … P15 are connected with the output port out of the circuit;
The source ends of the P-fets P8/P9 … P15 are respectively connected with the drain ends of the P-fets P0/P1 … P7;
The source terminal of the P-fet P0/P1 … P7 is connected to the supply voltage;
The input inverse of the vote is needed: x0_n/x1_n/… x7_n connects gate ports of N-fet N0'/N1' … N7 'and P-fet P8'/P9'…/P15';
The drain terminals of the N-fet N0'/N1' … N7 'and the P-fet P8'/P9'… P15' are connected with the output port out_n of the circuit;
The source ends of the P-fets P8'/P9' … P15 'are respectively connected with the drain ends of the P-fets P0'/P1'… P7';
The source terminal of the P-fet P0'/P1' … P7' is connected to the supply voltage;
The gate terminal of P-fet P0/P1 … P7/P0'/P1' … P7' is connected to the output port out;
an enable signal en of circuit operation is connected to the gate terminal of the tail circuit n-fet;
The drain terminals of the tail circuits N-fets are connected to the source terminals of all input N-fets (N0/N1 … N7/N0'/N1' … N7 ');
the source terminal of the tail circuit n-fet is connected to ground.
According to the invention, through the two groups of increased channels, the gate end of one group of n-fet Nd is grounded to realize constant closing, the gate end of p-fet Pd1 is grounded out, and the gate end of p-fet Pd2 is grounded to correspondingly realize constant closing; the grid end power supply voltage of the other group of n-fets Nd ' is constant on, the grid end of the p-fets Pd1' is out, and the grid end power supply voltage of the p-fets Pd2' is constant on correspondingly.
When the analog voting circuit described in this embodiment works, a group of current paths are added to the left and right sides respectively; however, one side of the passage on both sides always charges the output port out, the other side always discharges the output port out_n, and the left side is closed and the right side is opened as shown in fig. 2; if there are 4 "1"4 "0" s in the input data x0/x1 …/x7, then through the circuit of fig. 2, there are 5 paths on the left to charge out for 4 discharges, and 4 paths on the right to charge out_n for 5 discharges; judging whether the voltages of out and out_n are different to be more than 1 or more than 0, if the voltage of out is greater than the voltage of out_n, the number of 0 is greater than or equal to the number of 1, and if the voltage of out is less than the voltage of out_n, the number of 0 is less than the number of 1; the analog voter of the invention has high accuracy because the analog voter does not need to judge the current by adjusting the transistor size.
Example 2
Further optimization can be performed based on the analog voting circuit described in example 1, using only n-fet transistor paths, as shown in fig. 3.
Input signal for voting: x0/x1/… x7 connects the gate port of N-fet N0/N1 … N7;
input inverse of voting is required: x0_n/x1_n/… x7_n is connected with the gate end of N-fet N0'/N1' … N7 ';
Fig. 3 only retains the n-fet path as a discharge path, and the voltage of the output signal out/out_n is determined by how many discharge paths are.
Example 3
Based on the analog voting circuit described in example 2, the analog voting circuit can be further optimized, as shown in fig. 4, the working current of the analog voting circuit can be reduced, and the analog voting circuit can be optimized into a circuit that a capacitor is connected in series under each n-fet transistor; or a resistor is connected in series under each n-fet transistor; or a current source is connected in series under each n-fet transistor; or any one of a series capacitance or resistance or current source under each n-fet transistor.
Claims (6)
1. An analog voter circuit is characterized by comprising an amplifying unit connected between a power supply voltage and an output port, and a comparing unit and a tail circuit unit which are sequentially connected with the output port and a grounding port;
the comparison unit comprises a first branch and a second branch;
The first branch circuit comprises n+1 n-fet transistors, drain ends of the n-fet transistors are all connected with an output port out, source ends of the n-fet transistors are all grounded through a tail circuit unit, gate ends of the n-fet transistors are connected with n-bit input signals, and gate ends of the other n-fet transistors are grounded;
The second branch circuit comprises n+1 n-fet transistors, drain ends of the n-fet transistors are all connected with an output port out_n, source ends of the n-fet transistors are all grounded through a tail circuit unit, wherein gate ends of the n-fet transistors are connected with n-bit input inverted signals, and gate ends of the other n-fet transistors are connected with a power supply voltage.
2. An analog voter circuit according to claim 1, wherein the source of each n-fet transistor in the comparison unit for connection to an input signal is connected in series with a capacitor, resistor or current source.
3. An analog voter circuit according to claim 1, wherein the source of each n-fet transistor in the comparison unit for coupling an input inverse signal is connected in series with a capacitor, resistor or current source.
4. An analog voter circuit as claimed in claim 1, wherein the tail circuit unit comprises a tail circuit n-fet transistor; the gate end of the tail circuit n-fet transistor is connected with an enable signal en of the circuit operation, the source end is grounded, and the drain end is connected with the comparison unit.
5. An analog voter circuit according to claim 1, wherein the comparison unit comprises a first amplification branch and a second amplification branch;
The first amplifying branch comprises n+1 first p-fet transistors with source ends connected with a power supply voltage, and n+1 second p-fet transistors with drain ends connected with an output port out; the drain end of the first p-fet transistor is connected with the source end of the second p-fet transistor in a one-to-one correspondence manner; the gate ends of the n second p-fet transistors are respectively connected with n-bit input signals, and the gate ends of the other second p-fet transistors are grounded;
The second amplifying branch comprises n+1 third p-fet transistors with source ends connected with the power supply voltage, and n+1 fourth p-fet transistors with drain ends connected with the output port out_n, wherein the drain ends of the third p-fet transistors are correspondingly connected with the source ends of the fourth p-fet transistors one by one; the gate ends of the n third p-fet transistors are respectively connected with n-bit input inverse signals, and the gate ends of the other second p-fet transistors are connected with power supply voltage;
the gate terminals of the first p-fet transistor and the third p-fet transistor are both connected to the output port out.
6. An analog voter circuit according to claim 1, wherein said comparing unit comprises first, second, third and fourth comparing p-fet transistors, and first and second comparing n-fet transistors;
the source ends of the first comparison p-fet transistor and the second comparison p-fet transistor are both connected with the power supply voltage, the drain ends of the first comparison p-fet transistor and the second comparison p-fet transistor are both connected with the drain end of the first comparison n-fet transistor, the gate end of the first comparison p-fet transistor is connected with the enable signal en, and the gate end of the second comparison p-fet transistor is connected with the drain end of the second comparison n-fet transistor; the source end of the first comparison n-fet transistor is connected with the output port out, and the gate end of the first comparison n-fet transistor is connected with the drain end of the second comparison n-fet transistor;
the source ends of the third comparison p-fet transistor and the fourth comparison p-fet transistor are connected with the power supply voltage, the drain ends of the third comparison p-fet transistor and the fourth comparison p-fet transistor are connected with the enable signal en, and the gate end of the third comparison p-fet transistor is connected with the drain end of the first comparison n-fet transistor; the source end of the second comparison n-fet transistor is connected with the output port out_n, and the gate end of the second comparison n-fet transistor is connected with the drain end of the first comparison n-fet transistor.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610850626.0A CN106301353B (en) | 2016-09-26 | 2016-09-26 | Analog voter circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610850626.0A CN106301353B (en) | 2016-09-26 | 2016-09-26 | Analog voter circuit |
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| CN106301353A CN106301353A (en) | 2017-01-04 |
| CN106301353B true CN106301353B (en) | 2024-05-03 |
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| CN201610850626.0A Active CN106301353B (en) | 2016-09-26 | 2016-09-26 | Analog voter circuit |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0472913A (en) * | 1990-07-13 | 1992-03-06 | Nissan Motor Co Ltd | Output buffer circuit |
| CN105955387A (en) * | 2016-05-12 | 2016-09-21 | 西安电子科技大学 | Double-ring protection low drop out (LDO) linear voltage regulator |
| CN206211974U (en) * | 2016-09-26 | 2017-05-31 | 西安紫光国芯半导体有限公司 | Straw vote device circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7579879B2 (en) * | 2005-10-27 | 2009-08-25 | Honeywell International Inc. | Voting scheme for analog signals |
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2016
- 2016-09-26 CN CN201610850626.0A patent/CN106301353B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0472913A (en) * | 1990-07-13 | 1992-03-06 | Nissan Motor Co Ltd | Output buffer circuit |
| CN105955387A (en) * | 2016-05-12 | 2016-09-21 | 西安电子科技大学 | Double-ring protection low drop out (LDO) linear voltage regulator |
| CN206211974U (en) * | 2016-09-26 | 2017-05-31 | 西安紫光国芯半导体有限公司 | Straw vote device circuit |
Non-Patent Citations (1)
| Title |
|---|
| 彭伟娣 ; 张文杰 ; 谢亮 ; 金湘亮 ; .一种低功耗CMOS晶振电路设计.电子器件.2013,(第03期),全文. * |
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