CN106301051A - The drain current suppressing method of single-phase non-isolated cascaded H-bridges inverter and restraining device - Google Patents

The drain current suppressing method of single-phase non-isolated cascaded H-bridges inverter and restraining device Download PDF

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CN106301051A
CN106301051A CN201610790560.0A CN201610790560A CN106301051A CN 106301051 A CN106301051 A CN 106301051A CN 201610790560 A CN201610790560 A CN 201610790560A CN 106301051 A CN106301051 A CN 106301051A
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module
level
output
bridge
export
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CN106301051B (en
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于世能
杨乐
毛旺
徐君
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Sungrow Power Supply Co Ltd
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Sungrow Power Supply Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02J3/383—
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0038—Circuits or arrangements for suppressing, e.g. by masking incorrect turn-on or turn-off signals, e.g. due to current spikes in current mode control
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
    • H02M1/007—Plural converter units in cascade
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/56—Power conversion systems, e.g. maximum power point trackers

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Abstract

This application discloses drain current suppressing method and the restraining device of single-phase non-isolated cascaded H-bridges inverter, this inverter is formed by 1～2k H bridge module cascade, and No. i is collectively referred to as a module with 2k i+1 H bridge module, i=1, and 2 ..., k；The method includes: obtain the DC voltage of each H bridge module；Calculate the DC voltage error sum of two H bridge modules in each module；Follow the module making the DC voltage error sum of internal two H bridge modules the biggest to obtain the biggest output, make the output of two H bridge modules in same module keep equal and make total parasitic capacitor voltage keep constant principle, calculate the modulated signal of each H bridge module；Calculated modulated signal is sent to the H bridge module of correspondence, thus inhibits leakage current.

Description

The drain current suppressing method of single-phase non-isolated cascaded H-bridges inverter and restraining device
Technical field
The present invention relates to electric and electronic technical field, more particularly, it relates to the leakage of single-phase non-isolated cascaded H-bridges inverter Electric current suppressing method and restraining device.
Background technology
Single-phase non-isolated cascaded H-bridges inverter by multiple H bridge modules cascade form, its topological structure as shown in Figure 1: each H The photovoltaic battery panel of the direct current side joint independence of bridge module, the AC of each H bridge module accesses electrical network through filter inductance after being in series. Single-phase non-isolated cascaded H-bridges inverter by carrying out independent MPPT (Maximum Power Point to each photovoltaic battery panel Tracking, MPPT maximum power point tracking) control to obtain the photovoltaic energy utilization rate of maximum.
In single-phase non-isolated cascaded H-bridges inverter, there is directly electrical connection between electrical network and photovoltaic battery panel, lead Cause parasitic capacitance (the i.e. electric capacity C in Fig. 1 of photovoltaic battery panelP1～CPn) can produce under common-mode voltage and differential mode voltage effect Certain electric leakage, this not only brings conduction and radiation interference, adds grid current harmonic content and system loss, it is also possible to Injure relevant device and personal security.
Summary of the invention
In view of this, the present invention provides drain current suppressing method and the suppression of a kind of single-phase non-isolated cascaded H-bridges inverter Device, effectively to suppress leakage current.
A kind of drain current suppressing method of single-phase non-isolated cascaded H-bridges inverter, described single-phase non-isolated cascaded H-bridges inversion Device is formed by 1～2k H bridge module cascade, and No. i is collectively referred to as a module with 2k-i+1 H bridge module, i=1, and 2 ..., k；Described Method includes:
Obtain the DC voltage of each H bridge module；
According to the DC voltage got, be calculated in each module the DC voltage error of two H bridge modules it With；
Follow the module making the DC voltage error sum of internal two H bridge modules the biggest and obtain the biggest output work Rate, make the output of two H bridge modules in same module keep equal and make total parasitic capacitor voltage keep constant principle, Calculate the modulated signal of each H bridge module；
Calculated modulated signal is sent to the H bridge module of correspondence.
Wherein, follow the module making the DC voltage error sum of internal two H bridge modules the biggest described in and obtain the biggest Output, make the output of two H bridge modules in same module keep equal and make total parasitic capacitor voltage keep perseverance Fixed principle, calculates the modulated signal of each H bridge module, including:
According to the DC voltage error sum of two H bridge modules order from big to small in each module, will be except described No. k Other modules outside module are respectively defined as 1～k-1 module, and wherein, described k module refers to No. k and k+1 H The module of bridge module；
It is calculated the DC voltage sum of two H bridge modules in each module；
The DC voltage sum of two H bridge modules in i module is represented with Udi；Use VrefRepresent that single-phase non-isolated cascades The instantaneous voltage of total modulating wave of H bridge inverter；With Uei represent two H bridge modules of i module DC voltage error it With；Two stacking triangular carriers, and 1 >=Vc2 >=0.5 >=Vc1 >=0 is represented respectively with Vc1 and Vc2；When Time, define described total modulating wave and be positioned at modulating range m+, whenTime, define described total modulating wave and be positioned at Modulating range m-, m=1,2 ..., k；
When described total modulating wave is in positive half period, calculate the modulation letter of 1～2k H bridge module according to following rule Number:
WhenAnd during m=1, control 1～k module and export 0 level；
WhenAnd 1<during m: if Uek>Ue (m-1), control m-1 module export 0 level, k Number module output+2 level, m～k-1 module export 0 level, residue module output+2 level；Otherwise (i.e. Ue (m-1) > Uek > Uem, or Ue (m-1) > Uem > Uek), control m-1 module output+2 level, k module exports 0 level, m～k-1 module Export 0 level, residue module output+2 level；
WhenAnd during m=1, control 1～k-1 module and export 0 level, k mould Group output+1 level；
WhenAnd 1 < during m, control m～k-1 module export 0 level, k module Output+1 level, residue module output+2 level；
WhenAnd during m=k, control 1～k module output+2 level；
WhenAnd m is<during k: if Uek>Uem, control m module and export 0 level, k mould Group output+2 level, 1～m-1 module output+2 level, residue module export 0 level；Otherwise, m module output+2 is controlled Level, k module exports 0 level, 1～m-1 module output+2 level, residue module exports 0 level；
When described total modulating wave is in negative half-cycle, calculate the modulation letter of 1～2k H bridge module according to following rule Number:
WhenAnd during m=1, control 1～k module and export 0 level；
WhenAnd during m > 1: if Uek > Ue (m-1), control m-1 module output 0 electricity Flat, k module output-2 level, m～k-1 module export 0 level, residue module output-2 level；Otherwise, m-1 module Export-2 level, k module exports 0 level, m～k-1 module exports 0 level, residue module output-2 level；
WhenAnd during m=1, control m～k-1 module and export 0 level, module Vk exports-1 level；
WhenAnd during m > 1, control m～k-1 module and export 0 level, module Vk output-1 level, residue module output-2 level；
WhenAnd during m=k, control 1～k module output-2 level；
WhenAnd m is<during k: if Uek>Uem, control m module and export 0 level, k Number module output-2 level, m+1～k-1 module export 0 level, residue module output-2 level；Otherwise, m module is controlled Export-2 level, k module exports 0 level, m+1～k-1 module exports 0 level, residue module output-2 level.
Wherein, said two stacking triangular carrier is two synchronous stacking triangular carriers.
Wherein, said two stacking triangular carrier is the stacking triangular carrier of two antiphases.
A kind of drain current suppressing device of single-phase non-isolated cascaded H-bridges inverter, described single-phase non-isolated cascaded H-bridges inversion Device is formed by 1～2k H bridge module cascade, and i H bridge module and 2k-i+1 H bridge module are collectively referred to as a module, i=1, and 2 ..., k；Described device includes:
Acquiring unit, for obtaining the DC voltage of each H bridge module；
First computing unit, for according to the DC voltage that gets, is calculated two H bridge modules in each module DC voltage error sum；
Second computing unit, for following the module that the DC voltage error sum making internal two H bridge modules is the biggest Obtain the biggest output, make the output of two H bridge modules in same module keep equal and make total parasitic capacitance electricity Pressure keeps constant principle, calculates the modulated signal of each H bridge module；
Output unit, for being sent to the H bridge module of correspondence by calculated modulated signal.
Wherein, described second computing unit specifically for:
According to the DC voltage error sum of two H bridge modules order from big to small in each module, will be except described No. k Other modules outside module are respectively defined as 1～k-1 module, and wherein, described k module refers to No. k and k+1 H The module of bridge module；
It is calculated the DC voltage sum of two H bridge modules in each module；
The DC voltage sum of two H bridge modules in i module is represented with Udi；Use VrefRepresent that single-phase non-isolated cascades The instantaneous voltage of total modulating wave of H bridge inverter；With Uei represent two H bridge modules of i module DC voltage error it With；Two stacking triangular carriers, and 1 >=Vc2 >=0.5 >=Vc1 >=0 is represented respectively with Vc1 and Vc2；When Time, define described total modulating wave and be positioned at modulating range m+, and work asTime, define described total modulating wave position In modulating range m-, m=1,2 ..., k；
When described total modulating wave is in positive half period, calculate the modulation letter of 1～2k H bridge module according to following rule Number:
WhenAnd during m=1, control 1～k module and export 0 level；
WhenAnd 1<during m: if Uek>Ue (m-1), control m-1 module export 0 level, k Number module output+2 level, m～k-1 module export 0 level, residue module output+2 level；Otherwise (i.e. Ue (m-1) > Uek > Uem, or Ue (m-1) > Uem > Uek), control m-1 module output+2 level, k module exports 0 level, m～k-1 module Export 0 level, residue module output+2 level；
WhenAnd during m=1, control 1～k-1 module and export 0 level, k mould Group output+1 level；
WhenAnd 1 < during m, control m～k-1 module export 0 level, k module Output+1 level, residue module output+2 level；
WhenAnd during m=k, control 1～k module output+2 level；
WhenAnd m is<during k: if Uek>Uem, control m module and export 0 level, k mould Group output+2 level, 1～m-1 module output+2 level, residue module export 0 level；Otherwise, m module output+2 is controlled Level, k module exports 0 level, 1～m-1 module output+2 level, residue module exports 0 level；
When described total modulating wave is in negative half-cycle, calculate the modulation letter of 1～2k H bridge module according to following rule Number:
WhenAnd during m=1, control 1～k module and export 0 level；
WhenAnd during m > 1: if Uek > Ue (m-1), control m-1 module output 0 electricity Flat, k module output-2 level, m～k-1 module export 0 level, residue module output-2 level；Otherwise, m-1 module Export-2 level, k module exports 0 level, m～k-1 module exports 0 level, residue module output-2 level；
WhenAnd during m=1, control m～k-1 module and export 0 level, module Vk exports-1 level；
WhenAnd during m > 1, control m～k-1 module and export 0 level, module Vk output-1 level, residue module output-2 level；
WhenAnd during m=k, control 1～k module output-2 level；
WhenAnd m is<during k: if Uek>Uem, control m module and export 0 level, k Number module output-2 level, m+1～k-1 module export 0 level, residue module output-2 level；Otherwise, m module is controlled Export-2 level, k module exports 0 level, m+1～k-1 module exports 0 level, residue module output-2 level.
Wherein, said two stacking triangular carrier is two synchronous stacking triangular carriers.
Wherein, said two stacking triangular carrier is the stacking triangular carrier of two antiphases.
From above-mentioned technical scheme it can be seen that the present invention eliminates common mode by making total parasitic capacitor voltage keep constant Voltage and the differential mode voltage impact on leakage current, thus effectively inhibit leakage current.Additionally, the present invention also follows makes internal two The module that the DC voltage error sum of H bridge module is the biggest obtain the biggest output and make same module in two H bridges The output of module keeps equal principle, calculates the modulated signal of each H bridge module, to avoid the output of each H bridge module There is bigger difference in power, thus improves system generating efficiency.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing In having technology to describe, the required accompanying drawing used is briefly described, it should be apparent that, the accompanying drawing in describing below is only this Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to Other accompanying drawing is obtained according to these accompanying drawings.
Fig. 1 is a kind of single-phase non-isolated cascaded H-bridges inverter structure schematic diagram disclosed in prior art；
Fig. 2 is the drain current suppressing method stream of a kind of single-phase non-isolated cascaded H-bridges inverter disclosed in the embodiment of the present invention Cheng Tu；
Fig. 3 is the modulating range distribution schematic diagram of a kind of positive half period disclosed in the embodiment of the present invention；
Fig. 4 is the modulation schematic diagram of a kind of positive half period disclosed in the embodiment of the present invention；
Fig. 5 is parasitic capacitor voltage and the leakage current oscillogram of each H bridge module；
Fig. 6 is the drain current suppressing device knot of a kind of single-phase non-isolated cascaded H-bridges inverter disclosed in the embodiment of the present invention Structure schematic diagram.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete Describe, it is clear that described embodiment is only a part of embodiment of the present invention rather than whole embodiments wholely.Based on Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under not making creative work premise Embodiment, broadly falls into the scope of protection of the invention.
See Fig. 2, the embodiment of the invention discloses the drain current suppressing side of a kind of single-phase non-isolated cascaded H-bridges inverter Method, to realize while suppression leakage current, keeps each H bridge module output to equalize, including:
Step S01: obtain the DC voltage of each H bridge module in single-phase non-isolated cascaded H-bridges inverter.
Step S02: according to the DC voltage got, is calculated each mould in single-phase non-isolated cascaded H-bridges inverter Organize the DC voltage error sum of interior two H bridge modules.
Described below what be the module of single-phase non-isolated cascaded H-bridges inverter: the single-phase non-isolated level that the present embodiment is suitable for Connection H bridge inverter by 1～2k H bridge module cascade form, as it is shown in figure 1, for ease of describe, the present embodiment by i (i=1, 2 ..., k) number H bridge module and 2k-i+1 H bridge module are collectively referred to as a module, altogether obtain k module.Wherein, by No. k and k The module of+No. 1 H bridge module synthesis is referred to as k module.
The DC voltage error of H bridge module, refers to the actual value of this H bridge module DC voltage and the difference of command value. The actual value of definition i H bridge module DC voltage is respectively Vdci and Vdri, 2k-i+1 H bridge module direct current with command value The actual value of side voltage and command value are respectively Vdc (2k-i+1) and Vdr (2k-i+1), then calculate i H bridge mould in same module Block and the DC voltage error sum of 2k-i+1 H bridge module, it is simply that calculate Vdci-Vdri+Vdc (2k-i+1)-Vdr (2k- i+1)。
Step S03: follow the module making the DC voltage error sum of internal two H bridge modules the biggest and obtain the biggest Output, make the output of two H bridge modules in same module keep equal and make total parasitic capacitor voltage keep constant Principle, calculate the modulated signal of each H bridge module.
Wherein, make total parasitic capacitor voltage keep constant, be that derivation is as follows in order to suppress leakage current:
The leakage current i of known single-phase non-isolated cascaded H-bridges inverterlgFor:
In formula: CPV1Parasitic capacitance capacitance for i H bridge module；vNiOParasitic capacitor voltage for i H bridge module；vNtO Parasitic capacitor voltage sum for all H bridge modules；Assume that all H bridge module parasitic capacitor voltage are identical, i.e. CPV=CPV1= CPV2=...=CPVn, n=2k.
The parasitic capacitor voltage of known each H bridge module is:
In formula: vCMiAnd vDMiIt is respectively common-mode voltage and the differential mode voltage of i H bridge module.
According to formula 2, available total parasitic capacitor voltage expression formula is
In formula: vCMIt it is total common-mode voltage of 1～2k H bridge module.
As can be seen here, from formula 1, leakage current to be suppressed, it is necessary for keeping total parasitic capacitor voltage constant.Can by formula 3 Knowing, the method keeping total parasitic capacitor voltage constant is: for the module in addition to k module, due to vDMiWith vDM(n-i+1)'s Coefficient is contrary, the differential mode voltage of two H bridge modules in same module can be made to keep equal, keep two H in same module simultaneously Bridge module common-mode voltage sum is constant can eliminate the impact on leakage current of this module；For k module, by using specific opening Close combination ,-0.5v in formula 3 can be madeDMk+0.5vDM(k+1)-vDMk-vDM(k+1)Keep constant, thus maintain total parasitic capacitor voltage Constant, eliminate leakage current.
Herein it should be noted that level number contained by the output waveform of single-phase non-isolated cascaded H-bridges inverter is 4k+ 1, so on the premise of the requirement of satisfied elimination leakage current, for enabling single-phase non-isolated cascaded H-bridges inverter normally to work, Can direct, beyond all doubt it is confirmed that: calculate each H bridge module modulated signal time, it is necessary to 1～k-1 mould will be met Organizing interior two H bridge modules is that two H bridge modules are five electricity in three level output (i.e. output+2,0 ,-2 three kinds of level), k module Flat output (i.e.+2 ,+1,0 ,-1 ,-2 five kinds of level of output).
But in view of calculate the modulated signal of each H bridge module only in accordance with above-mentioned requirements if, although can ensure that single-phase Normally the working and inhibit leakage current of non-isolated cascaded H-bridges inverter, but do not ensure that each H bridge module output is equal Weighing apparatus.And for single-phase non-isolated cascaded H-bridges inverter, if each H bridge module output is uneven, system can be caused to generate electricity Inefficient problem, so the present embodiment is when calculating the modulated signal of each H bridge module, is also added into balancing each H bridge module defeated Go out the requirement of power.
Corresponding relation is there is: when the direct current of H bridge module between DC voltage and the output of known arbitrary H bridge module When side voltage reaches maximum power point, the output of this H bridge module is maximum.So for the different H of two DC voltages For bridge module, the direct current voltage error of which H bridge module is the biggest, and the output of which H bridge module and this H bridge module are The deviation of big output is the biggest, then the output of the two H bridge module to be balanced is it is necessary to make direct current voltage error bigger H bridge module obtain bigger output.Same reason, want to balance the output of 1～2k H bridge module it is necessary to The H bridge module that direct current voltage error is the biggest is made to obtain the biggest output.
On the premise of ensureing that in same module, the output of two H bridge modules is identical, balance the output of each H bridge module Power, namely balances the output of each module, so the present embodiment output of two H bridge modules in ensureing same module Power keep equal in the case of, as long as following the module making the DC voltage error sum of internal two H bridge modules the biggest The principle obtaining the biggest output calculates the modulated signal of each H bridge module, it is possible to avoid the output work of each H bridge module There is bigger difference in rate.
Step S04: calculated modulated signal is sent to the H bridge module of correspondence, thus meets effective suppression Leakage current, and there is bigger difference in the output avoiding each H bridge module.
Seen from the above description, the present embodiment eliminates common-mode voltage and difference by making total parasitic capacitor voltage keep constant The mode voltage impact on leakage current, thus effectively inhibit leakage current.Additionally, the present embodiment is also followed makes internal two H bridge moulds The module that the DC voltage error sum of block is the biggest obtain the biggest output and make same module in two H bridge modules Output keep equal principle, calculate the modulated signal of each H bridge module, to avoid the output of each H bridge module There is bigger difference, thus improve system generating efficiency.
Below, the one of which implementation of described step S03 is given.
Step S031: according to the DC voltage error sum of two H bridge modules order from big to small in each module, will Other modules in addition to k module are respectively defined as 1～k-1 module.
Step S032: be calculated the DC voltage sum of two H bridge modules in each module.
For being described below conveniently, represent the DC voltage sum of two H bridge modules in i module with Udi；Use VrefTable Show the instantaneous voltage of total modulating wave of single-phase non-isolated cascaded H-bridges inverter；The straight of two H bridge modules of i module is represented with Uei Stream side voltage error sum；Two stacking triangular carriers, and 1 >=Vc2 >=0.5 >=Vc1 >=0 is represented respectively with Vc1 and Vc2.
VrefAnd meet between UdiIfThen define described total modulation Ripple is positioned at modulating range m+, wherein m=1, and 2 ... k, as shown in Figure 3；IfThen define described total tune Ripple processed is positioned at modulating range m-.
Step S033: when total modulating wave is in positive half period, calculates the tune of 1～2k H bridge module according to following rule Signal processed, as shown in Figure 4 (Fig. 4 illustrate only 1 < m < situation during k):
1) whenAnd during m=1, control 1～k module and export 0 level；
2) whenAnd 1<during m: if Uek>Ue (m-1), control m-1 module export 0 level, K module output+2 level, m～k-1 module export 0 level, residue module output+2 level；Otherwise (i.e. Ue (m-1) > Uek > Uem, or Ue (m-1) > Uem > Uek), controlling m-1 module output+2 level, k module exports 0 level, m～k-1 module Export 0 level, residue module output+2 level；
3) whenAnd during m=1, control 1～k-1 module export 0 level, No. k Module output+1 level；
4) whenAnd 1 < during m, control m～k-1 module export 0 level, k mould Group output+1 level, residue module output+2 level；
5) whenAnd during m=k, control 1～k module output+2 level；
6) whenAnd m<during k: if Uek>Uem, control m module export 0 level, No. k Module output+2 level, 1～m-1 module output+2 level, residue module export 0 level；Otherwise, control m module output+ 2 level, k module exports 0 level, 1～m-1 module output+2 level, residue module exports 0 level.
When described total modulating wave is in negative half-cycle, calculate the modulation letter of 1～2k H bridge module according to following rule Number:
1) whenAnd during m=1, control 1～k module and export 0 level；
2) whenAnd during m > 1: if Uek > Ue (m-1), control m-1 module output 0 electricity Flat, k module output-2 level, m～k-1 module export 0 level, residue module output-2 level；Otherwise, m-1 module Export-2 level, k module exports 0 level, m～k-1 module exports 0 level, residue module output-2 level；
3) whenAnd during m=1, control m～k-1 module and export 0 level, mould Group Vk exports-1 level；
4) whenAnd during m > 1, control m～k-1 module and export 0 level, mould Group Vk output-1 level, residue module output-2 level；
5) whenAnd during m=k, control 1～k module output-2 level；
6) whenAnd m is<during k: if Uek>Uem, control m module output 0 electricity Flat, k module output-2 level, m+1～k-1 module export 0 level, residue module output-2 level；Otherwise, No. m is controlled Module exports-2 level, k module exports 0 level, m+1～k-1 module exports 0 level, residue module output-2 level.
Wherein, two stacking triangular carriers in the present embodiment, can be two synchronous stacking triangular carriers, it is possible to Think the stacking triangular carrier of two antiphases.
For correctness and the effectiveness of the checking program, this drain current suppressing scheme is emulated.Simulation parameter is as follows: Using the single-phase non-isolated cascaded H-bridges inverter with 4 H bridge modules, DC side command voltage is 35V, grid voltage amplitude For 110V, frequency is 50Hz, and filter inductance is 1mH, and the parasitic capacitance of each photovoltaic battery panel is 10nF.Can obtain after emulation The parasitic capacitor voltage of each H bridge module as shown in Figure 5 and leakage current waveform, it can be seen that after using the program, although each H The parasitic capacitor voltage amplitude of bridge module is different, but the high fdrequency component of the parasitic capacitor voltage of each H bridge module is suppressed, and And leakage current virtual value is 0.8mA after system stability, fully meet grid connection security standard.
Additionally, the embodiment of the invention also discloses the drain current suppressing device of a kind of single-phase non-isolated cascaded H-bridges inverter, Described single-phase non-isolated cascaded H-bridges inverter is formed by 1～2k H bridge module cascade, i H bridge module and 2k-i+1 H bridge mould Block is collectively referred to as a module, i=1, and 2 ..., k；Described device includes:
Acquiring unit 100, for obtaining the DC voltage of each H bridge module；
First computing unit 200, for according to the DC voltage got, being calculated two H bridge moulds in each module The DC voltage error sum of block；
Second computing unit 300, for following the mould that the DC voltage error sum making internal two H bridge modules is the biggest Group obtains the biggest output, makes the output of two H bridge modules in same module keep equal and make total parasitic capacitance The principle of voltages keep constant, calculates the modulated signal of each H bridge module；
Output unit 400, for being sent to the H bridge module of correspondence by calculated modulated signal.
Wherein, the second computing unit 300 specifically for:
According to the DC voltage error sum of two H bridge modules order from big to small in each module, will be except k module Outside other modules be respectively defined as 1～k-1 module；
It is calculated the DC voltage sum of two H bridge modules in each module；
The DC voltage sum of two H bridge modules in i module is represented with Udi；Use VrefRepresent that single-phase non-isolated cascades The instantaneous voltage of total modulating wave of H bridge inverter；With Uei represent two H bridge modules of i module DC voltage error it With；Two stacking triangular carriers, and 1 >=Vc2 >=0.5 >=Vc1 >=0 is represented respectively with Vc1 and Vc2；When Time, define described total modulating wave and be positioned at modulating range m+, whenTime, define described total modulating wave and be positioned at Modulating range m-, m=1,2 ..., k；
When described total modulating wave is in positive half period, calculate the modulation letter of 1～2k H bridge module according to following rule Number:
WhenAnd during m=1, control 1～k module and export 0 level；
WhenAnd 1<during m: if Uek>Ue (m-1), control m-1 module export 0 level, k Number module output+2 level, m～k-1 module export 0 level, residue module output+2 level；Otherwise (i.e. Ue (m-1) > Uek > Uem, or Ue (m-1) > Uem > Uek), control m-1 module output+2 level, k module exports 0 level, m～k-1 module Export 0 level, residue module output+2 level；
WhenAnd during m=1, control 1～k-1 module and export 0 level, k mould Group output+1 level；
WhenAnd 1 < during m, control m～k-1 module export 0 level, k module Output+1 level, residue module output+2 level；
WhenAnd during m=k, control 1～k module output+2 level；
WhenAnd m is<during k: if Uek>Uem, control m module and export 0 level, k mould Group output+2 level, 1～m-1 module output+2 level, residue module export 0 level；Otherwise, m module output+2 is controlled Level, k module exports 0 level, 1～m-1 module output+2 level, residue module exports 0 level；
When described total modulating wave is in negative half-cycle, calculate the modulation letter of 1～2k H bridge module according to following rule Number:
WhenAnd during m=1, control 1～k module and export 0 level；
WhenAnd during m > 1: if Uek > Ue (m-1), control m-1 module output 0 electricity Flat, k module output-2 level, m～k-1 module export 0 level, residue module output-2 level；Otherwise, m-1 module Export-2 level, k module exports 0 level, m～k-1 module exports 0 level, residue module output-2 level；
WhenAnd during m=1, control m～k-1 module and export 0 level, module Vk exports-1 level；
WhenAnd during m > 1, control m～k-1 module and export 0 level, module Vk output-1 level, residue module output-2 level；
WhenAnd during m=k, control 1～k module output-2 level；
WhenAnd m is<during k: if Uek>Uem, control m module and export 0 level, k Number module output-2 level, m+1～k-1 module export 0 level, residue module output-2 level；Otherwise, m module is controlled Export-2 level, k module exports 0 level, m+1～k-1 module exports 0 level, residue module output-2 level.
Wherein, said two stacking triangular carrier is two synchronous stacking triangular carriers.
Wherein, said two stacking triangular carrier is the stacking triangular carrier of two antiphases.
In sum, the present invention eliminates common-mode voltage and differential mode voltage pair by making total parasitic capacitor voltage keep constant The impact of leakage current, thus effectively inhibit leakage current.Additionally, the present invention also follows the DC side making internal two H bridge modules The biggest module of voltage error sum obtain the biggest output and make same module in the output of two H bridge modules Keep equal principle, calculate the modulated signal of each H bridge module, to avoid the output of each H bridge module to exist bigger Difference, thus improve system generating efficiency.
In this specification, each embodiment uses the mode gone forward one by one to describe, and what each embodiment stressed is and other The difference of embodiment, between each embodiment, identical similar portion sees mutually.For device disclosed in embodiment For, owing to it corresponds to the method disclosed in Example, so describe is fairly simple, relevant part sees method part and says Bright.
Described above to the disclosed embodiments, makes professional and technical personnel in the field be capable of or uses the present invention. Multiple amendment to these embodiments will be apparent from for those skilled in the art, as defined herein General Principle can realize in the case of without departing from the spirit or scope of the embodiment of the present invention in other embodiments.Therefore, The embodiment of the present invention is not intended to be limited to the embodiments shown herein, and be to fit to principles disclosed herein and The widest scope that features of novelty is consistent.

Claims (8)

1. the drain current suppressing method of a single-phase non-isolated cascaded H-bridges inverter, it is characterised in that described single-phase non-isolated level Connection H bridge inverter is formed by 1～2k H bridge module cascade, and No. i is collectively referred to as a module with 2k-i+1 H bridge module, i=1, 2,…,k；Described method includes:
Obtain the DC voltage of each H bridge module；
According to the DC voltage got, it is calculated the DC voltage error sum of two H bridge modules in each module；
Follow the module making the DC voltage error sum of internal two H bridge modules the biggest to obtain the biggest output, make In same module, the output of two H bridge modules keeps equal and makes total parasitic capacitor voltage keep constant principle, calculates The modulated signal of each H bridge module；
Calculated modulated signal is sent to the H bridge module of correspondence.
Method the most according to claim 1, it is characterised in that described in follow the DC side electricity making internal two H bridge modules Hold up the biggest module of poor sum to obtain the biggest output, make the output of two H bridge modules in same module keep Equal and make total parasitic capacitor voltage keep constant principle, calculate the modulated signal of each H bridge module, including:
According to the DC voltage error sum of two H bridge modules order from big to small in each module, will be except described k module Outside other modules be respectively defined as 1～k-1 module, wherein, described k module refers to No. k and k+1 H bridge mould The module of block；
It is calculated the DC voltage sum of two H bridge modules in each module；
The DC voltage sum of two H bridge modules in i module is represented with Udi；Use VrefRepresent single-phase non-isolated cascaded H-bridges The instantaneous voltage of total modulating wave of inverter；The DC voltage error sum of two H bridge modules of i module is represented with Uei；Point Do not represent two stacking triangular carriers, and 1 >=Vc2 >=0.5 >=Vc1 >=0 with Vc1 and Vc2；WhenTime, fixed The described total modulating wave of justice is positioned at modulating range m+, whenTime, define described total modulating wave and be positioned at modulator zone Between m-, m=1,2 ..., k；
When described total modulating wave is in positive half period, according to the modulated signal of following rule calculating 1～2k H bridge module:
WhenAnd during m=1, control 1～k module and export 0 level；
WhenAnd 1<during m: if Uek>Ue (m-1), control m-1 module export 0 level, k module Output+2 level, m～k-1 module export 0 level, residue module output+2 level；Otherwise (i.e. Ue (m-1) > Uek > Uem, or Ue (m-1) > Uem > Uek), control m-1 module output+2 level, k module exports 0 level, m～k-1 module output 0 electricity Flat, residue module output+2 level；
WhenAnd during m=1, controlling 1～k-1 module, to export 0 level, k module defeated Go out+1 level；
WhenAnd 1 < during m, control m～k-1 module export 0 level, k module output+ 1 level, residue module output+2 level；
WhenAnd during m=k, control 1～k module output+2 level；
WhenAnd m is<during k: if Uek>Uem, controlling m module, to export 0 level, k module defeated Go out+2 level, 1～m-1 module output+2 level, residue module exports 0 level；Otherwise, control m module output+2 level, K module exports 0 level, 1～m-1 module output+2 level, residue module exports 0 level；
When described total modulating wave is in negative half-cycle, according to the modulated signal of following rule calculating 1～2k H bridge module:
WhenAnd during m=1, control 1～k module and export 0 level；
WhenAnd during m > 1: if Uek > Ue (m-1), control m-1 module export 0 level, No. k Module output-2 level, m～k-1 module export 0 level, residue module output-2 level；Otherwise, m-1 module output-2 Level, k module export 0 level, m～k-1 module exports 0 level, residue module output-2 level；
WhenAnd during m=1, controlling m～k-1 module, to export 0 level, module Vk defeated Go out-1 level；
WhenAnd during m > 1, controlling m～k-1 module, to export 0 level, module Vk defeated Go out-1 level, residue module output-2 level；
WhenAnd during m=k, control 1～k module output-2 level；
WhenAnd m is<during k: if Uek>Uem, control m module and export 0 level, k mould Group output-2 level, m+1～k-1 module export 0 level, residue module output-2 level；Otherwise, control m module output- 2 level, k module export 0 level, m+1～k-1 module exports 0 level, residue module output-2 level.
Method the most according to claim 2, it is characterised in that said two stacking triangular carrier is two synchronous layers Folded triangular carrier.
Method the most according to claim 2, it is characterised in that said two stacking triangular carrier is the layer of two antiphases Folded triangular carrier.
5. the drain current suppressing device of a single-phase non-isolated cascaded H-bridges inverter, it is characterised in that described single-phase non-isolated level Connection H bridge inverter is formed by 1～2k H bridge module cascade, and i H bridge module and 2k-i+1 H bridge module are collectively referred to as a module, i =1,2 ..., k；Described device includes:
Acquiring unit, for obtaining the DC voltage of each H bridge module；
First computing unit, for according to the DC voltage that gets, is calculated the direct current of two H bridge modules in each module Side voltage error sum；
Second computing unit, obtains for the module following the DC voltage error sum making internal two H bridge modules the biggest The biggest output, the output of two H bridge modules in same module is made to keep equal and make total parasitic capacitor voltage protect Hold constant principle, calculate the modulated signal of each H bridge module；
Output unit, for being sent to the H bridge module of correspondence by calculated modulated signal.
Device the most according to claim 5, it is characterised in that described second computing unit specifically for:
According to the DC voltage error sum of two H bridge modules order from big to small in each module, will be except described k module Outside other modules be respectively defined as 1～k-1 module, wherein, described k module refers to No. k and k+1 H bridge mould The module of block；
It is calculated the DC voltage sum of two H bridge modules in each module；
The DC voltage sum of two H bridge modules in i module is represented with Udi；Use VrefRepresent single-phase non-isolated cascaded H-bridges The instantaneous voltage of total modulating wave of inverter；The DC voltage error sum of two H bridge modules of i module is represented with Uei；Point Do not represent two stacking triangular carriers, and 1 >=Vc2 >=0.5 >=Vc1 >=0 with Vc1 and Vc2；WhenTime, fixed The described total modulating wave of justice is positioned at modulating range m+, and works asTime, define described total modulating wave and be positioned at modulation Interval m-, m=1,2 ..., k；
When described total modulating wave is in positive half period, according to the modulated signal of following rule calculating 1～2k H bridge module:
WhenAnd during m=1, control 1～k module and export 0 level；
WhenAnd 1<during m: if Uek>Ue (m-1), control m-1 module export 0 level, k module Output+2 level, m～k-1 module export 0 level, residue module output+2 level；Otherwise (i.e. Ue (m-1) > Uek > Uem, or Ue (m-1) > Uem > Uek), control m-1 module output+2 level, k module exports 0 level, m～k-1 module output 0 electricity Flat, residue module output+2 level；
WhenAnd during m=1, controlling 1～k-1 module, to export 0 level, k module defeated Go out+1 level；
WhenAnd 1 < during m, control m～k-1 module export 0 level, k module output + 1 level, residue module output+2 level；
WhenAnd during m=k, control 1～k module output+2 level；
WhenAnd m is<during k: if Uek>Uem, controlling m module, to export 0 level, k module defeated Go out+2 level, 1～m-1 module output+2 level, residue module exports 0 level；Otherwise, control m module output+2 level, K module exports 0 level, 1～m-1 module output+2 level, residue module exports 0 level；
When described total modulating wave is in negative half-cycle, according to the modulated signal of following rule calculating 1～2k H bridge module:
WhenAnd during m=1, control 1～k module and export 0 level；
WhenAnd during m > 1: if Uek > Ue (m-1), control m-1 module export 0 level, No. k Module output-2 level, m～k-1 module export 0 level, residue module output-2 level；Otherwise, m-1 module output-2 Level, k module export 0 level, m～k-1 module exports 0 level, residue module output-2 level；
WhenAnd during m=1, controlling m～k-1 module, to export 0 level, module Vk defeated Go out-1 level；
WhenAnd during m > 1, controlling m～k-1 module, to export 0 level, module Vk defeated Go out-1 level, residue module output-2 level；
WhenAnd during m=k, control 1～k module output-2 level；
WhenAnd m is<during k: if Uek>Uem, control m module and export 0 level, k mould Group output-2 level, m+1～k-1 module export 0 level, residue module output-2 level；Otherwise, control m module output- 2 level, k module export 0 level, m+1～k-1 module exports 0 level, residue module output-2 level.
Device the most according to claim 6, it is characterised in that said two stacking triangular carrier is two synchronous layers Folded triangular carrier.
Device the most according to claim 6, it is characterised in that said two stacking triangular carrier is the layer of two antiphases Folded triangular carrier.
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