CN106298802A - A kind of LTPS array base palte and manufacture method, display floater - Google Patents
A kind of LTPS array base palte and manufacture method, display floater Download PDFInfo
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- CN106298802A CN106298802A CN201610674042.2A CN201610674042A CN106298802A CN 106298802 A CN106298802 A CN 106298802A CN 201610674042 A CN201610674042 A CN 201610674042A CN 106298802 A CN106298802 A CN 106298802A
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- semiconductor layer
- cushion
- layer
- array base
- sheet material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
Abstract
The present invention provides a kind of LTPS array base palte and manufacture method, display floater, and the method includes: provide the matrix with semiconductor layer；Forming the second cushion in semiconductor layer surface, the second cushion is for ensureing that foreign ion is injected into the top layer of semiconductor layer；The matrix comprising the second cushion carries out channel doping, implanting impurity ion.The present invention can reduce the situation that between NTFT and PTFT occurred in prior art LTPS technique, threshold voltage difference diminishes, and improves the reliability of TFT device.
Description
Technical field
The present invention relates to Display Technique field, be specifically related to a kind of LTPS (Low Temperature Poly-silicon,
Low temperature polycrystalline silicon) array base palte and manufacture method, display floater.
Background technology
Use the liquid crystal indicator of LTPS technique by its higher electron mobility, high aperture, high-resolution, anti-
Answer the advantages such as speed is fast, high brightness, low-power consumption, the most become the study hotspot of field of liquid crystal display.But LTPS making technology
Complicated, it is impossible to reduce production cost, the most accurate costliness of equipment.Save light shield operation and can save Tact Time (during beat
Between) and the cost such as photoresistance, the most each factory the most actively studies and uses the operation saving lampshade to reduce production cost, makes production capacity maximum
Change.
But this technology there is also defect, in TFT manufacture process, need formed NTFT and PTFT, need further exist for by
The threshold voltage of NTFT and PTFT regulates symmetry as far as possible, and increases the threshold voltage difference reliability with raising TFT, based on saving
After CHD (Channel Doping, the channel doping) processing procedure of the LTPS technique after the improvement of light shield operation, threshold value between NTFT and PTFT
Voltage difference reduces, and this phenomenon is unfavorable for the driving of CMOS, can reduce the reliability of TFT device.
Summary of the invention
In view of this, the present invention provides a kind of LTPS array base palte and manufacture method, display floater, to reduce based on saving
The situation that between NTFT and PTFT occurred in the LTPS technique after the improvement of light shield operation, threshold voltage difference diminishes, thus improve TFT
The reliability of device.
The present invention provides the manufacture method of a kind of LTPS array base palte, including: the matrix with semiconductor layer is provided；Half
Conductor layer surface forms the second cushion, and the second cushion is for ensureing that foreign ion is injected into the top layer of semiconductor layer；?
Channel doping, implanting impurity ion is carried out on the matrix of two cushions.
Wherein, form the second cushion in semiconductor layer surface to include: form silicon oxide (SiO in semiconductor layer surfacex)
Layer, silicon nitride (SiNx) layer or both combinations.
Silicon oxide (SiO is formed in semiconductor layer surfacex) layer, silicon nitride (SiNx) layer can use CVD technique, plasma
Chemical gaseous phase deposition (Plasma Enhanced Chemical vapor deposition, PECVD), sputtering, vacuum evaporation or
Low pressure gas phase deposition forms silicon oxide (SiO in described semiconductor layer surfacex) method such as layer, silicon nitride (SiNx) layer, but do not limit
In this.
The matrix with semiconductor layer is provided to include: to provide substrate sheet material；The first cushion formed on substrate sheet material；
Forming drain electrode and source electrode, the metal routing L of TFT between the first cushion and semiconductor layer, wherein TFT includes NTFT and PTFT；
Drain electrode and source electrode are formed semiconductor layer.
Described foreign ion is p type impurity ion, such as: boron, indium, gallium plasma.
The present invention provides a kind of LTPS array base palte, including: the substrate sheet material of sequentially stacking, semiconductor layer, the second buffering
Layer；Semiconductor layer includes that foreign ion, foreign ion are positioned at the region away from described substrate sheet material of semiconductor layer.
Wherein, LTPS array base palte farther includes: the first cushion between substrate sheet material and semiconductor layer；It is formed at
The drain electrode of the TFT between the first cushion and semiconductor layer and source electrode, metal routing L, wherein TFT includes NTFT and PTFT；Formed
Semiconductor layer in drain electrode and source electrode；The second cushion being formed on semiconductor layer.
The present invention provides a kind of LTPS display floater, including: the first matrix being oppositely arranged and the second matrix, the second matrix
Including the substrate sheet material of sequentially stacking, semiconductor layer, the second cushion；Semiconductor layer includes that foreign ion, foreign ion are positioned at
The region away from described substrate sheet material of semiconductor layer.
Wherein, LTPS display floater, farther include: the first cushion between substrate sheet material and semiconductor layer；Formed
The drain electrode of the TFT between the first cushion and described semiconductor layer and source electrode, metal routing L, wherein TFT include NTFT and
PTFT；It is formed at the semiconductor layer on drain electrode and source electrode；The second cushion being formed on semiconductor layer.
The LTPS array base palte of the present invention and manufacture method, display floater, by existing based on save light shield operation
LTPS technique after improvement is improved again, forms the second cushion in semiconductor layer surface；At the base including the second cushion
Channel doping, implanting impurity ion is carried out on body.Wherein, the second cushion ensures that a large amount of foreign ions are injected into semiconductor layer
Top layer, improves its contribution to NTFT threshold voltage, thus reduces existing based on saving the LTPS technique after light shield operation is improved
The situation that between NTFT and PTFT of middle appearance, threshold voltage difference diminishes, improves the reliability of TFT device.
Accompanying drawing explanation
Fig. 1 is the flow chart of LTPS manufacturing method of array base plate one embodiment of the present invention；
Fig. 2 be the present invention LTPS manufacturing method of array base plate one embodiment in the showing of matrix with polysilicon layer is provided
It is intended to；
Fig. 3 be the present invention LTPS manufacturing method of array base plate one embodiment in carry out the schematic diagram of channel doping；
Fig. 4 is the channel doping principle schematic of LTPS manufacturing method of array base plate one embodiment of prior art；
Fig. 5 is the channel doping principle schematic of LTPS manufacturing method of array base plate one embodiment of the present invention；
Fig. 6 is the structural representation of the LTPS array base palte first embodiment of the present invention；
Fig. 7 is the structural representation of LTPS array base palte second embodiment of the present invention；
Fig. 8 is the structural representation of display floater one embodiment of the present invention.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Describe wholely.
Fig. 1 is the flow chart of the manufacture method of LTPS array base palte one embodiment of the present invention.As it is shown in figure 1, this enforcement
The manufacture method of example comprises the following steps:
Step 11: the matrix with semiconductor layer is provided.
Described matrix 21, for forming the LTPS array base palte of display panels, can be glass basis, plastic substrate
Or bendable matrix.As in figure 2 it is shown, matrix 21 can also include substrate sheet material 211, be formed on substrate sheet material 211 transparent
The first cushion (Buffer layer) 212, the drain D of TFT being formed on the first cushion 212 and source S, metal walk
Line L, wherein TFT includes NTFT and PTFT, the polysilicon layer 213 being formed on drain electrode and source electrode.
Wherein, described semiconductor layer is polysilicon layer；
Wherein, the first cushion 212 is silicon oxide (SiOx) layer, silicon nitride (SiNx) layer or both combination, first delay
Rush the layer 212 impurity in preventing substrate sheet material 211 to diffuse up in subsequent handling and to affect the low temperature that formed afterwards many
The quality of polycrystal silicon film.Silicon oxide (SiOx) layer and silicon nitride (SiNx) layer can use CVD technique, PCVD
(Plasma Enhanced Chemical vapor deposition, PECVD) technique is formed, it is also possible to use sputtering, vacuum
The methods such as evaporation or low pressure gas phase deposition, but it is not limited to this.
Polysilicon layer becomes the detailed process of drain D and source S, includes but not limited to: formed in drain D and source S
One polysilicon layer 213, polysilicon layer 213 covers drain D and source S, metal routing L.
Wherein, the present embodiment can utilize light shield to be exposed the metal level being formed on cushion 212, and in exposure
After carry out developing, the pattern process such as etching to obtain drain D and source S, wherein available containing phosphoric acid, nitric acid, acetic acid and
Metal level is etched by the etching solution of deionized water, it would however also be possible to employ dry etching.Wherein, described metal level can be gold
Belong to, such as aluminum, titanium, chromium, steel, or metal-oxide, such as titanium oxide, or metal alloy or other conductive material are constituted.
The present embodiment can also be obtained by other means drain D and the source S of TFT, for example with CVD technique, PECVD
The methods such as technique sputtering, vacuum evaporation or low pressure gas phase deposition are directly formed on described first cushion 212 has predetermined figure
The drain D of case and source S.
Step 12: form the second cushion in described semiconductor layer surface.
As it is shown on figure 3, the second cushion 22 is silicon oxide (SiOx) layer, silicon nitride (SiNx) layer or both combination；The
Two cushions 22, for ensureing that described foreign ion is injected into the top layer of polysilicon layer, improve foreign ion to NTFT threshold voltage
Contribution, increase the threshold voltage difference between NTFT and PTFT, improve the reliability of TFT；Silicon oxide (SiOx) layer and silicon nitride
(SiNx) layer can use CVD technique, PCVD (Plasma Enhanced Chemical vapor
Deposition, PECVD) technique formation, it is also possible to the methods such as employing sputtering, vacuum evaporation or low pressure gas phase deposition, but not only
It is limited to this.
Step 13: carry out channel doping on the described matrix comprising described second cushion, inject described foreign ion.
As it is shown in figure 5, comprise 21 and second the matrix of cushion 22 carry out ditch away from the matrix skin of substrate sheet material 211
Road adulterates, implanting impurity ion, and makes substantial amounts of foreign ion be injected into the close of polysilicon layer 213 via the second cushion 22
Region/the top layer of the second cushion 22, thus improve the contribution to NTFT threshold voltage of the foreign ion of injection, increase NTFT and
Threshold voltage difference between PTFT, improves the reliability of TFT.
Channel doping can be carried out, such as by ion implantation technique and device: ion implantation apparatus.
The foreign ion injected is p type impurity ion (acceptor impurity ion), such as: boron, indium, gallium plasma.
The principle of channel doping is as shown in Figure 4 and Figure 5: the ion that channel doping injects only is injected into CMOS's and PMOS
Depletion layer just can have contribution to its threshold voltage.
Wherein, in prior art, the threshold voltage contribution of p type impurity ion pair NTFT that channel doping injects is compared to
The principle that the threshold voltage contribution of PTFT is low is as follows: PMOS depletion layer 402 Breadth Maximum increases with implantation dosage and increases, and injects
Its depletion layer 402 of the substantially all injection of boron ion 401, thus implantation dosage is substantially all contributes to threshold voltage；And NMOS
Depletion layer 402 Breadth Maximum increases with implantation dosage and reduces.As shown in Figure 4, the Breadth Maximum of NMOS depletion layer 402 is less than note
Entering the degree of depth of foreign ion, the implantation dosage remaining in depletion layer 402 the most on a small quantity has contribution to threshold voltage, thus it is right
The threshold voltage contribution of NTFT is little.
The present invention carries out channel doping on the matrix 400 comprising the second cushion 404, injects boron ion 401, it is ensured that note
The boron ion 401 entered is injected into the top layer of polysilicon layer 403.As it is shown in figure 5, the substantially all injection of boron ion 401 injected
The depletion layer 402 of NMOS and PMOS, improves its contribution to NTFT threshold voltage, the boron ion 401 of the injection threshold to NTFT
Threshold voltage contribution is consistent with the threshold voltage of PTFT, thus increases threshold voltage difference between NTFT and PTFT, improves the reliable of TFT
Property.
Step 14: remove described second cushion after described channel doping.
The matrix comprising the second cushion 22 carries out channel doping, Fluohydric acid. after implanting impurity ion, can be used clear
Washing machine removes the second cushion 22, removes the basal body structure after the second cushion 22 as shown in Figure 2.
In other embodiments, described second cushion, wherein the second buffering can also be retained after described channel doping
Layer can be that existing insulating barrier is formed, it is also possible to is that the material as described by previous embodiment is formed.
The embodiment of the present invention provides a kind of LTPS array base palte, such as Fig. 6, including the substrate sheet material 211, many of: sequentially stacking
Crystal silicon layer 213；Described polysilicon layer 213 include foreign ion, described foreign ion be positioned at described polysilicon layer away from described
The region of substrate sheet material.
Wherein, LTPS array base palte farther includes: substrate sheet material 211 and being sequentially formed on substrate sheet material 211
Cushion 212, the drain D of TFT and source S, metal routing L, wherein TFT includes NTFT and PTFT, polysilicon layer 213, insulation
Layer 23, grid layer 24, flatness layer 25, common electrode layer 26, passivation layer 27, pixel electrode 28, contact hole O.
Wherein, the manufacturing process of LTPS array base palte includes: form the second cushion 22 on polysilicon layer 213 surface, the
Two cushions 22 are for ensureing that foreign ion is injected into the top layer of polysilicon layer 213, and principle is as shown in Figure 5；Delay comprising second
Rush and on the matrix of layer 22, carry out channel doping, implanting impurity ion, as shown in Figure 3；The second buffering is removed after institute's channel doping
Layer 22.Certainly, the second cushion 22 is retained also possible.
Wherein, the present embodiment applies to the array base palte of NMOS or PMOS, in other embodiments, it is also possible to application
In CMOS-type array base palte.
The embodiment of the present invention provides a kind of LTPS array base palte, such as Fig. 7, including the substrate sheet material 211, many of: sequentially stacking
Crystal silicon layer the 213, second cushion 22；Described polysilicon layer 213 includes that foreign ion, described foreign ion are positioned at described polysilicon
The region away from described substrate sheet material of layer.
Wherein, LTPS array base palte farther includes: substrate sheet material 211 and being sequentially formed on substrate sheet material 211
First cushion 212, the drain D of TFT and source S, metal routing L, wherein TFT include NTFT and PTFT, polysilicon layer 213,
Second cushion 22, insulating barrier 23, grid layer 24, flatness layer 25, common electrode layer 26, passivation layer 27, pixel electrode 28, contact
Hole O.
Wherein, the second cushion 22 is silicon oxide (SiOx) layer, silicon nitride (SiNx) layer or both combination；Second buffering
Layer 22, for ensureing that described foreign ion is injected into the top layer of polysilicon layer, improves the foreign ion tribute to NTFT threshold voltage
Offer, increase the threshold voltage difference between NTFT and PTFT, improve the reliability of TFT；Silicon oxide (SiOx) layer and silicon nitride (SiNx)
Layer can use CVD technique, PCVD (Plasma Enhanced Chemical vapor
Deposition, PECVD) technique formation, it is also possible to the methods such as employing sputtering, vacuum evaporation or low pressure gas phase deposition, but not only
It is limited to this.
Wherein, the manufacturing process of LTPS array base palte includes: form the second cushion on described polysilicon layer 213 surface
22, the second cushion 22 is for ensureing that foreign ion is injected into the top layer of polysilicon layer 213, and principle is as shown in Figure 5；Comprising
Channel doping is carried out on the matrix of two cushions 22, implanting impurity ion, as shown in Figure 3.
Wherein, the present embodiment applies to the array base palte of NMOS or PMOS, in other embodiments, it is also possible to application
In CMOS-type array base palte.
The embodiment of the present invention further provides for display floater and the liquid crystal display that a kind of LTPS array forms substantially, as
Shown in Fig. 8, this display floater or liquid crystal display include bias light the 800, first Polarizer the 801, first glass substrate 802,
LTPS array base palte 803, liquid crystal 804, sealing gasket 805, ITO electrode 806, protecting film 807, color filter 808, glass substrate 809,
Second Polarizer 810.Specifically, the array base palte during this LTPS array base palte 803 is such as each embodiment above-mentioned.
Wherein, in LTPS array base palte and display device one embodiment, embodiment and above-mentioned LTPS array base palte
Manufacture method embodiment be similar to, have identical useful consequence with it.
On this basis, the foregoing is only embodiments of the invention, not thereby limit the scope of the claims of the present invention, all
It is the equivalent structure utilizing present specification and accompanying drawing content to be made or equivalence flow process conversion, technical characteristic between the most each embodiment
Be combined with each other, or be directly or indirectly used in other relevant technical fields, be the most in like manner included in the patent protection of the present invention
In the range of.
Claims (10)
1. the manufacture method of a LTPS array base palte, it is characterised in that including:
The matrix with semiconductor layer is provided；
Forming the first cushion in described semiconductor layer surface, it is described that described first cushion is used for ensureing that foreign ion is injected into
The top layer of semiconductor layer；
Through described first cushion to carrying out channel doping on described matrix, inject described foreign ion to described quasiconductor
In.
Method the most according to claim 1, it is characterised in that farther include:
Remove described first cushion.
Method the most according to claim 1, it is characterised in that described form the first cushion in described semiconductor layer surface
Including:
Silicon oxide (SiO is formed in described semiconductor layer surfacex) layer, silicon nitride (SiNx) layer or both combination.
Method the most according to claim 2, it is characterised in that described at described semiconductor layer surface formation silicon oxide
(SiOx) layer, silicon nitride (SiNx) layer include:
Use CVD technique, PCVD (Plasma Enhanced Chemicalvapor deposition,
PECVD), sputtering, vacuum evaporation or low pressure gas phase deposition form silicon oxide (SiO in described semiconductor layer surfacex) layer, silicon nitride
(SiNx) layer or both combinations.
Method the most according to claim 1, it is characterised in that described offer has the matrix of semiconductor layer and includes:
Substrate sheet material is provided；
Described substrate sheet material forms the second cushion；
Described second cushion is formed drain electrode and source electrode, the metal routing L of TFT, wherein said TFT include NTFT and
PTFT；
Described drain electrode and described source electrode form described semiconductor layer.
Method the most according to claim 1, it is characterised in that described foreign ion is p type impurity ion.
7. a LTPS array base palte, it is characterised in that including:
The substrate sheet material of sequentially stacking, semiconductor layer；
Described semiconductor layer include foreign ion, described foreign ion be positioned at described semiconductor layer away from described substrate sheet material
Region.
LTPS array base palte the most according to claim 7, it is characterised in that
It is formed at the first cushion of described semiconductor layer.
LTPS array base palte the most according to claim 7, it is characterised in that farther include:
The second cushion between described substrate sheet material and described semiconductor layer；
The drain electrode of the TFT being formed between described second cushion and described semiconductor layer and source electrode, metal routing L, wherein TFT bag
Include NTFT and PTFT.
10. a LTPS display floater, it is characterised in that including:
The first matrix being oppositely arranged and the second matrix, described second matrix includes the substrate sheet material of sequentially stacking, semiconductor layer；
Described semiconductor layer include foreign ion, described foreign ion be positioned at described semiconductor layer away from described substrate sheet material
Region.
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| CN201610674042.2A CN106298802B (en) | 2016-08-16 | 2016-08-16 | A kind of LTPS array substrate and manufacturing method, display panel |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019109488A1 (en) * | 2017-12-06 | 2019-06-13 | 武汉华星光电半导体显示技术有限公司 | Transistor and manufacturing method therefor |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020047825A1 (en) * | 1997-08-29 | 2002-04-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| CN1573843A (en) * | 2003-06-05 | 2005-02-02 | 三星Sdi株式会社 | Flat panel display device with polycrystalline silicon thin film transistor |
| CN1815740A (en) * | 2004-12-16 | 2006-08-09 | 三星电子株式会社 | Thin film transistor, inverter, logic device, and method of manufacturing semiconductor device |
| CN103779420A (en) * | 2011-08-23 | 2014-05-07 | 广东中显科技有限公司 | Polycrystalline silicon thin-film transistor with bridging grain structure |
-
2016
- 2016-08-16 CN CN201610674042.2A patent/CN106298802B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020047825A1 (en) * | 1997-08-29 | 2002-04-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| CN1573843A (en) * | 2003-06-05 | 2005-02-02 | 三星Sdi株式会社 | Flat panel display device with polycrystalline silicon thin film transistor |
| CN1815740A (en) * | 2004-12-16 | 2006-08-09 | 三星电子株式会社 | Thin film transistor, inverter, logic device, and method of manufacturing semiconductor device |
| CN103779420A (en) * | 2011-08-23 | 2014-05-07 | 广东中显科技有限公司 | Polycrystalline silicon thin-film transistor with bridging grain structure |
| CN103779391A (en) * | 2011-08-23 | 2014-05-07 | 广东中显科技有限公司 | Polycrystalline silicon thin film with bridging grain structure and preparation method thereof |
| CN103779209A (en) * | 2011-08-23 | 2014-05-07 | 广东中显科技有限公司 | Method for preparing polycrystalline silicon thin-film transistor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019109488A1 (en) * | 2017-12-06 | 2019-06-13 | 武汉华星光电半导体显示技术有限公司 | Transistor and manufacturing method therefor |
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