CN106298714A - Semiconductor structure - Google Patents
Semiconductor structure Download PDFInfo
- Publication number
- CN106298714A CN106298714A CN201510437356.6A CN201510437356A CN106298714A CN 106298714 A CN106298714 A CN 106298714A CN 201510437356 A CN201510437356 A CN 201510437356A CN 106298714 A CN106298714 A CN 106298714A
- Authority
- CN
- China
- Prior art keywords
- semiconductor structure
- groove
- layer
- dielectric layer
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 239000010410 layer Substances 0.000 claims abstract description 94
- 229910000679 solder Inorganic materials 0.000 claims abstract description 54
- 239000012792 core layer Substances 0.000 claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000003466 welding Methods 0.000 claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 abstract description 12
- 238000000034 method Methods 0.000 abstract description 10
- 230000004907 flux Effects 0.000 abstract 3
- 238000005476 soldering Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- 241000208340 Araliaceae Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
The invention provides a semiconductor structure, which comprises a substrate, a plurality of welding pads, a plurality of welding flux layers and an electronic element. The substrate comprises a core layer, a metal layer and a dielectric layer, wherein the metal layer is arranged on the dielectric layer, and the dielectric layer is arranged on the core layer and comprises at least one groove. The bonding pad is disposed on the dielectric layer and electrically connected to the metal layer. The groove is arranged between any two adjacent welding pads. The solder layers are respectively arranged on the solder pads. The electronic element is arranged on the welding pad through the welding flux layer, thereby avoiding the problems of bridging phenomenon and short circuit of the welding flux convex block in the process of reflow soldering and further improving the production yield.
Description
Technical field
The invention relates to a kind of semiconductor structure, and avoid solder to bridge in particular to a kind of
Semiconductor structure.
Background technology
In recent years, along with making rapid progress of electronic technology, and the coming out one after another of high-tech electronic industry,
Electronic product more humane, with better function is constantly weeded out the old and bring forth the new, and towards light, thin, short,
Little trend strides forward.Under this trend, owing to circuit board has, wiring is fine and closely woven, assemble compact and performance
The advantage such as good, therefore circuit board becomes as carrying multiple electronic components (such as: chip) and making this
One of main media that a little electronic components are electrically connected to each other.
Crystal covering type (flip chip) encapsulation is a kind of mode of chip and circuit board package.Have on circuit board
Multiple weld pads, and circuit board can make electrically with chip by the way of the solder that is configured on weld pad is with reflow
Connect.In recent years, owing to the signal of transmission required between electronic component (such as chip) increases day by day,
Therefore the weld pad number having needed for circuit board increases the most day by day, but, the limited space on circuit board, because of
Spacing between this connection pad develops towards micro-spacing (fine pitch).
But, when configuring solder projection on these weld pads and engaging in the way of reflow with chip, this
A little solder projections can present molten condition, owing to these connection pads are to be arranged in micro-spacing because reflow is heated
On the surface of substrate, therefore it is easily caused in reflow process the solder projection in molten condition and occurs bridge joint existing
As and short circuit problem, and the electric connection structure of micro-spacing cannot be provided.It is said that in general, this solder projection
Although usage amount through strict calculating, but, actual when implementing on engineering-environment, still suffered from
Many parameters solder projection will be caused to be heated after overflow, such as heating-up temperature, heat time heating time, material this
The trickle factor such as body, is likely to cause overflow, especially on the substrate of limited space, and the shadow caused
Sound may be bigger.
Summary of the invention
The present invention provides a kind of semiconductor structure, which obviates solder projection and bridge occurs during reflow
The problem connecing phenomenon and short circuit, and then promote production yield.
The semiconductor structure of the present invention includes substrate, multiple weld pad, multiple solder layer and electronic component.
Substrate includes core layer, metal level and dielectric layer, and metal level is arranged on dielectric layer, and dielectric layer is arranged
In core layer and include at least one groove.Weld pad is arranged on dielectric layer and is electrically connected with metal level.
Groove is arranged between wantonly two adjacent weld pads.Solder layer is respectively arranged on weld pad.Electronic component passes through
Solder layer and be arranged on weld pad.
In one embodiment of this invention, the two lateral walls of above-mentioned groove is parallel to each other.
In one embodiment of this invention, the surface of the two lateral walls of above-mentioned groove is matsurface.
In one embodiment of this invention, the distance between the two lateral walls of above-mentioned groove is toward near core
The direction of central layer is gradually reduced.
In one embodiment of this invention, the quantity of at least one above-mentioned groove is multiple, and groove is wherein
Two be arranged between wantonly two adjacent weld pads.
In one embodiment of this invention, the degree of depth of above-mentioned each groove between 10 microns to 50 microns it
Between.
In one embodiment of this invention, above-mentioned each groove exposes core layer.
In one embodiment of this invention, the bottom surface of above-mentioned groove is matsurface.
In one embodiment of this invention, above-mentioned semiconductor structure also includes welding resisting layer, is arranged at dielectric
On layer and expose weld pad.
In one embodiment of this invention, above-mentioned substrate is printed circuit board (PCB).
Based on above-mentioned, arrange between the semiconductor structure of the present invention wantonly two adjacent weld pads on its substrate
There is at least one groove, to utilize the groove between wantonly two adjacent weld pads to extend the solder on weld pad
The layer flow path when molten condition, makes the solder layer on wantonly two adjacent weld pads can the groove of correspondence
And separate, thus wantonly two adjacent weld pads can be greatly reduced and make solder layer thereon because spacing is relatively near
The situation of bridge joint after reflow, therefore, the semiconductor structure of the present invention can have higher production yield.
For the features described above of the present invention and advantage can be become apparent, special embodiment below, and coordinate
Accompanying drawing is described in detail below.
Accompanying drawing explanation
Figure 1A to Fig. 1 E is that the Making programme of a kind of semiconductor structure according to one embodiment of the invention cuts open
Face schematic diagram；
Fig. 2 is the generalized section of a kind of semiconductor structure according to another embodiment of the present invention；
Fig. 3 is the generalized section of a kind of semiconductor structure according to another embodiment of the present invention；
Fig. 4 is the generalized section of a kind of semiconductor structure according to another embodiment of the present invention；
Fig. 5 is the generalized section of a kind of semiconductor structure according to another embodiment of the present invention.
Description of reference numerals:
100,100a～100d: semiconductor structure；
110: substrate；
112: core layer；
112a: core line layer；
114: metal level；
116: dielectric layer；
116a: groove；
116b: matsurface；
120: weld pad；
130: solder bump；
132: solder layer；
140: electronic component；
150: welding resisting layer.
Detailed description of the invention
About addressing other technologies content, feature and effect before the present invention, coordinate with reference to accompanying drawing following
Each embodiment detailed description in, can clearly present.The direction being previously mentioned in following example is used
Language, such as: on " ", D score, "front", "rear", "left", "right" etc., be only ginseng
Examine the direction of accompanying drawing.Therefore, the direction term of use is used to explanation, and is not used for limiting the present invention.
Further, in following examples, same or analogous element will use same or analogous label.
Figure 1A to Fig. 1 E is that the Making programme of a kind of semiconductor structure according to one embodiment of the invention cuts open
Face schematic diagram.The manufacture method of the semiconductor structure of the present embodiment comprises the following steps: first, to refer to
Figure 1A, it is provided that substrate 110, wherein, substrate 110 includes core layer 112, metal level 114 and is situated between
Electric layer 116, and metal level 114 is arranged on dielectric layer 116, dielectric layer 116 is then arranged at core
On layer 112.In the present embodiment, metal forming such as can be pressed on Jie by the manufacture method of metal level 114
In electric layer 116, and this metal forming is carried out patterned process and forms metal level 114 as shown in Figure 1A.
Certainly, the invention is not limited in this.In one embodiment of this invention, substrate 110 can include multiple
Dielectric layer 116 and multiple metal level 114, dielectric layer 116 can be at least provided with in the phase of core layer 112
To on two surfaces, metal level 114 then may be disposed in each dielectric layer 116 and core layer 112, and
Such as it is electrically connected to each other by conducting elements such as vias.Specifically, substrate 110 can be printing
Circuit board (printed circuit board, PCB).Certainly, the present invention be not limiting as substrate 110 kind,
Number of plies and preparation method thereof, it is true that substrate 110 is alternatively glass fibre basal plate, BT (Bismaleimide
Triacine) resin substrate, glass epoxy resin Copper Foil (FR4) substrate or the base of other similar materials
Plate.
Then, refer to Figure 1B, form at least one groove 116a on dielectric layer 116.In this enforcement
In example, form groove 116a method on dielectric layer 116 and can include cut, and, groove 116a
The core layer 112 of lower section can be exposed as shown in Figure 1 C, it is possible to do not expose the core layer 112 of lower section, change sentence
Talking about, groove 116a can run through dielectric layer 116 also can be not through dielectric layer 116.Specifically, each ditch
The degree of depth of groove 116a is about between 10 microns (μm) are to 50 microns.Additionally, the phase of groove 116a
Can be parallel to each other as shown in Figure 1 C to two side.Certainly, the present embodiment only in order to illustrate, this
Bright it is not limiting as the degree of depth of groove, shape and form.
Please continue with reference to Fig. 1 C, form multiple weld pad 120 on dielectric layer 116.Specifically, weld pad
120 electrically connect with metal level 114, and groove 116a is between wantonly two adjacent weld pads 120.Then,
Formation welding resisting layer 150 as shown in Figure 1 C is on dielectric layer 116, and welding resisting layer 150 exposes weld pad 120
And groove 116a.In the present embodiment, welding resisting layer 150 can have multiple opening, and it exposes weldering respectively
Pad 120 and the groove 116a between wantonly two adjacent weld pads 120.
Then, refer to Fig. 1 D, form multiple solder bump 130 on weld pad 120.In the present embodiment,
Forming the solder bump 130 mode on weld pad 120 and can include planting ball or printing, certainly, the present invention is not
As limit.Then, more as shown in figure ip electronic component 140 is set on weld pad 120.In this reality
Executing in example, electronic component 140 can include resistance, electric capacity, inductance, diode, transistor or integrated electricity
Passive device or the active members such as road (IC).
Then, refer to Fig. 1 E, carry out reflow process, form multiple solder with fusion welding block 130
Layer 132, wherein, above-mentioned solder layer 132 is covered each by weld pad 120, in the present embodiment, if accidentally producing
During raw overflow phenomena, the solder layer 132 on wantonly two adjacent weld pads 120 is suitable to prolong the most respectively
Extend the two lateral walls of the groove 116a of correspondence, and separate with corresponding groove 116a.Also
That is, the present embodiment utilizes the groove 116a between wantonly two adjacent weld pads 120 to extend solder
Layer 132, by the flow path of flow down on weld pad 120, makes the solder on wantonly two adjacent weld pads 120
Groove 116a that layer 132 is available corresponding and separate, and then wantonly two adjacent weld pads can be greatly reduced
120 situations making solder layer 132 thereon be prone to bridge joint after reflow because spacing is relatively near.It is said that in general,
The usage amount of this solder layer 132 is all the calculating in engineering, even if producing overflow, its spillway discharge is also
Will not attend the meeting greatly beyond the flow path after extending, so, the system of the semiconductor structure 100 of the present embodiment
I.e. it is substantially completed, and on substrate 110, forms preventative design.
Substrate can be included as referring to figure 1e according to the semiconductor structure 100 produced by above-mentioned manufacture method
110, multiple weld pads 120, multiple solder layer 132 and electronic component 140.In the present embodiment, base
Plate 110 can be printed circuit board (PCB), and it can include core layer 112, metal level 114 and dielectric layer 116,
Wherein, metal level 114 is arranged on dielectric layer 116, and dielectric layer 116 is arranged in core layer 112,
And dielectric layer 116 includes at least one groove 116a.Weld pad 120 is arranged on dielectric layer 116, and with gold
Belong to layer 114 to be electrically connected with.Groove 116a is then arranged between wantonly two adjacent weld pads 120, and,
In the present embodiment, the two lateral walls of groove 116a such as can be parallel to each other.Solder layer 132 is respectively provided with
On weld pad 120.Electronic component 140 is then arranged on weld pad 120 by solder layer 132, and with
It is electrically connected with.Specifically, the solder layer 132 on wantonly two adjacent weld pads 120 is suitable to each extend over
To the two lateral walls of corresponding groove 116a and separate with corresponding groove 116a.
So configured, the semiconductor structure 100 of the present embodiment utilize be positioned at wantonly two adjacent weld pads 120 it
Between groove 116a extend the solder layer 132 flow path when molten condition, make wantonly two adjacent welderings
Solder layer 132 on pad 120 groove 116a that can be corresponding and separate, thus can be greatly reduced and appoint
The situation that solder layer 132 on two adjacent weld pads 120 bridges after reflow, and then quasiconductor can be promoted
The production yield of structure 100.
Fig. 2 is the generalized section of a kind of semiconductor structure according to another embodiment of the present invention.At this
Should be noted that, the semiconductor structure 100 of semiconductor structure 100a and Fig. 1 E of the present embodiment is similar,
Therefore, the present embodiment continues to use element numbers and the partial content of previous embodiment, wherein uses identical mark
Number represent the identical or element of approximation, and eliminate the explanation of constructed content.About omission portion
The explanation divided refers to previous embodiment, and it is no longer repeated for the present embodiment.Below for the present embodiment
The difference of semiconductor structure 100 of semiconductor structure 100a and Fig. 1 E explain.
Refer to Fig. 2, in the present embodiment, the two lateral walls of groove 116a is also parallel to each other, only
The surface of above-mentioned two side is matsurface.So configured, solder layer 132 and groove 116a can be increased further
The contact area of two lateral walls, thus solder layer 132 can be extended further when molten condition along two
The flow path of wall flow and time, make solder layer 132 by having time enough shape under molten condition
Become solid-state, and then can further reduce the solder layer 132 on wantonly two adjacent weld pads 120 after reflow
The probability of bridge joint, and promote the production yield of semiconductor structure 100a further.
Fig. 3 is the generalized section of a kind of semiconductor structure according to another embodiment of the present invention.At this
Should be noted that, the semiconductor structure 100 of semiconductor structure 100b and Fig. 1 E of the present embodiment is similar,
Therefore, the present embodiment continues to use element numbers and the partial content of previous embodiment, wherein uses identical mark
Number represent the identical or element of approximation, and eliminate the explanation of constructed content.About omission portion
The explanation divided refers to previous embodiment, and it is no longer repeated for the present embodiment.Below for the present embodiment
The difference of semiconductor structure 100 of semiconductor structure 100b and Fig. 1 E explain.
Refer to Fig. 3, in the present embodiment, the such as Fig. 3 of the distance between the two lateral walls of groove 116a
Shown in toward being gradually reduced near the direction of core layer 112 and the most as referring to figure 1e parallel to each other.So
Configuration, compared to the semiconductor structure 100 shown in Fig. 1 E, the semiconductor structure 100b of the present embodiment increases
Add the matsurface 116b on the length of the two lateral walls of groove 116a and wall, thus can prolong further
The flow path that long solder layer 132 is dirty along two side when molten condition, and the matsurface on wall
116b has delayed the speed that solder layer 132 flows, and then can further reduce wantonly two adjacent weld pads 120
On the probability that bridges after reflow of solder layer 132, to promote the production yield of semiconductor structure 100b.
Fig. 4 is the generalized section of a kind of semiconductor structure according to another embodiment of the present invention.At this
Should be noted that, the semiconductor structure 100 of semiconductor structure 100c and Fig. 1 E of the present embodiment is similar,
Therefore, the present embodiment continues to use element numbers and the partial content of previous embodiment, wherein uses identical mark
Number represent the identical or element of approximation, and eliminate the explanation of constructed content.About omission portion
The explanation divided refers to previous embodiment, and it is no longer repeated for the present embodiment.Below for the present embodiment
The difference of semiconductor structure 100 of semiconductor structure 100c and Fig. 1 E explain.
Refer to Fig. 4, in the present embodiment, the quantity of the groove 116a of dielectric layer 116 is multiple, its
In, wherein the two of groove 116a are arranged between wantonly two adjacent weld pads 120.It is to say, wantonly two
Two groove 116a it are provided with between adjacent weld pad 120, and, it is positioned at wantonly two adjacent weld pads 120
Between two groove 116a be not attached to each other lead to.So, the solder layer on wantonly two adjacent weld pads 120
132 then can flow in each self-corresponding two groove 116a in reflow process respectively, and via above-mentioned two ditches
The stop of the sidewall of groove 116a and separate, thus the solder on wantonly two adjacent weld pads 120 can be avoided
Layer 132 is the possibility of bridge joint after reflow, and then the production yield of semiconductor structure 100c can be substantially improved.
Fig. 5 is the generalized section of a kind of semiconductor structure according to another embodiment of the present invention.At this
Should be noted that, the semiconductor structure 100 of semiconductor structure 100d and Fig. 1 E of the present embodiment is similar,
Therefore, the present embodiment continues to use element numbers and the partial content of previous embodiment, wherein uses identical mark
Number represent the identical or element of approximation, and eliminate the explanation of constructed content.About omission portion
The explanation divided refers to previous embodiment, and it is no longer repeated for the present embodiment.Below for the present embodiment
The difference of semiconductor structure 100 of semiconductor structure 100d and Fig. 1 E explain.
Refer to Fig. 5, in the present embodiment, the groove 116a of semiconductor structure 100d does not expose core
Layer 112, say, that groove 116a does not run through dielectric layer 116, and, the bottom surface of groove 116a
It is illustrated in figure 5 matsurface 116b.So configured, owing to groove 116a does not expose core layer 112,
Therefore, the core layer 112 below groove 116a still can retain the design of original circuit, say, that core
The upper surface of central layer 112 can have core line layer 112a.Further, the bottom surface of groove 116a is matsurface,
The contact area of solder layer 132 and groove 116a can be increased, thus solder layer 132 can be extended in reflow
Flow path in journey, causes solder layer 132 to make up because groove 116a does not exposes core layer 112
The situation that flow path shortens.Further, in one embodiment of this invention, the opposite sides of groove 116a
Wall and bottom surface can be all matsurface 116b, further to increase connecing of solder layer 132 and groove 116a
Contacting surface is amassed, and extends the solder layer 132 flow path in reflow process.Therefore, partly the leading of the present embodiment
The solder layer 132 that body structure 100d can be greatly reduced on wantonly two adjacent weld pads 120 bridges after reflow
Probability, and promote the production yield of semiconductor structure 100d.
In sum, arrange between the semiconductor structure of the present invention wantonly two adjacent weld pads on its substrate
There is at least one groove, to utilize the groove between wantonly two adjacent weld pads to extend the solder on weld pad
The layer flow path when molten condition, makes the solder layer on wantonly two adjacent weld pads can the groove of correspondence
And separate, thus wantonly two adjacent weld pads can be greatly reduced and make solder layer thereon because spacing is relatively near
The situation of bridge joint after reflow, therefore, the semiconductor structure of the present invention sets owing to having preventative structure
Meter, can have higher production yield.
Last it is noted that various embodiments above is only in order to illustrate technical scheme, rather than right
It limits；Although the present invention being described in detail with reference to foregoing embodiments, this area common
Skilled artisans appreciate that the technical scheme described in foregoing embodiments still can be modified by it,
Or the most some or all of technical characteristic is carried out equivalent；And these amendments or replacement, and
The essence not making appropriate technical solution departs from the scope of various embodiments of the present invention technical scheme.
Claims (10)
1. a semiconductor structure, it is characterised in that including:
Substrate, including core layer, metal level and dielectric layer, described metal level is arranged at described dielectric layer
On, described dielectric layer is arranged in described core layer and includes at least one groove；
Multiple weld pads, are arranged on described dielectric layer and electrically connect with described metal level, and described groove is arranged
Between wantonly two adjacent weld pads；
Multiple solder layers, are respectively arranged on those weld pads；And
Electronic component, is arranged on those weld pads by those solder layers.
Semiconductor structure the most according to claim 1, it is characterised in that relative the two of described groove
Sidewall is parallel to each other.
Semiconductor structure the most according to claim 2, it is characterised in that relative the two of described groove
The surface of sidewall is matsurface.
Semiconductor structure the most according to claim 1, it is characterised in that relative the two of described groove
Distance between sidewall is gradually reduced toward the direction near described core layer.
Semiconductor structure the most according to claim 1, it is characterised in that described at least one groove
Quantity is multiple, and wherein the two of those grooves are arranged between wantonly two adjacent weld pads.
Semiconductor structure the most according to claim 1, it is characterised in that the degree of depth of each described groove
Between 10 microns to 50 microns.
Semiconductor structure the most according to claim 1, it is characterised in that each described groove exposes institute
State core layer.
Semiconductor structure the most according to claim 1, it is characterised in that each described groove does not exposes
Described core layer.
Semiconductor structure the most according to claim 8, it is characterised in that the bottom surface of each described groove
For matsurface.
Semiconductor structure the most according to claim 1, it is characterised in that also include welding resisting layer,
It is arranged on described dielectric layer and exposes those weld pads.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104116984A TWI575686B (en) | 2015-05-27 | 2015-05-27 | Semiconductor structure |
| TW104116984 | 2015-05-27 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106298714A true CN106298714A (en) | 2017-01-04 |
| CN106298714B CN106298714B (en) | 2019-02-19 |
Family
ID=57651083
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510437356.6A Active CN106298714B (en) | 2015-05-27 | 2015-07-23 | Semiconductor structure |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN106298714B (en) |
| TW (1) | TWI575686B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11004819B2 (en) | 2019-09-27 | 2021-05-11 | International Business Machines Corporation | Prevention of bridging between solder joints |
| CN113937010A (en) * | 2021-12-16 | 2022-01-14 | 绍兴中芯集成电路制造股份有限公司 | Method for manufacturing semiconductor device |
| US11264314B2 (en) | 2019-09-27 | 2022-03-01 | International Business Machines Corporation | Interconnection with side connection to substrate |
| US11735529B2 (en) | 2021-05-21 | 2023-08-22 | International Business Machines Corporation | Side pad anchored by next adjacent via |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201228489A (en) * | 2010-11-03 | 2012-07-01 | 3M Innovative Properties Co | Flexible LED device for thermal management and method of making |
| TW201250943A (en) * | 2011-06-09 | 2012-12-16 | Unimicron Technology Corp | Semiconductor package and fabrication method thereof |
| CN103190204A (en) * | 2010-11-03 | 2013-07-03 | 3M创新有限公司 | Flexible LED device with wire bond free die |
| CN203932096U (en) * | 2011-02-18 | 2014-11-05 | 3M创新有限公司 | Flexible light-emitting semiconductor device and for supporting and be electrically connected the flexible article of light-emitting semiconductor device |
-
2015
- 2015-05-27 TW TW104116984A patent/TWI575686B/en active
- 2015-07-23 CN CN201510437356.6A patent/CN106298714B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201228489A (en) * | 2010-11-03 | 2012-07-01 | 3M Innovative Properties Co | Flexible LED device for thermal management and method of making |
| CN103190204A (en) * | 2010-11-03 | 2013-07-03 | 3M创新有限公司 | Flexible LED device with wire bond free die |
| CN203932096U (en) * | 2011-02-18 | 2014-11-05 | 3M创新有限公司 | Flexible light-emitting semiconductor device and for supporting and be electrically connected the flexible article of light-emitting semiconductor device |
| TW201250943A (en) * | 2011-06-09 | 2012-12-16 | Unimicron Technology Corp | Semiconductor package and fabrication method thereof |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11004819B2 (en) | 2019-09-27 | 2021-05-11 | International Business Machines Corporation | Prevention of bridging between solder joints |
| US11264314B2 (en) | 2019-09-27 | 2022-03-01 | International Business Machines Corporation | Interconnection with side connection to substrate |
| US11456269B2 (en) | 2019-09-27 | 2022-09-27 | International Business Machines Corporation | Prevention of bridging between solder joints |
| US11735529B2 (en) | 2021-05-21 | 2023-08-22 | International Business Machines Corporation | Side pad anchored by next adjacent via |
| CN113937010A (en) * | 2021-12-16 | 2022-01-14 | 绍兴中芯集成电路制造股份有限公司 | Method for manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201642417A (en) | 2016-12-01 |
| TWI575686B (en) | 2017-03-21 |
| CN106298714B (en) | 2019-02-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9978705B2 (en) | Semiconductor substrate and semiconductor package structure having the same | |
| CN104956477A (en) | Wiring board | |
| US9629241B2 (en) | Printed circuit board, ball grid array package and wiring method of printed circuit board | |
| TW201318122A (en) | Package carrier, pacakge carrier manufacturing method, package structure for semiconductor device and manufacturing method thereof | |
| CN106298714A (en) | Semiconductor structure | |
| KR20080046021A (en) | Semiconductor chip having a different height bump and semiconductor package including the same | |
| KR20160140184A (en) | Package substrate and method of manufacturing the same | |
| US20090316329A1 (en) | Chip component and method for producing the same and component built-in module and method for producing the same | |
| CN103545286B (en) | Circuit substrate, semiconductor packaging structure and circuit substrate manufacturing process | |
| CN109003959B (en) | A kind of high thermal conductivity encapsulating structure that bonding wire is preforming and its manufacturing method | |
| CN110856375B (en) | Hot-pressing tin-melting welding circuit board and manufacturing method thereof | |
| CN110299295A (en) | Bonding semiconductor packaging method | |
| CN105489580B (en) | Semiconductor substrate and semiconductor package | |
| CN101197344B (en) | Packaging substrate and its manufacturing method | |
| CN101989593A (en) | Packaging substrate as well as manufacturing method and packaging structure thereof | |
| KR102107034B1 (en) | Printed circuit board, semiconductor package having the same and method for manufacturing the same | |
| CN102026498A (en) | Method for manufacturing circuit board, circuit board and chip packaging structure | |
| JP2015225869A (en) | Semiconductor device | |
| JP7283027B2 (en) | printed circuit board | |
| US20180042112A1 (en) | Electronic device | |
| CN110211954A (en) | A kind of multichip packaging structure and its manufacturing method | |
| CN104124180A (en) | Manufacturing method of chip packaging structure | |
| CN103390598A (en) | Semiconductor package and fabrication method thereof | |
| JPH0758244A (en) | Semiconductor package and manufacture thereof | |
| JP6702410B2 (en) | module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |