CN106298656A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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Publication number
CN106298656A
CN106298656A CN201510259513.9A CN201510259513A CN106298656A CN 106298656 A CN106298656 A CN 106298656A CN 201510259513 A CN201510259513 A CN 201510259513A CN 106298656 A CN106298656 A CN 106298656A
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Prior art keywords
layer
grid groove
flatness layer
semiconductor device
device manufacturing
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CN201510259513.9A
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Inventor
杨宗杰
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to CN201510259513.9A priority Critical patent/CN106298656A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)

Abstract

The open a kind of semiconductor device manufacturing method of the present invention, first, it is provided that there is the substrate of first crystal tubular construction and transistor seconds structure.Wherein, first crystal tubular construction has first grid groove, and transistor seconds structure has second grid groove.Then, first grid groove with second grid groove are formed the first workfunction layers, and in the first workfunction layers, forms flatness layer.Afterwards, flatness layer forms patterning photoresist oxidant layer, then etching part is positioned at the flatness layer in transistor seconds structure.Then, after removing patterning photoresist oxidant layer, overall etch flatness layer is until removing be positioned at the flatness layer in transistor seconds structure completely, and retains patterning flatness layer and cover first crystal tubular construction.Finally, the first workfunction layers being positioned in second grid groove is removed.

Description

Semiconductor device manufacturing method
Technical field
The present invention relates to a kind of semiconductor device manufacturing method, especially relate to a kind of there is metal gates Semiconductor device manufacturing method.
Background technology
Along with day by day the reducing of size of semiconductor element, the size of grid structure reduces the most therewith.Therefore, The thickness of gate dielectric also must reduce to avoid element efficiency to be affected.In general, grid is situated between The material of electric layer is typically silicon oxide.Gate dielectric with silicon oxide as material when thickness reduces often Have the phenomenon of leakage current (leakage current).In order to reduce the generation of leakage current, the existing practice It is with high-k (high dielectric constant；High-k) material replacement silicon oxide is used as grid Pole dielectric layer.In the case of using high dielectric constant material as gate dielectric, with polysilicon as material The grid of material can react generation fermi level pinning (Fermi-level pinning) with high dielectric constant material, Thus result in limit voltage (threshold voltage) to increase and affect element efficiency.
Threshold is caused in order to avoid the grid with polysilicon as material can react with high dielectric constant material Voltage increases, and a kind of practice of the prior art is to be used as grid with metal level.But, with metal level During as grid, in follow-up high temperature processing technology, often cause the merit of metal level because temperature is the highest The variation of function, and then element efficiency is impacted.Satisfying this, processing technology can for post tensioned unbonded prestressed concrete (gate last) After completing the annealing of all of high temperature manufacturing process steps such as dopant activation, remove sacrifice grid (dummy gate or replacement gate), to form gate trench, then, inserts required metal, And complete the metal gates of transistor unit, accordingly, it is possible to resolve in preferential (gate first) processing technology of grid The work function drifting problem occurred.But, the step replacing gate fabrication process is considerably complicated, and element It is prone in processing technology produce defect or residue, and affects element function.
Summary of the invention
In view of this, it is an object of the invention to provide a kind of semiconductor device manufacturing method, it simplifies system Make technique, and improve processing technology yield.
For reaching above-mentioned purpose, the present invention provides a kind of semiconductor device manufacturing method, first, it is provided that have First crystal tubular construction and the substrate of transistor seconds structure.Wherein, first crystal tubular construction has first Gate trench, transistor seconds structure has second grid groove.Then, at first grid groove and Two gate trench are formed the first workfunction layers, and is formed smooth in the first workfunction layers Layer, and flatness layer fills up first grid groove and second grid groove.Afterwards, flatness layer forms figure Case photoresist oxidant layer, is positioned at second as mask layer, etching part patterning photoresist oxidant layer Flatness layer on transistor arrangement.Then, after removing patterning photoresist oxidant layer, overall etch is put down Smooth layer is until removing be positioned at the flatness layer in transistor seconds structure completely, and retains patterning flatness layer and cover Cover first crystal tubular construction.Finally, to pattern flatness layer as hard mask layer, remove and be positioned at second The first workfunction layers in gate trench.
In one embodiment of this invention, aforesaid semiconductor device manufacturing method is also included in first grid Before groove and second grid groove form the first workfunction layers, at first grid groove and second Gate trench is formed barrier layer.
In one embodiment of this invention, aforesaid semiconductor device manufacturing method, wherein, overall etch During the step of this flatness layer, expose the barrier layer being positioned in first grid groove.
In one embodiment of this invention, aforesaid semiconductor device manufacturing method, wherein, the first work content When forming the step of flatness layer on number metal level, the thickness of flatness layer is 1900 angstroms.
In one embodiment of this invention, aforesaid semiconductor device manufacturing method, wherein, with patterning Photoresist oxidant layer as mask layer, etching part is positioned at the flatness layer in transistor seconds structure until its Thickness is less than 150 angstroms, and still covers the first workfunction layers.
In one embodiment of this invention, aforesaid semiconductor device manufacturing method, its step also includes moving Except patterning flatness layer, in order to expose the first workfunction layers being positioned in first grid groove.
In one embodiment of this invention, aforesaid semiconductor device manufacturing method, its step is also included in After removing the step of patterning flatness layer, in first grid groove with second grid groove, form the second merit Function metal.
In one embodiment of this invention, aforesaid semiconductor device manufacturing method, wherein, first crystal Tubular construction and transistor seconds structure are fin-shaped field-effect transistor structure.
In one embodiment of this invention, aforesaid semiconductor device manufacturing method, wherein, flatness layer Material comprises light and absorbs oxide (DUO), spin-on glasses (SOG), bottom anti-reflective material (BARC) or sacrifice light absorbing material (SLAM).
For the above and other objects, features and advantages of the present invention can be become apparent, cited below particularly excellent Select embodiment, and the accompanying drawing appended by cooperation, be described in detail below.
Accompanying drawing explanation
Fig. 1 to Fig. 8 is cuing open of the manufacture method of the semiconductor element depicted in the first embodiment of the present invention Face schematic diagram；
Fig. 9 to Figure 13 is the manufacture method of the semiconductor element depicted in the second embodiment of the present invention Generalized section.
Symbol description
10: substrate
101: shallow trench is isolated
102: dielectric layer
103: high dielectric constant layer
104: etching stopping layer
105: sacrifice grid
106: cap rock
107: clearance wall
108: lightly doped drain
109: source/drain
110: contact hole etching stopping layer
120: inner layer dielectric layer
20th: the first district
201: first crystal tubular construction
202: first grid groove
30th: the second district
301: transistor seconds structure
302: second grid groove
410: the first workfunction layers
420: flatness layer
420R: residue flatness layer
421,422: patterning flatness layer
430: patterning photoresist oxidant layer
440: the second workfunction layers
D1, d2, d3, d4: thickness
Detailed description of the invention
For the present invention aforementioned and other technology contents, feature and effect, coordinate with reference to accompanying drawing following A preferred embodiment detailed description in, can clearly present.The side being previously mentioned in following example To term, such as: upper and lower, left and right, front or rear etc., it is only the direction with reference to attached drawings.Cause This, the direction term of use is used to illustrate not for limiting the present invention.
Fig. 1 to Fig. 8 is the manufacture method according to the semiconductor element depicted in the first embodiment of the present invention Generalized section.First, it is provided that substrate 10, e.g. silicon substrate, containing silicon substrate or silicon-coated insulated (silicon-on-insulator, SOI) substrate etc..There is on substrate 10 multiple shallow trench isolation (shallow Trench isolation, STI) 101, shallow trench isolation 101 can have suitable stress.Pass through shallow trench Isolating 101 areas encompassed, definable goes out the first district 20 and the second district 30 being electrically insulated from. Then formed on the substrate 10 in the first district 20 and the second district 30 first crystal tubular construction 201 with Transistor seconds structure 301, first crystal tubular construction 201 and transistor seconds structure 301 can have not Same conductivity type.Such as, in the present embodiment, first crystal tubular construction 201 is P-type transistor, and Transistor seconds structure 301 is then N-type transistor.
In one embodiment of this invention, as it is shown in figure 1, first crystal tubular construction 201 and the second crystal Tubular construction 301 all can comprise dielectric layer 102, high dielectric constant layer 103, etching stopping layer 104, sacrifice Grid 105, cap rock 106, clearance wall (spacer) 107, lightly doped drain (light doped drain, LDD) 108 and source/drain 109.In a preferred embodiment of the invention, dielectric layer 102 is silicon dioxide layer, The dielectric constant of high dielectric constant layer 103 is approximately greater than 4, and it can be rare-earth oxide layer or lanthanum Series metal oxide layer, such as hafnium oxide (hafnium oxide, HfO2), hafnium silicate oxygen compound (hafnium silicon oxide,HfSiO4), hafnium silicate nitrogen oxide (hafnium silicon oxynitride, HfSiON), aluminium oxide (aluminum oxide, Al2O3), lanthana (lanthanum oxide, La2O3)、 Lanthanum aluminate (lanthanum aluminum oxide, LaAlO), tantalum oxide (tantalum oxide, Ta2O5)、 Zirconium oxide (zirconium oxide, ZrO2), Zirconium orthosilicate. oxygen compound (zirconium silicon oxide, ZrSiO4), zirconic acid hafnium (hafnium zirconium oxide, HfZrO), ytterbium oxide (yttrium oxide, Yb2O3), silicon oxide ytterbium (yttrium silicon oxide, YbSiO), zirconium aluminate (zirconium aluminate, ZrAlO), hafnium (hafnium aluminate, HfAlO), aluminium nitride (aluminum nitride, AlN), Titanium oxide (titanium oxide, TiO2), nitrogen zirconium oxide (zirconium oxynitride, ZrON), nitrogen aoxidize Hafnium (hafnium oxynitride, HfON), nitrogen-oxygen-silicon zirconium (zirconium silicon oxynitride, ZrSiON), nitrogen-oxygen-silicon hafnium (hafnium silicon oxynitride, HfSiON), strontium bismuth tantalum pentoxide (strontium bismuth tantalate,SrBi2Ta2O9, SBT), lead zirconate titanate (lead zirconate titanate, PbZrxTi1-xO3, PZT) or barium strontium (barium strontium titanate, BaxSr1-xTiO3, BST), But it is not limited with above-mentioned.
In the present embodiment, etching stopping layer 104 can comprise metal level or metal nitride layer, e.g. Titanium nitride (TiN).Sacrifice grid 105 e.g. polysilicon gate, it is also possible to be by polysilicon layer, amorphous Compound grid combined by silicon (amorphous Si) or germanium layer.Cap rock 106 the most e.g. silicon nitride layer. Clearance wall 107 can be lamination layer structure.In one embodiment, clearance wall 107 can partially or completely be moved Remove so that hole etching stopping layer (contact etch stop layer, CESL) 110 is for first crystal in contact Tubular construction 201 and transistor seconds structure 301 can have preferred stress.Lightly doped drain 108 and Source/drain 109 is then formed with the admixture of debita spissitudo.And in another embodiment, dielectric layer 102 And etching stopping layer 104 then can omit.
First crystal tubular construction 201 and transistor seconds structure 301 still can comprise other semiconductor structures, Such as metal silicide layer (salicide) or with selective epitaxial grow up (selective epitaxial growth, SEG) and formed have hexahedron (hexagon is again sigma Σ) or octahedron (octangon) cross sectional shape Source/drain (not shown), the compression stress of the passage of P-type transistor can be increased, make hole move Speed accelerates, and then increases speed of operation and the usefulness of P-type transistor.
After forming first crystal tubular construction 201 and transistor seconds structure 301, depend on the substrate 10 Sequence forms contact hole etching stopping layer (contact etch stop layer, CESL) 110 and inner layer dielectric layer (inter-layer dielectric, ILD) 120, covers and ties with transistor seconds at first crystal tubular construction 201 On structure 301.In one embodiment, contact hole etching stopping layer 110 can comprise two kinds of different stressor layers It is divided in the first district 20 and the second district 30, and it is brilliant to be covered each by first crystal tubular construction 201 and second Body tubular construction 301 and provide different stress (stress), using as selective stress system (selective strain scheme,SSS)；Contact hole etching stopping layer 110 can be simple layer or composite bed, can be first Apply compression stress on transistor arrangement 201 and in transistor seconds structure 301, apply stretching stress.
As in figure 2 it is shown, then carry out planarizing processing technology, such as chemical-mechanical planarization (chemical Mechanical polish, CMP) processing technology or etch-back processing technology or a combination of both, with sequentially Remove the inner layer dielectric layer 120 of part, the contact hole etching stopping layer 110 of part, the clearance wall of part 107, and remove cap rock 106 completely, tie until exposing first crystal tubular construction 201 with transistor seconds The end face sacrificing grid 105 of structure 301.
As it is shown on figure 3, carry out wet etching processing technology and/or dry ecthing processing technology to remove first crystal Tubular construction 201 and the sacrifice grid 105 of transistor seconds structure 301, wherein this etching step can stop At etching stopping layer 104, and in first crystal tubular construction 201, form first grid groove respectively (trench) 202, and in transistor seconds structure 301, form second grid groove 302.In the present invention An embodiment in, after defining first grid groove 202 and second grid groove 302, optional Remove to selecting property etching stopping layer 104.
As shown in Figure 4, form the first workfunction layers 410, accordingly the first merit the most comprehensively Function metal 410 conformally covers first grid groove 202, second grid groove 302 is situated between with internal layer The surface of electric layer 120, but it is not fully filled with first grid groove 202 and second grid groove 302. First workfunction layers 410 is for meeting first crystal tubular construction 201, such as P-type transistor, required merit The metal of function requirements, e.g. nickel (Ni), palladium (Pd), platinum (Pt), beryllium (Be), iridium (Ir), tellurium (Te), Rhenium (Re), ruthenium (Ru), rhodium (Rh), tungsten (W), molybdenum (Mo)；Tungsten, ruthenium, molybdenum, tantalum (Ta), titanium (Ti) Nitride；Tungsten, tantalum, the carbide of titanium；Or nitrogen titanium aluminide (TiAlN), nitrogen calorize tantalum (TaAlN) etc.. And in other embodiments of the invention, before forming the first workfunction layers 410, it is possible to selectivity Form barrier layer 405, e.g. tantalum nitride (TaN) layer on DIYU substrate 10 comprehensively.
As it is shown in figure 5, form flatness layer 420 the most comprehensively, its thickness d 1 is about 1500 Angstrom, flatness layer 420 covers in the first workfunction layers 410, and fills up first grid groove 202 With this second grid groove 302.Wherein, the material of flatness layer 420 can include absorbing oxide containing light (DUO), spin-on glasses (SOG), bottom anti-reflective material (BARC) or sacrifice light absorbing material (SLAM), but be not limited to this.Then, carry out flatness layer 420 being etched back processing technology (not shown), make The thickness of flatness layer 420 reduces, and flatness layer 420 is being carried out step, in order to remove flatness layer 420 The residue on surface.It follows that on flatness layer 420 painting photoresist layer, utilize Lithography Etching Processing technology forms patterning photoresist oxidant layer 430, and patterning photoresist oxidant layer 430 is at least covered Cover first crystal tubular construction 201.
As shown in Figure 6, to pattern photoresist oxidant layer 430 as mask layer, dry ecthing making is carried out Technique removes the flatness layer 420 being positioned in transistor seconds structure 301, is positioned at second until exposing The first workfunction layers 410 on transistor arrangement 301, and stay patterning flatness layer 421 to cover On first crystal tubular construction 201.
As it is shown in fig. 7, carry out being etched back processing technology, the first workfunction layers 410 that will come out Removing completely, this eat-back processing technology stops at barrier layer 405, accordingly, is positioned at second grid groove 302 The first workfunction layers 410 can be completely removed, and the first workfunction layers 410 retained to I haven't seen you for ages covers in first grid groove 202.
As shown in Figure 8, it is etched processing technology and sequentially removes patterning photoresist oxidant layer 430 and figure Case flatness layer 421, to expose the first workfunction layers 410 being positioned at the first district 20.Then, The second workfunction layers and low resistance metal layer can be sequentially formed, may be used to that there is double work function gold Belong to the semiconductor element of grid.
But, repeatedly find through inventor's experiment, the space that first embodiment still haves much room for improvement.Such as, When carrying out being etched back processing technology after forming flatness layer 420, it is possible to cause smooth the most comprehensively Layer 420 produces some holes, and then damages the first workfunction metal in first crystal tubular construction 201 Layer 410, and, the cleaning step carried out after eat-back, also cannot completely residue be removed clean, The surface making flatness layer 420 is the most smooth, and follow-up on flatness layer 420 during painting photoresist layer Easily produce bubble, cause the error of lithographic fabrication process.It addition, as illustrated in figs. 7 and 8, beating Just remove patterning photoresist oxidant layer 430 after opening second grid groove 302, there may be some light Cause anticorrosive additive material to remain in second grid groove 302, and follow-up removing patterns flatness layer 421 institute The etchant that uses also cannot etch photo anti-corrosion agent material, therefore still has light in second grid groove 302 Cause anticorrosive additive material residue, and affect the usefulness of transistor seconds structure.
Refer to Fig. 9 to Figure 13, be semiconductor element depicted according to the second embodiment of the present invention The generalized section of manufacture method.The part steps phase of the part steps of the present embodiment and first embodiment With, such as Fig. 1 to Fig. 5, and the Fig. 9 depicted in the present embodiment can be connected at depicted in first embodiment After Fig. 4, as it is shown in figure 9, the present embodiment forms flatness layer 420 on substrate 10 comprehensively, have one thick Degree d2, can be thicker than the flatness layer of first embodiment (shown in Fig. 5), and thickness d 2 is about 1900 angstroms.Then, Flatness layer 420 is formed patterning photoresist oxidant layer 430, at least covers first crystal tubular construction 201。
As shown in Figure 10, to pattern photoresist oxidant layer 430 as mask layer, it is etched making Technique, such as dry-etching processing technology, patterns flatness layer 422 to be formed.But, noticeable It is, in the present embodiment, only to remove the flatness layer 420 that part is positioned in transistor seconds structure 301, position In transistor seconds structure 301, remaining flatness layer 420R the most still covers second grid groove 302, Remaining flatness layer 420R thickness d 3 is about 150 angstroms, in other words, in second grid groove 302 First workfunction layers 410 the most therefore etching step and come out.And pattern flatness layer 422 By the protection of patterning photoresist oxidant layer 430, thickness is the most thinning, and covers at the first transistor knot On structure 201.
As shown in figure 11, it is etched processing technology and removes patterning photoresist oxidant layer 430 completely, and Expose patterning flatness layer 422, and pattern the thickness of flatness layer 422 much larger than remaining flatness layer 420R.Then, as shown in figure 12, carrying out being etched back processing technology, overall etch flatness layer is until completely Remove the residue flatness layer 420R being positioned in transistor seconds structure, and expose and be positioned at the second district 30 First workfunction layers 410, and on first crystal tubular construction 201, retain patterning flatness layer 422, But, thick through this eat-back processing technology, the thickness of patterning flatness layer 422 also can be thinning, its thickness D4 for example, 500 angstroms.
It follows that with patterning flatness layer 422 as hard mask layer, protect first grid structure 202 In the first workfunction layers 410, and remove the first workfunction layers 410 being positioned at the second district 30, And expose such as barrier layer 405 in second grid structure 302, form structure as shown in Figure 8.
Then, as shown in figure 13, first embodiment and the second embodiment all can on substrate 10 holomorphism Becoming the second workfunction layers 440, the second workfunction layers 440 is along first work content in the first district 20 The inner layer dielectric layer 120 in number metal level the 410, second district 30 and the barrier layer 405 of second grid groove Surface formed, but be not fully filled with first grid groove 202 and second grid groove 302.Second Workfunction layers 440 is for meeting transistor seconds structure 301, such as N-type transistor, required work function The metal required, e.g. titanium aluminide (titanium aluminides, TiAl), calorize zirconium (aluminum Zirconium, ZrAl), calorize tungsten (aluminum tungsten, WAl), calorize tantalum (aluminum tantalum, TaAl) or calorize hafnium (aluminum hafnium, HfAl), but it is not limited with above-mentioned.
Then, follow-up processing technology can be carried out, such as, formed low-resistance on the substrate 10 comprehensively Metal level, and fill up first grid groove and second grid groove (not shown).The most real in the present invention Execute in example, metal level can comprise aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), Copper (Cu), titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), titanium tungsten (Ti/W) or titanium and nitridation The composition metal layered materials such as titanium (Ti/TiN), but be not limited.Follow-up also can carry out contact insert fasten (contact Plug) making and other desired processing technology.
It should be noted that in the second embodiment of the present invention, at painting photoresist layer in smooth Before layer 420, eliminate eat-back processing technology and the cleaning step of flatness layer, therefore, infringement can be avoided The first workfunction layers 410 in first crystal tubular construction 201, also will not produce residue and be detained On flatness layer 420 surface, photoresist oxidant layer coated articles matter therefore can be avoided the best.Additionally, such as Figure 10 To Figure 12, before opening second grid groove 302, first remove patterning photoresist oxidant layer 430, And photo anti-corrosion agent material can be removed clean again by follow-up several roads processing technology, therefore, can avoid photic Anticorrosive additive material remains in second grid groove 302, affects the electrical of metal gates.
Previous embodiment is as a example by the manufacture method of planar transistor (planar transistor), but the present invention Also apply be applicable to other non-planar transistors (non-planar transistor), such as fin-shaped field-effect transistor (Fin FET) etc., these embodiments all should belong to the scope that the present invention is contained.
Although disclosing the present invention in conjunction with preferred embodiment above, but it being not limited to the present invention, Any skilled person, without departing from the spirit and scope of the present invention, can make a little change and profit Decorations, therefore protection scope of the present invention should be with being as the criterion that the claim enclosed is defined.

Claims (9)

1. a semiconductor device manufacturing method, its step includes:
The substrate having first crystal tubular construction with transistor seconds structure, wherein, this first crystal are provided Tubular construction has first grid groove, and this transistor seconds structure has second grid groove；
One first workfunction layers is formed in this first grid groove with this second grid groove；
Forming a flatness layer in this first workfunction layers, this flatness layer fills up this first grid groove With this second grid groove；
This flatness layer is formed a patterning photoresist oxidant layer；
Using this patterning photoresist oxidant layer as mask layer, etching part is positioned at this transistor seconds structure On this flatness layer；
Remove this patterning photoresist oxidant layer；
After removing this patterning photoresist oxidant layer, this flatness layer of overall etch is until removing be positioned at completely This flatness layer in this transistor seconds structure, and retain a patterning flatness layer and cover this first crystal Tubular construction；And
Using this patterning flatness layer as hard mask layer, remove be positioned in this second grid groove this first Workfunction layers.
2. semiconductor device manufacturing method as claimed in claim 1, its step also includes:
Before forming this first workfunction layers in this first grid groove with this second grid groove, A barrier layer is formed in this first grid groove with this second grid groove.
3. semiconductor device manufacturing method as claimed in claim 2, wherein, at overall etch, this is smooth Layer step time, expose this barrier layer being positioned in this first grid groove.
4. semiconductor device manufacturing method as claimed in claim 1, wherein, at this first work function gold When belonging to the step forming this flatness layer on layer, a thickness of this flatness layer is 1900 angstroms.
5. semiconductor device manufacturing method as claimed in claim 1, wherein, photic anti-with this patterning Erosion oxidant layer is as mask layer, and etching part is positioned at this flatness layer in this transistor seconds structure until one Thickness is less than 150 angstroms, and still covers this first workfunction layers.
6. semiconductor device manufacturing method as claimed in claim 1, its step also includes:
Remove this patterning flatness layer, in order to expose this first work content being positioned in this first grid groove Number metal level.
7. semiconductor device manufacturing method as claimed in claim 6, its step also includes:
After the step removing this patterning flatness layer, at this first grid groove and this second grid groove Middle formation one second workfunction layers.
8. semiconductor device manufacturing method as claimed in claim 1, wherein, this first crystal tubular construction It is fin-shaped field-effect transistor structure with this transistor seconds structure.
9. semiconductor device manufacturing method as claimed in claim 1, wherein, the material bag of this flatness layer Containing light absorb oxide (DUO), spin-on glasses (SOG), bottom anti-reflective material (BARC) or Sacrifice light absorbing material (SLAM).
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