CN106297634B - A kind of shift register, gate driving circuit and driving method - Google Patents
A kind of shift register, gate driving circuit and driving method Download PDFInfo
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- CN106297634B CN106297634B CN201610794582.4A CN201610794582A CN106297634B CN 106297634 B CN106297634 B CN 106297634B CN 201610794582 A CN201610794582 A CN 201610794582A CN 106297634 B CN106297634 B CN 106297634B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Shift Register Type Memory (AREA)
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The present invention provides a kind of shift register, in which: pull-up module is electrically connected first input end, the second input terminal and low level signal input terminal, including first film transistor, the second thin film transistor (TFT) and third thin film transistor (TFT)；Pull-down module is electrically connected second clock signal input part and low level signal input terminal, including the 4th thin film transistor (TFT) and the second capacitor；Output module is electrically connected the first clock signal input terminal, second clock signal input part, the first output end and low level signal input terminal, including first capacitor, the 5th thin film transistor (TFT), the 6th thin film transistor (TFT) and the 7th thin film transistor (TFT)；Reseting module is electrically connected reset signal input terminal and low level signal input terminal, including the 8th thin film transistor (TFT) and the 9th thin film transistor (TFT)；Current potential keeps module electrical connection first input end, low level signal input terminal and high level signal input terminal, including third capacitor, the tenth thin film transistor (TFT) and the 11st thin film transistor (TFT).
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of shift registers, gate driving circuit and driving method.
Background technique
Currently, each field is to display, the requirement of the including but not limited to mobile terminals such as mobile phone, plate is higher and higher, together
When also improve requirement to display panel.Display panel frivolous should resist again various harsh environments.
In technical field of display panel, display panel needs that long term high temperature is undergone to work, but under long term high temperature work at present,
Technical staff has found that the part of devices characteristic in the gate driving circuit of display panel is easy to happen offset, causes to leak electricity in circuit
It flows through big.Gate driving circuit includes that the shift register of composition is often more sensitive, since the problem of leakage current is easy to cause
Interdependent node potential shift is so as to cause grid output abnormality.
Summary of the invention
To solve the above problems, the present invention provides a kind of shift register, including pull-up module, pull-down module, output mould
Block, reseting module, current potential keep module, first node, second node and third node, in which:
Pull-up module electrical connection first input end, the second input terminal and low level signal input terminal, including first is thin
Film transistor, the second thin film transistor (TFT) and third thin film transistor (TFT)；
The pull-down module electrical connection second clock signal input part and low level signal input terminal, including the 4th film are brilliant
Body pipe and the second capacitor；
The output module is electrically connected the first clock signal input terminal, second clock signal input terminal, the first output
End and low level signal input terminal, including first capacitor, the 5th thin film transistor (TFT), the 6th thin film transistor (TFT) and the 7th film
Transistor；
The reseting module electrical connection reset signal input terminal and low level signal input terminal, including the 8th film crystal
Pipe and the 9th thin film transistor (TFT)；
The current potential keeps module electrical connection first input end, low level signal input terminal and high level signal input
End, including third capacitor, the tenth thin film transistor (TFT) and the 11st thin film transistor (TFT).
A kind of gate driving circuit, including a kind of at least one level shift register described above, wherein described first is defeated
Enter first output end that end is upper level, second input terminal is first output end of next stage.
A kind of driving method drives a kind of gate driving circuit described above, including first stage, second stage,
Three stages and fourth stage, wherein
In the first stage, the reset signal input terminal output reset signal, first clock signal is defeated at this time
Enter end output low level signal, the second clock signal input part exports high level；
In the second stage, the first input end input high level signal, first clock signal input at this time
Hold input high level signal, the second clock signal input part input low level signal；
In the phase III, the first input end stops input signal, the first clock signal input terminal output
Low level signal, the second clock signal input part export high level signal, and first output signal exports grid at this time
Signal；
In the fourth stage, first clock signal input terminal exports high level signal, the second clock signal
Input terminal exports low level signal；At this point, the high level signal of output signal described in the second input terminal output next stage.
Compared with prior art, technical solution of the present invention has one of the following advantages: in 9T2C, i.e. nine film crystals
Increase current potential on the basis of pipe and two capacitors and keeps module.Wherein, current potential keep module include two thin film transistor (TFT)s with
And a capacitor, and it is electrically connected first input end, low level signal input terminal and high level signal input terminal.By increasing electricity
Position keeps module, it is ensured that and the shift register in gate driving circuit keeps working normally under the long-time condition of high temperature,
Wherein the film transistor device in shift register will not cause performance that drift occurs because of high temperature leads to leakage current.Have
Current potential keeps the shift register of module that can guarantee that associated film transistor at or close to low level current potential, guarantees output
The normal output of signal.
Gate driving circuit is made of above-mentioned shift register, ensure that the normal output of grid signal；In addition, also providing
A kind of driving method driving above-mentioned gate driving circuit keeps the cooperation of module and other modules by current potential, realizes high temperature
Under working condition, the normal output of signal.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is a kind of module diagram of shift register provided by the invention；
Fig. 2 is a kind of schematic diagram of the pull-up module of shift register provided by the invention；
Fig. 3 is a kind of schematic diagram of the pull-down module of shift register provided by the invention；
Fig. 4 is a kind of schematic diagram of the output module of shift register provided by the invention；
Fig. 5 is a kind of schematic diagram of the reseting module of shift register provided by the invention；
Fig. 6 is that a kind of current potential of shift register provided by the invention keeps the schematic diagram of module；
Fig. 7 is a kind of connection schematic diagram of shift register provided by the invention；
Fig. 8 is a kind of driving method provided by the invention.
Specific embodiment
A kind of shift register of the invention, gate driving circuit and driving method are carried out below with reference to schematic diagram more detailed
Thin description, which show the preferred embodiment of the present invention, it should be appreciated that those skilled in the art can modify and be described herein
The present invention, and still realize advantageous effects of the invention.Therefore, following description should be understood as those skilled in the art
Member's is widely known, and is not intended as limitation of the present invention.
In the prior art, technical staff simulates the characteristic of the thin film transistor (TFT) of connection trigger signal, it has been investigated that, this is thin
Film transistor is under hot operation, and threshold voltage can be there is a situation where deviating to the left, and leakage current dramatically increases at this time.In order to solve
The problem, the present invention provide a kind of shift register that module is kept with current potential, which can guarantee above-mentioned thin
The current potential that film transistor is kept fixed in specific time.
As shown in FIG. 1, FIG. 1 is a kind of module diagrams of shift register provided by the invention.Wherein, the present invention shifts
Register includes pull-up module 1, pull-down module 2, output module 3, reseting module 4, current potential holding module 5, first node (in figure
Be not shown), second node (not shown) and third node (not shown).Wherein, first node, second node with
And third node is the definition carried out in order to illustrate connection type of the invention.
Pull-up module 1 is electrically connected first input end IN, the second input terminal Gn+1 and low level signal input terminal L.Lower drawing-die
Block 2 is electrically connected second clock signal input part CKV2 and low level signal input terminal L.Output module 3 is electrically connected the first clock letter
Number input terminal CKV1, second clock signal input part CKV2, the first output end Gn and low level signal input terminal L.Reset mould
Block 4 is electrically connected reset signal input terminal RESET and low level signal input terminal L.Current potential keeps first input of the electrical connection of module 5
Hold IN, low level signal input terminal L and high level signal input terminal H.
The connection type and effect of modules are illustrated now in conjunction with shift register correlation function.As shown in Fig. 2, figure
2 be a kind of schematic diagram of the pull-up module of shift register provided by the invention.Pull-up module 1 includes first film transistor
M1, the second thin film transistor (TFT) M2 and third thin film transistor (TFT) M3.The first input of grid electrical connection of first film transistor M1
Hold IN, the first pole of first film transistor M1 is electrically connected third node K, the second pole electrical connection of first film transistor M1 the
One node PU.The grid of second thin film transistor (TFT) M2 is electrically connected the second input terminal Gn+1, the first pole of the second thin film transistor (TFT) M2
It is electrically connected first node PU, the second pole of the second thin film transistor (TFT) M2 is electrically connected low level signal input terminal L, receives low level letter
Number.The grid of third thin film transistor (TFT) M3 is electrically connected second node PD, the first pole electrical connection first of third thin film transistor (TFT) M3
The second pole of node PU, third thin film transistor (TFT) M3 are electrically connected low level signal input terminal L.
Fig. 3 is a kind of schematic diagram of the pull-down module of shift register provided by the invention.Pull-down module 2 includes the 4th thin
Film transistor M4 and the second capacitor C2.Wherein, the grid of the 4th thin film transistor (TFT) M4 is electrically connected first node PU, the 4th film
First pole of transistor is electrically connected second node PD, and the second pole of the 4th thin film transistor (TFT) M4 is electrically connected low level signal input terminal
L.The first pole of second capacitor C2 is electrically connected second clock signal input part CKV2, the second pole electrical connection second of the second capacitor C2
Node PD.
Fig. 4 is a kind of schematic diagram of the output module of shift register provided by the invention.Output module 3 includes the 5th thin
Film transistor M5, the 6th thin film transistor (TFT) M6, the 7th thin film transistor (TFT) M7 and first capacitor C1.Wherein, first capacitor C1
First pole is electrically connected first node PU, and the second pole of first capacitor C1 is electrically connected the second pole of the 5th thin film transistor (TFT) M5.5th
The grid of thin film transistor (TFT) M5 is electrically connected first node PU, and the first pole of the 5th thin film transistor (TFT) M5 is electrically connected second clock signal
The second pole of input terminal CKV2, the 5th thin film transistor (TFT) M5 are electrically connected the first output end Gn.The grid of 6th thin film transistor (TFT) M6
It is electrically connected second node PD, the second pole of the first pole electrical connection first capacitor C1 of the 6th thin film transistor (TFT) M6, the 6th film crystalline substance
The second pole of body pipe M6 is electrically connected low level signal input terminal L.7th thin film transistor (TFT) M7 grid is electrically connected the first clock signal
The second pole of the first pole electrical connection first capacitor C1 of input terminal CKV1, the 7th thin film transistor (TFT) M7, the 7th thin film transistor (TFT) M7
The second pole be electrically connected low level signal input terminal L.
Fig. 5 is a kind of schematic diagram of the reseting module of shift register provided by the invention.Reseting module 4 includes the 8th thin
Film transistor M8 and the 9th thin film transistor (TFT) M9.Wherein, the grid electrical connection reset signal input of the 8th thin film transistor (TFT) M8
RESET is held, the first pole of the 8th thin film transistor (TFT) M8 is electrically connected the first output end Gn, and the second of the 8th thin film transistor (TFT) M8 is extremely electric
Connect low level signal input terminal L.The grid of 9th thin film transistor (TFT) M9 is electrically connected reset signal input terminal RESET, and the 9th is thin
The first pole of film transistor M9 is electrically connected first node PU, and the second pole electrical connection low level signal of the 9th thin film transistor (TFT) M9 is defeated
Enter to hold L.
Fig. 6 is that a kind of current potential of shift register provided by the invention keeps the schematic diagram of module.Current potential keeps module 5 to wrap
Include the tenth thin film transistor (TFT) M10, the 11st thin film transistor (TFT) M11 and third capacitor C3.Wherein, the first pole of third capacitor C3
It is electrically connected first input end IN, the second pole of third capacitor C3 is electrically connected third node K.The grid of tenth thin film transistor (TFT) M10
It is electrically connected first input end IN, the first pole of the tenth thin film transistor (TFT) M10 is electrically connected high level signal input terminal H, the tenth film
The second pole of transistor M10 is electrically connected third node K.The grid of 11st thin film transistor (TFT) M11 is electrically connected second node PD, the
The first pole of 11 thin film transistor (TFT) M11 is electrically connected third node K, and the second pole electrical connection of the 11st thin film transistor (TFT) M11 is low
Level signal input terminal L.
Above-mentioned Fig. 2 to Fig. 6 respectively describes pull-up module, pull-down module, output module, reseting module and current potential and keeps
The specific connection structure of module.Wherein, above-mentioned to have elaborated first node PU, second node PD and third node K, specifically
, first node PU is the second pole of the first film crystal M1, the first pole of the second thin film transistor (TFT) M2, third thin film transistor (TFT)
The first pole of M3, the first pole of the 9th thin film transistor (TFT) M9, the grid of the 4th thin film transistor (TFT) M4, first capacitor C1 the first pole
And the 5th thin film transistor (TFT) M5 grid tie point；It is grid that second node PD is third thin film transistor (TFT) M3, the 6th thin
The tie point of second pole of the grid of film transistor M6, the first pole of the 4th thin film transistor (TFT) M4 and the second capacitor C2；Third
Node K is the first pole of first film transistor M1, the first pole of the 11st thin film transistor (TFT) M11 and the tenth thin film transistor (TFT)
The tie point of the second pole of M10.
Fig. 7 is a kind of connection schematic diagram of shift register provided by the invention, specifically, first film transistor M1 is extremely
11st thin film transistor (TFT) M11 can be P-type TFT, i.e., when the grid of thin film transistor (TFT) receives low level signal,
Thin film transistor (TFT) conducting, first extremely on signal can be conducted to the second pole；First film transistor M1 is brilliant to the 11st film
Body pipe M11 can also be N-type TFT, i.e., when the grid of thin film transistor (TFT) receives high level signal, thin film transistor (TFT)
Conducting, first extremely on signal can be conducted to the second pole.
Specifically, above-mentioned shift register concatenation connects into gate driving circuit, gate driving circuit is normally at display
The non-display area of panel.Wherein, other than first order shift register, the first input end IN of other all shift registers is
The first input end of first output end Gn of upper level shift register, the shift register of the first order access trigger signal, should
Signal is provided by the integrated drive chips on panel；Other than the shift register of afterbody, other all shift registers
The second input terminal Gn+1 be next stage shift register the first output end Gn.
In above-described embodiment, the low level signal input terminal of all thin film transistor (TFT) electrical connections can be same input terminal,
It is also possible to different input terminals, is provided which low level signal.In addition, above-mentioned first input end, low level signal input terminal, first
Clock signal input terminal, second clock signal input part, high level signal input terminal etc. can integrate in integrated drive chips
Inside is not described in detail herein, and integrated or external form is included within the scope of the present invention, and the present invention does not do specific limit
System.
The working principle of shift register and gate driving circuit in order to better illustrate the present invention, now in conjunction with Fig. 7 with
And Fig. 8 is described in detail.Wherein, Fig. 8 is a kind of driving method provided by the invention.Driving method of the present invention is above-mentioned for driving
Gate driving circuit, above-mentioned gate driving circuit are made of previously described shift register concatenation, and all thin film transistor (TFT)s are equal
For N-type TFT, specific connection structure is repeated no more.The driving method mainly includes four-stage, specially the first rank
Section T1, second stage T2, phase III T3 and fourth stage T4.
In the first stage during T1, first input end IN not yet output signal, the first clock signal input terminal CKV1 is defeated
Low level signal out, second clock signal input part CKV2 export high level signal, and reset signal input terminal RESET output resets
Signal.Second transistor M2 grid no signal inputs at this time, is in an off state；First film transistor M1 and the tenth film
The grid of transistor M10 receives the low level signal of first input end IN and is in an off state；Because second clock signal inputs
CKV2 input high level signal is held, the second capacitor C2 charges at this time, and second node PD keeps high level signal thus the tenth
One thin film transistor (TFT) M11, third thin film transistor (TFT) M3 and the 6th thin film transistor (TFT) M6 conducting, the 11st thin film transistor (TFT) M11
The second pole, third thin film transistor (TFT) M3 the second pole and the 6th thin film transistor (TFT) M6 the second pole receive low level signal input
Hold the low level signal of L output；Because third thin film transistor (TFT) M3 is connected, low level signal is caused to be transmitted to first node PU, this
When the 4th thin film transistor (TFT) M4 disconnect；During first stage T1, reset signal input terminal RESET output reset signal, this
When the 8th thin film transistor (TFT) M8 and the 9th thin film transistor (TFT) M9 conducting, low level signal input terminal L output low level signal
Into shift register, reset initialization is carried out, therefore the first output end Gn exports low level signal at this time.
During second stage T2, first input end IN output pulse signal, i.e. high level signal, the first clock signal is defeated
Enter to hold CKV1 to export high level signal, second clock signal input part CKV2 becomes low level signal.At this point, because of first input end
IN exports high level signal, and first film transistor M1 and the tenth thin film transistor (TFT) M10 conducting, third capacitor C3 are filled
Electricity, third node K are high level, and first node PU becomes high level；Because the first clock signal input terminal CKV1 exports high level
Signal, the 7th thin film transistor (TFT) M7 is connected at this time, and the second pole of the 7th thin film transistor (TFT) M7 receives low level signal input terminal L's
Low level signal, and it is transmitted to the second pole of first capacitor C1；Because second clock signal input part CKV2 exports low level signal,
Low level signal is transmitted to the second pole of the 5th thin film transistor (TFT) M5 by the 5th thin film transistor (TFT) in the on-state at this time, at this time
First output end Gn still exports low level signal；Second node PD becomes low level under the action of the second capacitor C2.
During phase III, first input end IN maintains low level signal, the first clock signal input terminal CKV1 at this time
Low level signal is exported, second clock signal input part CKV2 exports high level signal.Because first input end IN maintains low level
Signal, first film transistor M1 and the tenth thin film transistor (TFT) M10 are in an off state at this time, and third node K is at this time
Low level state is maintained under the action of three capacitor C3；And first node PU is being in high level state, therefore the 5th on last stage
The high level signal of thin film transistor (TFT) M5 conducting, second clock signal input part CKV2 output is transmitted to the 5th thin film transistor (TFT) M5
The second pole, at this time because the coupling of first capacitor C1 causes first node PU to be elevated；4th thin film transistor (TFT) M4 because
The high level state of first node PU and be connected, the second pole receive low level signal simultaneously be transmitted to second node PD, therefore second
Node PD maintains low level；First output end Gn output pulse signal at this time, the signal are transmitted to grid line and are used to open and picture
The thin film transistor (TFT) of plain electrode connection.
During fourth stage, first input end IN maintains low level signal, the first clock signal input terminal CKV1 output
High level signal, second clock signal input part CKV2 export low level signal.At this point, because of the effect of the second capacitor C2, second
Node PD becomes low level；The grid of 7th thin film transistor (TFT) M7 leads the 7th thin film transistor (TFT) M7 because receiving high level signal
Logical, low level signal is transmitted to the second pole of first capacitor C1 from the second pole of the 7th thin film transistor (TFT) M7 at this time；First node
PU becomes low level because of the continuous discharge of first capacitor C1 and third thin film transistor (TFT) M3 conducting input low level signal；This
When, the tenth thin film transistor (TFT) M10 and first film transistor M1 are still in an off state, and third node K becomes because of no signal
Change and maintains low level.
In above process, when first node PU is in low level state, third node K can maintain low level constantly
State, therefore the difference between the first pole and the second pole of the first transistor M1 is able to maintain that in lower range.That is,
Third node K becomes high level in first input end IN output pulse signal phase process, other stages third node K is always
Low level state is maintained, especially when the first output end Gn exports low level signal, because of the of first film transistor M1
One pole is electrically connected third node K, can maintain low level state always, reduce the risk of leakage current, prevent the first film
Transistor M1 generating device characteristic deviation and influence the first signal output end Gn signal output.
Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that
The invention is not limited to the specific embodiments described herein, be able to carry out for a person skilled in the art it is various it is apparent variation,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out by above embodiments to the present invention
It is described in further detail, but the present invention is not limited to the above embodiments only, without departing from the inventive concept, also
It may include more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.
Claims (10)
1. a kind of shift register, including pull-up module, pull-down module, output module, reseting module, current potential keep module, the
One node, second node and third node, in which:
The pull-up module electrical connection first input end, the second input terminal and low level signal input terminal, including the first film are brilliant
Body pipe, the second thin film transistor (TFT) and third thin film transistor (TFT)；
The pull-down module electrical connection second clock signal input part and low level signal input terminal, including the 4th thin film transistor (TFT)
And second capacitor；
The output module is electrically connected the first clock signal input terminal, second clock signal input part, the first output end and low
Level signal input terminal, including first capacitor, the 5th thin film transistor (TFT), the 6th thin film transistor (TFT) and the 7th thin film transistor (TFT)；
Reseting module electrical connection reset signal input terminal and low level signal input terminal, including the 8th thin film transistor (TFT) with
And the 9th thin film transistor (TFT)；
The current potential keeps module electrical connection first input end, low level signal input terminal and high level signal input terminal, packet
Include third capacitor, the tenth thin film transistor (TFT) and the 11st thin film transistor (TFT)；
The current potential is kept in module, and the first pole of the third capacitor is electrically connected the first input end, the electrical connection of the second pole
The third node；
The grid of tenth thin film transistor (TFT) is electrically connected the first input end, and the first of the tenth thin film transistor (TFT) is extremely electric
The high level signal input terminal is connected, the second pole of the tenth thin film transistor (TFT) is electrically connected the third node；
The grid of 11st thin film transistor (TFT) is electrically connected the second node, the first pole of the 11st thin film transistor (TFT)
It is electrically connected the third node, the second pole of the 11st thin film transistor (TFT) is electrically connected the low level signal input terminal.
2. a kind of shift register according to claim 1, in the pull-up module,
The grid of the first film transistor is electrically connected the first input end, and the first of the first film transistor is extremely electric
The third node is connected, the second pole of the first film transistor is electrically connected the first node；
The grid of second thin film transistor (TFT) is electrically connected second input terminal, and the first of second thin film transistor (TFT) is extremely electric
The first node is connected, the second pole of second thin film transistor (TFT) is electrically connected the low level signal input terminal；
The grid of the third thin film transistor (TFT) is electrically connected the second node, and the first pole of the third thin film transistor (TFT) is electrically connected
The first node is connect, the second pole of the third thin film transistor (TFT) is electrically connected low level signal input terminal.
3. a kind of shift register as described in claim 1, in the pull-down module,
The grid of 4th thin film transistor (TFT) is electrically connected the first node, and the first pole of the 4th thin film transistor (TFT) is electrically connected
The second node is connect, the second pole of the 4th thin film transistor (TFT) is electrically connected the low level signal input terminal；
First pole of second capacitor is electrically connected the second clock signal input part, and the second pole of second capacitor is electrically connected
Connect the second node.
4. a kind of shift register as described in claim 1, in the output module,
First pole of the first capacitor is electrically connected the first node, the second pole electrical connection the described 5th of the first capacitor
Second pole of thin film transistor (TFT)；
The grid of 5th thin film transistor (TFT) is electrically connected the first node, and the first pole of the 5th thin film transistor (TFT) is electrically connected
The second clock signal input part is connect, the second pole of the 5th thin film transistor (TFT) is electrically connected first output end；
The grid of 6th thin film transistor (TFT) is electrically connected the second node, and the first pole of the 6th thin film transistor (TFT) is electrically connected
The second pole of the first capacitor is connect, the second pole of the 6th thin film transistor (TFT) is electrically connected the low level signal input terminal；
The grid of 7th thin film transistor (TFT) is electrically connected first clock signal input terminal, the 7th thin film transistor (TFT)
First pole is electrically connected the second pole of the first capacitor, and the second pole of the 7th thin film transistor (TFT) is electrically connected the low level letter
Number input terminal.
5. a kind of shift register as described in claim 1, in the reseting module,
The grid electrical connection reset signal input terminal of 8th thin film transistor (TFT), the first of the 8th thin film transistor (TFT)
Pole is electrically connected first output end, and the second pole of the 8th thin film transistor (TFT) is electrically connected the low level signal input terminal；
The grid electrical connection reset signal input terminal of 9th thin film transistor (TFT), the first of the 9th thin film transistor (TFT)
Pole is electrically connected the first node, and the second pole of the 9th thin film transistor (TFT) is electrically connected the low level signal input terminal.
6. a kind of shift register as described in claim 1, wherein the first film transistor to the 11st film
Transistor can be prepared by any one of amorphous silicon, low temperature polycrystalline silicon or oxide semiconductor.
7. a kind of shift register as described in claim 1, wherein the first film transistor to the 11st film
Transistor is P-type TFT or N-type TFT.
8. a kind of gate driving circuit, including a kind of at least one level shift register described in claim 1, wherein described
One input terminal is first output end of upper level, and second input terminal is first output end of next stage.
9. a kind of driving method, drive a kind of gate driving circuit according to any one of claims 8, including the first stage, second stage,
Phase III and fourth stage, wherein
In the first stage, the reset signal input terminal output reset signal, first clock signal input terminal at this time
Low level signal is exported, the second clock signal input part exports high level；
In the second stage, the first input end input high level signal, first clock signal input terminal is defeated at this time
Enter high level signal, the second clock signal input part input low level signal；
In the phase III, the first input end stops input signal, and first clock signal input terminal exports low electricity
Ordinary mail number, the second clock signal input part export high level signal, and first output signal exports grid signal at this time；
In the fourth stage, first clock signal input terminal exports high level signal, the second clock signal input
End output low level signal；At this point, the high level signal of output signal described in the second input terminal output next stage.
10. a kind of driving method as claimed in claim 9, wherein
In the first stage, the first node and the third node keep low potential, and the second node keeps high electricity
Position；
In the second stage, the first node and the third node become high potential, and the second node becomes low electricity
Position；
In the phase III, the first node current potential is elevated, and the second node and the third node become low electricity
Position；
In the fourth stage, the first node, the second node and the third node become low potential.
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| CN109377934A (en) * | 2018-12-27 | 2019-02-22 | 厦门天马微电子有限公司 | Shift register cell, its driving method, gate driving circuit and display device |
| CN109935188B (en) | 2019-03-08 | 2020-11-24 | 合肥京东方卓印科技有限公司 | Gate driving unit, gate driving method, gate driving module, circuit and display device |
| CN110010054B (en) * | 2019-05-06 | 2023-07-28 | 京东方科技集团股份有限公司 | Gate drive circuit, display panel and display device |
| CN110060645B (en) * | 2019-05-07 | 2022-08-09 | 京东方科技集团股份有限公司 | Shifting register and driving method thereof, grid driving circuit and display device |
| CN110085159B (en) * | 2019-05-30 | 2022-08-09 | 京东方科技集团股份有限公司 | Shifting register unit, grid driving circuit and display device |
| CN110148383B (en) | 2019-06-19 | 2021-01-26 | 京东方科技集团股份有限公司 | Shift register unit and driving method thereof and grid driving circuit |
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