CN106294260A

CN106294260A - The method that data export synchronous bus from asynchronous bus

Info

Publication number: CN106294260A
Application number: CN201610679509.2A
Authority: CN
Inventors: 冯威; 朱伟; 陈志军; 伍翔; 王晶龙; 吴艳
Original assignee: Changsha Rich Communication Technology Co Ltd
Current assignee: Changsha Rich Communication Technology Co Ltd
Priority date: 2016-08-18
Filing date: 2016-08-18
Publication date: 2017-01-04
Anticipated expiration: 2036-08-18
Also published as: CN106294260B

Abstract

The method that data export synchronous bus from asynchronous bus, comprises the following steps: the chip selection signal CS and write signal WE of main equipment asynchronous bus are connected to the input with gate device by (1)；(2) outfan with gate device is connected to the clock signal clk end from equipment；(3) control signal GPIO of main equipment is connected to the control signal from equipment synchronous bus；(4), when main equipment carries out write operation, chip selection signal CS and write signal WE is given to from the synchronous bus of equipment, as the clock signal clk of synchronous bus by producing a periodic signal with gate device；(5) control signal GPIO of main equipment is set to the signal significant level needed, and main equipment performs the write operation of an invalid data, control signal GPIO puts back into inactive level, produces one and the control signal of clock signal clk synchronization.Peripheral circuit of the present invention is simple, it is not necessary to extra clock signal.

Description

The method that data export synchronous bus from asynchronous bus

Technical field

The present invention relates to a kind of method that data export synchronous bus from asynchronous bus.

Background technology

In electronic product, have and need primary processor the data handled well to be issued peripheral hardware (as display module, outside are deposited in a large number Storage module) operation, the most all use the mode of data/address bus to carry out one to one, or one-to-many data transmission.

Asynchronous bus is again a kind of popular bus mode, with reference to Fig. 1, Fig. 2, the most the most frequently used intel i80 Bus mode, wherein chip selection signal CS is for particular device a certain in bus, only (this case when chip selection signal CS is effective Example is Low level effective), corresponding reception equipment just starts there is write signal WR response, and accepts data corresponding to write signal WR (present case is that write signal WR rising edge gathers data/address bus).If chip selection signal CS is invalid, even if write signal WR has action, Being considered as the equipment for other, accepting device corresponding for this chip selection signal CS will not do to be comprehended.

In addition to asynchronous bus, also having a kind of synchronous bus mode, with reference to Fig. 3, and the main distinction of asynchronous bus is two Clock signal clk to be relied between individual equipment, clock signal clk for control signal (this sentences synchronizing signal SP is example) and The synchronization of data signal obtains.Being by clock signal clk rising edge in lower example, the equipment that receives obtains synchronizing information, then start Rear each clock receives data, completes the accurate reception of whole data with this.

When the system of electronic product designs and be integrated, main equipment can be run into and provide asynchronous bus, and receive data Then can only receive the data synchronous bus from equipment.Now need at main equipment and select to be replaced from equipment, with Keep the consistent of bus, it is common practice to being further added by a processor and carry out the conversion of both sides bus, this will make system more Complicated and cause cost to increase.

The most also have and produce clock signal by main equipment or external clock generator, by clock plus peripheral auxiliary circuits Carrying out the conversion of bus, this mode is harsher to requirement and the control of clock, and design difficulty is bigger.

Summary of the invention

The technical problem to be solved is, overcomes the deficiency of above-mentioned background technology, it is provided that a kind of peripheral circuit letter Single, it is not necessary to the method that the data of extra clock signal export synchronous bus from asynchronous bus.

The present invention solves its technical problem and employed technical scheme comprise that, a kind of data export synchronous bus from asynchronous bus Method, comprise the following steps:

(1) the chip selection signal CS on main equipment asynchronous bus and write signal WE is connected to the input with gate device of outside；

(2) the clock signal clk end that the outfan with gate device is connected to from equipment；

(3) control signal GPIO of main equipment is directly connected to the control signal from equipment synchronous bus；

(4), when main equipment carries out write operation, chip selection signal CS and write signal WE produces a cycle by outside with gate device The signal of property is given to from the synchronous bus of equipment, as the clock signal clk of synchronous bus；

(5) control signal GPIO of main equipment is set to the signal significant level needed, and main equipment performs an invalid data Write operation, then control signal GPIO is put back into inactive level, then produces one and control signal that clock signal clk synchronizes.

Further, in step (3), described control signal selection synchronizing signal SP from equipment synchronous bus.

Compared with prior art, advantages of the present invention is as follows:

(1) utilize and carry out logical process with the chip selection signal CS and write signal WE of goalkeeper's asynchronous bus, produce synchronous bus time Clock, peripheral circuit is simple, it is not necessary to extra clock signal；(2) utilize control signal GPIO of main equipment, then coordinate once without The write operation of effect data, produces the control signal that synchronous bus needs, can produce the control signal of multiple synchronization, meets synchronization total The reception timing requirements of line equipment, directly carries out the coupling of sequential and the transmission of data.

Accompanying drawing explanation

Fig. 1 is the connection block diagram of the bus mode of existing intel i80.

Fig. 2 be existing intel i80 bus mode output write eDRAM.

Fig. 3 be existing synchronous bus mode write eDRAM.

Fig. 4 is that the circuit of the embodiment of the present invention connects schematic block diagram.

Fig. 5 is that the waveform of the embodiment of the present invention generates schematic block diagram.

Detailed description of the invention

Below in conjunction with the accompanying drawings and the present invention is described in further detail by specific embodiment.

In terms of the contrast of synchronous bus and asynchronous bus, receiving this part of data, the write signal WE of asynchronous bus and with The clock signal clk of step bus is substantially compatibility with the sequential of data/address bus, and the main distinction is embodied in control signal and clock In the association of signal CLK, the present invention utilizes chip selection signal CS and write signal WE with goalkeeper's asynchronous bus to carry out logical process, produces The clock signal clk of raw synchronous bus, utilizes control signal GPIO of main equipment, then coordinates the write operation of an invalid data, Produce synchronous bus need control signal, thus realize main equipment from asynchronous bus transmit data to synchronous bus from setting Standby.

With reference to Fig. 4, Fig. 5, the present embodiment comprises the following steps:

(3) control signal GPIO of main equipment being directly connected to the control signal from equipment synchronous bus, the present embodiment is from setting The control signal of standby synchronous bus selects synchronizing signal SP；Main equipment can be attached directly to from equipment by multiple control signals GPIO On, as multiple different synchronous bus control signals；

(5) control signal GPIO of main equipment is set to the signal significant level (such as low level) needed, and main equipment performs one The write operation of individual invalid data, then control signal GPIO is put back into inactive level (such as high level), then produce one and clock is believed The control signal that number CLK synchronizes；Control signal GPIO can stride across the multiple invalid or write operation of valid data, realizes difference The synchronous control signal of clock cycle length.

Although seeing in sequential that write signal WE and clock signal clk are essentially identical, but write signal WE is the upper multiplexing of bus Signal, miscellaneous equipment work time also have output, if be directly connected with the clock signal clk from equipment, can cause grasping by mistake Make, cause Data reception errors.Therefore write signal WE and chip selection signal CS signal are carried out logical AND operation by the present invention, it is ensured that only The write signal WE from equipment having chip selection signal CS corresponding gives clock signal clk.

The control signal (synchronizing signal SP in this example) of synchronised clock, it is also desirable to clock matches.The present embodiment uses main The universal input output signal (control signal GPIO) of equipment is simulated, according to the demand of synchronous bus, and the corresponding height of output Level and change.But there is also the need to the synchronization of clock signal clk, also will be during the effect of control signal GPIO for this In, the change of write signal WE is produced by sending the write operation (can write according to timing requirements) of hash with one or many Change, and be converted into clock signal clk so that control signal and clock signal clk can meet the timing requirements of synchronous bus.

Those skilled in the art can carry out various modifications and variations to the present invention, if these amendments and modification are at this Within the scope of invention claim and equivalent technologies thereof, then these amendments and modification are also within protection scope of the present invention.

The prior art that the content not described in detail in description is known to the skilled person.

Claims

1. the method that data export synchronous bus from asynchronous bus, it is characterised in that comprise the following steps:

2. the method that data as claimed in claim 1 export synchronous bus from asynchronous bus, it is characterised in that: step (3) In, described control signal selection synchronizing signal SP from equipment synchronous bus.