CN106292996A - Voltage based on multi core chip reduces method and system - Google Patents
Voltage based on multi core chip reduces method and system Download PDFInfo
- Publication number
- CN106292996A CN106292996A CN201610600313.XA CN201610600313A CN106292996A CN 106292996 A CN106292996 A CN 106292996A CN 201610600313 A CN201610600313 A CN 201610600313A CN 106292996 A CN106292996 A CN 106292996A
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- China
- Prior art keywords
- kernel
- voltage
- thread
- reduce
- multi core
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/329—Power saving characterised by the action undertaken by task scheduling
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Sources (AREA)
Abstract
The invention provides a kind of voltage based on multi core chip and reduce method and system, described method comprises the steps: the thread of voltage and the operation detecting each kernel;Judge whether the voltage of this kernel exceedes voltage threshold;Voltage such as this kernel exceedes voltage threshold, then reduce the number of threads of this kernel.The technical scheme that the present invention provides has the advantage effectively reducing voltage.
Description
Technical field
The present invention relates to electronic applications, particularly relate to a kind of voltage based on multi core chip and reduce method and system.
Background technology
Chip, English is Chip;Chipset is Chipset.Chip generally refers to the carrier of integrated circuit, is also integrated electricity
Road result after designing, manufacture, encapsulate, testing, it is common that the independent entirety that can use immediately." chip " and
" integrated circuit " the two word often mixes and uses, and such as in everybody usual discussion topic, IC design and chip set
What meter was said is a meaning, and chip industry, integrated circuit industry, IC industry are the most also meanings.It practice, the two word
It is related, also has any different.Integrated circuit entity because the integrated circuit of narrow sense, to be often to emphasize presented in chip
Circuit itself is such as simple to only five phaseshift oscillators that element is joined together to form, when it also presents on drawing
When, we can also be its integrated circuit, and when we to take this little integrated circuit apply when, it must be with
One piece of independent material object, or be embedded in bigger integrated circuit, rely on chip to play his effect;Integrated circuit is more
The weight design of circuit and placement-and-routing, chip more accentuator circuit integrated, produce and encapsulate.And the integrated circuit of broad sense, when relating to
And during to industry (being different from other industry), it is also possible to comprise the various implications that chip is relevant.
Existing electronic chip all has multiple kernel, but the voltage of multiple kernels cannot be carried out by existing electronic chip
Control.
Summary of the invention
Thering is provided a kind of voltage based on multi core chip to reduce method, which solve prior art cannot realize multi core chip
Voltage reduce shortcoming.
On the one hand, it is provided that a kind of voltage based on multi core chip reduces method, and described method comprises the steps:
Detect the voltage of each kernel and the thread of operation;
Judge whether the voltage of this kernel exceedes voltage threshold;
Voltage such as this kernel exceedes voltage threshold, then reduce the number of threads of this kernel.
Optionally, described method also includes:
It is assigned in other kernels run by the thread of this kernel reduced.
Optionally, described method also includes:
The thread of this kernel reduced is evenly distributed in other kernels operation.
Second aspect, it is provided that a kind of voltage based on multi core chip reduces system, and described system includes:
Detector unit, for detecting the voltage of each kernel and the thread of operation;
Judging unit, for judging whether the voltage of this kernel exceedes voltage threshold;
Reduce unit, exceed voltage threshold for the voltage such as this kernel, then reduce the number of threads of this kernel.
Optionally, described system also includes:
Allocation unit, for being assigned in other kernels run by the thread of this kernel reduced.
Optionally, described system also includes:
All subdivisions, for being evenly distributed in other kernels operation by the thread of this kernel reduced.
The technical scheme that the specific embodiment of the invention provides detects voltage and the thread of operation of each kernel, such as this
The voltage of kernel exceedes voltage threshold, then reduce the number of threads of this kernel, so its advantage with the voltage reducing chip.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
In having technology to describe, the required accompanying drawing used is briefly described, it should be apparent that, the accompanying drawing in describing below is only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to
Other accompanying drawing is obtained according to these accompanying drawings.
Fig. 1 reduces the flow chart of method for a kind of based on multi core chip the voltage that the present invention provides;
Fig. 2 reduces the structure chart of system for a kind of based on multi core chip the voltage that the present invention provides.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Describe, it is clear that described embodiment is only a part of embodiment of the present invention rather than whole embodiments wholely.Based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under not making creative work premise
Embodiment, broadly falls into the scope of protection of the invention.
A kind of based on multi core chip the voltage reduction side provided for the present invention the first better embodiment refering to Fig. 1, Fig. 1
The flow chart of method, the method is completed by electronic chip, and the method is as it is shown in figure 1, comprise the steps:
Step S101, detect the voltage of each kernel and the thread of operation;
Step S102, judge whether the voltage of this kernel exceedes voltage threshold;
Step S103, voltage such as this kernel exceed voltage threshold, then reduce the number of threads of this kernel.
The technical scheme that the specific embodiment of the invention provides detects voltage and the thread of operation of each kernel, such as this
The voltage of kernel exceedes voltage threshold, then reduce the number of threads of this kernel, so its advantage with the voltage reducing chip.
Optionally, said method can also include after step s 103:
It is assigned in other kernels run by the thread of this kernel reduced.
Optionally, said method can also include after step s 103:
The thread of this kernel reduced is evenly distributed in other kernels operation.
A kind of based on multi core chip the voltage provided for the present invention the second better embodiment refering to Fig. 2, Fig. 2 reduces system
System, this system includes:
Detector unit 201, for detecting the voltage of each kernel and the thread of operation;
Judging unit 202, for judging whether the voltage of this kernel exceedes voltage threshold;
Reduce unit 203, exceed voltage threshold for the voltage such as this kernel, then reduce the number of threads of this kernel.
The technical scheme that the specific embodiment of the invention provides detects voltage and the thread of operation of each kernel, such as this
The voltage of kernel exceedes voltage threshold, then reduce the number of threads of this kernel, so its advantage with the voltage reducing chip.
Optionally, said system can also include:
Allocation unit 204, for being assigned in other kernels run by the thread of this kernel reduced.
Optionally, said system can also include:
All subdivisions 205, for being evenly distributed in other kernels operation by the thread of this kernel reduced.
It should be noted that for aforesaid each method embodiment or embodiment, in order to be briefly described, therefore by its all table
Stating as a series of combination of actions, but those skilled in the art should know, the present invention is not by described sequence of movement
Restriction, because of according to the present invention, some step can use other orders or carry out simultaneously.Secondly, people in the art
Member also should know, embodiment described in the specification or embodiment belong to preferred embodiment, involved action and list
Necessary to the unit not necessarily present invention.
In the above-described embodiments, the description to each embodiment all emphasizes particularly on different fields, and does not has the portion described in detail in certain embodiment
Point, may refer to the associated description of other embodiments.
Step in embodiment of the present invention method can carry out order according to actual needs and adjust, merges and delete.
Unit in embodiment of the present invention device can merge according to actual needs, divides and delete.This area
The feature of the different embodiments described in this specification and different embodiment can be combined or combine by technical staff.
Through the above description of the embodiments, those skilled in the art it can be understood that to the present invention permissible
Realize with hardware, or firmware realizes, or combinations thereof mode realizes.When implemented in software, can be by above-mentioned functions
It is stored in computer-readable medium or is transmitted as the one or more instructions on computer-readable medium or code.Meter
Calculation machine computer-readable recording medium includes computer-readable storage medium and communication media, and wherein communication media includes being easy to from a place to another
The individual local any medium transmitting computer program.Storage medium can be any usable medium that computer can access.With
As a example by this but be not limited to: computer-readable medium can include random access memory (Random Access Memory,
RAM), read only memory (Read-Only Memory, ROM), EEPROM (Electrically
Erasable Programmable Read-Only Memory, EEPROM), read-only optical disc (Compact Disc Read-
Only Memory, CD-ROM) or other optical disc storage, magnetic disk storage medium or other magnetic storage apparatus or can be used in
Carry or store and there is instruction or the desired program code of data structure form can be by any other of computer access
Medium.In addition.Any connection can be suitable become computer-readable medium.Such as, if software is to use coaxial cable, light
Fine optical cable, twisted-pair feeder, Digital Subscriber Line (Digital Subscriber Line, DSL) or such as infrared ray, radio and
The wireless technology of microwave etc from website, server or other remote source, then coaxial cable, optical fiber cable, double
The wireless technology of twisted wire, DSL or such as infrared ray, wireless and microwave etc be included in affiliated medium fixing in.Such as this
Bright used, dish (Disk) and dish (disc) include compress laser disc (CD), laser dish, laser disc, Digital Versatile Disc (DVD),
Floppy disk and Blu-ray Disc, the duplication data of the usual magnetic of its mid-game, dish then carrys out the duplication data of optics with laser.Group above
Close within should also be as being included in the protection domain of computer-readable medium.
In a word, the foregoing is only the preferred embodiment of technical solution of the present invention, be not intended to limit the present invention's
Protection domain.All within the spirit and principles in the present invention, any modification, equivalent substitution and improvement etc. made, should be included in
Within protection scope of the present invention.
Claims (6)
1. a voltage based on multi core chip reduces method, it is characterised in that described method comprises the steps: to detect each
The voltage of kernel and the thread of operation;
Judge whether the voltage of this kernel exceedes voltage threshold;
Voltage such as this kernel exceedes voltage threshold, then reduce the number of threads of this kernel.
Method the most according to claim 1, it is characterised in that described method also includes:
It is assigned in other kernels run by the thread of this kernel reduced.
Method the most according to claim 1, it is characterised in that described method also includes:
The thread of this kernel reduced is evenly distributed in other kernels operation.
4. a voltage based on multi core chip reduces system, it is characterised in that described system includes:
Detector unit, for detecting the voltage of each kernel and the thread of operation;
Judging unit, for judging whether the voltage of this kernel exceedes voltage threshold;
Reduce unit, exceed voltage threshold for the voltage such as this kernel, then reduce the number of threads of this kernel.
System the most according to claim 4, it is characterised in that described system also includes:
Allocation unit, for being assigned in other kernels run by the thread of this kernel reduced.
System the most according to claim 4, it is characterised in that described system also includes:
All subdivisions, for being evenly distributed in other kernels operation by the thread of this kernel reduced.
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CN201610600313.XA CN106292996A (en) | 2016-07-27 | 2016-07-27 | Voltage based on multi core chip reduces method and system |
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CN201610600313.XA CN106292996A (en) | 2016-07-27 | 2016-07-27 | Voltage based on multi core chip reduces method and system |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2018018449A1 (en) * | 2016-07-27 | 2018-02-01 | 李媛媛 | Multi-core chip-based voltage reduction method and system |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030184271A1 (en) * | 2000-12-20 | 2003-10-02 | Kazuo Aisaka | Eletronic circuit of low power consumption, and power consumption reducing method |
CN101076770A (en) * | 2004-09-28 | 2007-11-21 | 英特尔公司 | Method and apparatus for varying energy per instruction according to the amount of available parallelism |
CN101341456A (en) * | 2005-12-21 | 2009-01-07 | Nxp股份有限公司 | Schedule based cache/memory power minimization technique |
-
2016
- 2016-07-27 CN CN201610600313.XA patent/CN106292996A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030184271A1 (en) * | 2000-12-20 | 2003-10-02 | Kazuo Aisaka | Eletronic circuit of low power consumption, and power consumption reducing method |
CN101076770A (en) * | 2004-09-28 | 2007-11-21 | 英特尔公司 | Method and apparatus for varying energy per instruction according to the amount of available parallelism |
CN101341456A (en) * | 2005-12-21 | 2009-01-07 | Nxp股份有限公司 | Schedule based cache/memory power minimization technique |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2018018449A1 (en) * | 2016-07-27 | 2018-02-01 | 李媛媛 | Multi-core chip-based voltage reduction method and system |
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Application publication date: 20170104 |