CN106257685B - 针对具有高电阻操作晶圆的绝缘体上硅衬底的装置结构 - Google Patents
针对具有高电阻操作晶圆的绝缘体上硅衬底的装置结构 Download PDFInfo
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Abstract
本发明涉及针对具有高电阻操作晶圆的绝缘体上硅衬底的装置结构,其利用包括高电阻操作晶圆的绝缘体上硅衬底的装置结构以及形成装置结构的方法。在该高电阻操作晶圆中形成掺杂区。形成穿过该绝缘体上硅衬底的装置层及绝缘体埋层延伸至该高电阻操作晶圆的第一沟槽。该掺杂区包括相对该第一沟槽横向延伸的该掺杂区的横向延伸部分。在该第一沟槽内外延生长半导体层,以及利用该半导体层的至少部分形成装置结构。形成穿过该装置层及该绝缘体埋层延伸至该掺杂区的该横向延伸部分的第二沟槽,以及在该第二沟槽中形成导电插塞。该掺杂区及该插塞包括体接触。
Description
技术领域
本发明通常涉及半导体装置及集成电路制造,尤其涉及双极结型晶体管的制造方法及装置结构。
背景技术
除其它终端使用以外,双极结型晶体管可见于高频及高功率应用中。尤其,双极结型晶体管在无线通信***及移动装置的放大器、开关及振荡器中可获得特定的终端使用。双极结型晶体管也可用于高速逻辑电路。双极结型晶体管是三终端电子装置,其包括由不同半导体材料区定义的发射极、本征基极(intrinsic base)以及集电极(collector)。在该装置结构中,本征基极位于发射极与集电极之间。NPN双极结型晶体管可包括构成发射极及集电极的n型半导体材料区,以及构成本征基极的p型半导体材料区。PNP双极结型晶体管包括构成发射极及集电极的p型半导体材料区,以及构成本征基极的n型半导体材料区。于工作时,基极-发射极结正向偏置且基极-集电极结反向偏置。集电极-发射极电流可由基极-发射极电压控制。
双极结型晶体管需要改进的制造方法及装置结构。
发明内容
在本发明的一个实施例中,提供一种方法以利用包括高电阻操作晶圆的绝缘体上硅衬底形成装置结构。在该高电阻操作晶圆中形成掺杂区。形成穿过该绝缘体上硅衬底的装置层及绝缘体埋层延伸至该高电阻操作晶圆的第一沟槽。该掺杂区包括相对该第一沟槽横向延伸的横向延伸部分。在该第一沟槽内外延生长半导体层,以及利用该半导体层的至少部分形成装置结构。形成穿过该装置层及该绝缘体埋层延伸至该掺杂区的该横向延伸部分的第二沟槽,以及在该第二沟槽中形成导电插塞。该掺杂区及该插塞包括体接触。
在本发明的一个实施例中,利用具有高电阻操作晶圆、绝缘体埋层及装置层的绝缘体上硅衬底形成装置结构。该装置结构包括位于穿过该装置层及该绝缘体埋层延伸至该高电阻操作晶圆的第一沟槽中的半导体层。装置结构至少部分形成于该半导体层中。位于该高电阻操作晶圆中的掺杂区包括相对该第一沟槽横向延伸的该掺杂区的横向延伸部分。位于第二沟槽中的插塞穿过该装置层及该绝缘体埋层延伸至该掺杂区的该横向延伸部分。该掺杂区及该插塞包括体接触。
附图说明
包含于并构成本说明书的一部分的附图说明本发明的各种实施例,并与上面所作的本发明的概括说明以及下面所作的实施例的详细说明一起用于解释本发明的实施例。
图1至4显示依据本发明的一个实施例处于制造装置结构的制程方法的连续制造阶段中的衬底的部分的剖视图。
图5显示依据本发明的一个替代实施例通过制造装置结构的制程方法加工的衬底部分的剖视图。
图6显示依据本发明的一个替代实施例通过制造装置结构的制程方法加工的衬底部分的剖视图。
图7显示依据本发明的一个替代实施例通过制造装置结构的制程方法加工的衬底部分的剖视图。
图8A及8B显示依据本发明的一个替代实施例通过制造装置结构的制程方法加工的衬底部分的剖视图。
具体实施方式
请参照图1且依据本发明的一个实施例,绝缘体上半导体(semiconductor-on-insulator;SOI)衬底10包括装置层12、绝缘体埋层14以及高电阻操作晶圆16。装置层12通过介于中间的绝缘体埋层14与高电阻操作晶圆16隔开并远远薄于高电阻操作晶圆16。装置层12支撑于绝缘体埋层14的顶部表面14a上并通过绝缘体埋层14与高电阻操作晶圆16电性绝缘。绝缘体埋层14可由电性绝缘体组成,且尤其可构成由二氧化硅(例如SiO2)组成的氧化物埋层。高电阻操作晶圆16可以大于1kΩ-cm的电阻率为特征,且可由高电阻硅、蓝宝石、石英、氧化铝或其它合适的材料组成。
通过沉积硬掩膜、利用光刻及蚀刻制程图案化硬掩膜及装置层12以定义沟槽、沉积电性绝缘体以填充该些沟槽、利用化学机械抛光制程相对该硬掩膜平坦化该电性绝缘体以及移除该硬掩膜而在SOI衬底10的装置层12中可形成沟槽隔离区18。在一个实施例中,沟槽隔离区18可由通过低压化学气相沉积(low pressure chemical vapor phasedeposition;LPCVD)沉积的二氧化硅(SiO2)组成,且可完全穿过装置层12到达绝缘体埋层14的顶部表面14a。
在装置层12的顶部表面12a及沟槽隔离区18上形成介电层20。介电层20可由电性绝缘体组成,例如利用化学气相沉积(chemica vapor deposition;CVD)沉积的二氧化硅(SiO2)。
在介电层20的顶部表面上形成图案化掩膜22。掩膜22可由施加并通过光刻图案化的牺牲材料层组成。为此,该牺牲材料层可由光阻剂组成,该光阻剂通过旋涂制程施加、经预烘烤、暴露于穿过光掩膜投射的辐射、曝光后烘烤以及利用化学显影剂显影,从而在沟槽隔离区18中的开口的预定位置的图案化掩膜22中形成开口24。
通过向高电阻操作晶圆16中引入掺杂物浓度的离子注入可在高电阻操作晶圆16中形成掺杂区26。掺杂区26的导电类型与高电阻操作晶圆16的导电类型相反。在一个实施例中,该掺杂区接收掺杂物浓度,例如有效赋予p型导电性的周期表第III族的掺杂物(例如硼),且高电阻操作晶圆16包含具有有效赋予n型导电性的浓度的周期表的第V族的n型掺杂物(例如磷(P)、砷(As)或锑(Sb))。掺杂区26在高电阻操作晶圆16中提供低电阻区。
在形成掺杂区26以后可移除掩膜22。如果掩膜22由光阻剂组成,则掩膜22可通过灰化或溶剂剥离以及后续清洗制程来移除。
请参照图2,其中类似的附图标记表示图1中类似的特征,且在该制程方法的后续制造阶段中,使用蚀刻制程定义沟槽28,该沟槽穿过沟槽隔离区18及绝缘体埋层14延伸至高电阻操作晶圆16的顶部表面。沟槽28与掺杂区26对齐。通过使用衬垫氧化物以及在沟槽28的预定位置处定义的具有宽度W1的开口的蚀刻掩膜可形成沟槽28。为此,该蚀刻掩膜可包括光敏材料,例如光阻剂,其通过旋涂制程施加、经预烘烤、暴露于穿过光掩膜投射的光、曝光后烘烤以及利用化学显影剂显影,从而定义蚀刻掩膜。在具有该蚀刻掩膜的情况下,使用蚀刻制程以在该开口的位置处形成具有宽度W1的沟槽28。该蚀刻制程可以单个蚀刻步骤或多个蚀刻步骤执行,可依赖于一种或多种蚀刻化学材料,且可在具有蚀刻选择性的受控制条件下执行,以防止侵入高电阻操作晶圆16中。在通过该蚀刻制程形成沟槽28以后,可移除该掩膜层。如果该掩膜层由光阻剂组成,则该掩膜层可通过灰化或溶剂剥离以及后续的传统清洗制程移除。
掺杂区26(形成体接触的部分)具有宽度W2,宽度W2大于沟槽28的宽度W1。掺杂区26的较大宽度提供相对沟槽28横向延伸的掺杂区26的横向延伸部分31。在半导体层填充沟槽28以后的后续制造阶段中,掺杂区26的横向延伸部分31允许在穿过装置层12及绝缘体埋层14延伸至掺杂区26的不同沟槽中形成插塞。在该代表性实施例中,掺杂区26仅横向偏离沟槽28的一侧。不过,掺杂区26可经延伸以在沟槽28的两侧提供横向偏离。
不导电间隙壁30形成于沟槽28的侧壁上并可相对高电阻操作晶圆16的顶部表面16a垂直延伸。通过沉积由电性绝缘体组成的共形层,例如通过化学气相沉积沉积的氮化硅(Si3N4),并利用优先自水平表面移除该电性绝缘体的各向异性蚀刻制程(例如反应离子蚀刻)成形该共形层,可形成间隙壁30。
利用外延生长制程(例如选择性外延生长制程)在沟槽28内部可形成半导体层32。外延生长是一种制程,通过该制程在高电阻操作晶圆16的单晶半导体材料上沉积半导体层32的单晶半导体材料,且在该制程中,在半导体层32的半导体材料中复制高电阻操作晶圆16的单晶材料的晶向及结晶结构。在外延生长期间,构成半导体层32的半导体材料将获得衬底10的单晶半导体材料的晶向及结晶结构,该衬底的单晶半导体材料充当生长的模板。由于选择性外延生长制程的选择性质,构成半导体层32的半导体材料不会自绝缘体表面(例如形成半导体层32时存在的介电层20的顶部表面)进行外延生长的成核。
半导体层32包含掺杂物浓度,其提供具有与掺杂区26相反的导电类型的组成半导体材料。在一个实施例中,半导体层32包括具有有效赋予n型导电性的浓度的周期表的第V族的n型掺杂物(例如磷(P)、砷(As)或锑(Sb))。半导体层32可包括上部34以及与上部34相比具有较高掺杂物浓度的下部36,从而在掺杂物被活化以后,与上部34相比,下部36具有较高的电性导电性。掺杂物浓度差可大于或等于对下部36进行重掺杂的量级。
请参照图3,其中类似的附图标记表示图2中类似的特征,且在该制程方法的后续制造阶段中,通过沉积硬掩膜、利用光刻及蚀刻制程图案化该硬掩膜及半导体层32以定义沟槽、沉积电性绝缘体以填充该沟槽、利用化学机械抛光制程相对该硬掩膜平坦化该电性绝缘体以及移除该硬掩膜而在半导体层32中可形成沟槽隔离区38。在一个实施例中,沟槽隔离区38可由通过低压化学气相沉积沉积的二氧化硅组成。
沟槽隔离区38仅部分延伸穿过半导体层32的厚度。尤其,沟槽隔离区38穿过半导体层32的上部34进入半导体层32的下部36。沟槽隔离区38位于间隙壁30的横向内侧,以由半导体层32的上部34的部分及半导体层32的下部36的部分在沟槽隔离区38与间隙壁30之间定义集电极接触45。
装置结构40通过在该制程的前端工艺(front-end-of-line;FEOL)部分中利用半导体层32形成,且在该代表实施例中,利用半导体层32的上部34形成。装置结构40可为双极结型晶体管,其包括发射极41、位于半导体层32的上部34中的集电极、以及垂直位于发射极41与集电极之间的基极层42。如果发射极指状结构、集电极及基极的其中两个或全部三个都由不同的半导体材料组成,则装置结构40可被称为异质结双极晶体管(heterojunctionbipolar transistor;HBT)。装置结构40可被配置为功率放大器。
半导体层32内部的沟槽隔离区38将基极层42与集电极接触45隔开。基极层42可由半导体材料组成,例如合金硅-锗(SiGe),具有95原子百分比至50原子百分比范围内的硅(Si)含量以及5原子百分比至50原子百分比范围内的锗(Ge)含量。基极层42的锗含量可沿基极层42的厚度方向呈渐变(graded)和/或阶跃(graded)。基极层42可包括掺杂物,例如具有对组成半导体材料有效赋予p型导电性的选自周期表的第III族的p型掺杂物(例如硼)以及(选择性地)碳(C)以抑制该p型掺杂物的迁移率。通过低温外延生长制程,在半导体层32的顶部表面上可形成基极层42。
请参照图4,其中类似的附图标记表示图3中类似的特征,且在该制程方法的后续制造阶段中,可开设沟槽44,该沟槽穿过沟槽隔离区18及绝缘体埋层14延伸至高电阻操作晶圆16中的掺杂区26的横向延伸部分31。可施加可选保护层例如氮化硅,以在该沟槽形成制程期间覆盖装置结构40。体接触的插塞46形成于沟槽44中,并提供至掺杂区26的横向延伸部分31的导电路径。插塞46可由多晶硅组成,该多晶硅在沉积期间经掺杂以具有与掺杂区26相同的导电类型。在一个替代实施例中,插塞46可以对称方式位于离开集电极接触45的装置结构40的不止一侧上。可选择地,可用不同的导电体(例如金属导电体,如以氮化钛衬里的钨)填充沟槽44。插塞46可通过镶嵌(damascene)制程形成,在此情况下,在蚀刻沟槽44之前,在晶圆及装置结构40上方形成平面介电质。作为替代,沟槽44及插塞46可在形成装置结构40之前形成。
在该制程的前端工艺部分期间,在SOI衬底10的表面区域的至少部分上复制掺杂区26、半导体层32、半导体层32中的沟槽隔离区38、以及装置结构40。在SOI衬底10上的不同位置处可形成另一个装置结构48。装置结构48可为包括另一个双极结型晶体管的低噪声放大器、由场效应晶体管组成的开关、场效应晶体管、被动装置(例如电阻器或电容器)、可变电容等。
接着执行中端工艺(middle-of-line;MOL)及后端工艺(back-end-of-line;BEOL)制程,其包括硅化物形成、形成至装置结构40、48的局部互连结构的接触及布线、以及形成通过该局部互连结构与装置结构40、48耦接的互连结构的介电层、过孔插塞以及布线。例如二极管、电阻器、电容器、可变电容以及电感器等其它主动及被动电路元件可集成于该互连结构中并可用于集成电路中。
请参照图5,其中类似的附图标记表示图2中类似的特征且依据一个替代实施例,沟槽28可形成有上部54以及比上部54窄的下部52。沟槽28的窄下部52具有宽度W3且沟槽28的上部54具有宽度W1,宽度W1大于宽度W3。与掺杂区26相邻的半导体层32的下部36的部分56符合沟槽28的窄下部52的形状。
在一个实施例中,形成沟槽28的上部56的蚀刻制程的条件经控制以使上部54仅部分穿过绝缘体埋层14且不会贯穿至高电阻操作晶圆16及掺杂区26。在利用图案化掩膜22形成沟槽28的上部54以后,通过施加另一个蚀刻掩膜可形成沟槽28的窄下部52,以双镶嵌图案化及蚀刻方式,开口具有与宽度W3匹配的尺寸。沟槽28的下部52及上部54在形成间隙壁30及半导体层32之前形成。在形成间隙壁30及半导体层32以后,如上联系图3所述继续执行制程。
对沟槽28所作的引入窄下部52的更改可有效降低集电极-衬底电容并缩小面积。该缩小对于毫米波应用可能更为重要并允许调整集电极-衬底电容。
请参照图6,其中类似的附图标记表示图2中类似的特征且依据一个替代实施例,沟槽28可形成有比上部54宽的宽下部58。宽下部58位于沟槽28的基部并与高电阻操作晶圆16及掺杂区26相邻。沟槽28的宽下部58具有宽度W4,宽度W4大于沟槽28的上部54的宽度W1。与掺杂区26相邻的半导体层32的下部36的部分60符合沟槽28的宽下部58的形状。
在一个实施例中,通过在形成沟槽28的上部54且形成间隙壁30以后执行的湿化学蚀刻制程可形成沟槽28的宽下部58。在形成半导体层32以前形成沟槽28的上部54以及宽下部58。该湿化学蚀刻制程也加深沟槽28,以使基部与高电阻操作晶圆16及掺杂区26共同延伸。在形成半导体层32以后,如上联系图3所述继续执行制程。
沟槽28的宽下部58可促进终止下部58中的半导体层32的材料中的位错传播至沟槽28的周边。如此,可降低位错向沟槽28的上部54中的半导体层32中传播。
掺杂区26的宽度W2大于沟槽28的宽下部58的宽度W4。掺杂区26的较大宽度提供相对沟槽28的宽下部58横向延伸的掺杂区26的横向延伸部分31。在半导体层32填充沟槽28以后的后续制造阶段中,掺杂区26的横向延伸部分31允许在穿过装置层12及绝缘体埋层14延伸至掺杂区26的不同沟槽中形成插塞。
请参照图7,其中类似的附图标记表示图6中类似的特征且依据一个替代实施例,可从装置结构40的构造去除沟槽隔离区38并可在沟槽隔离区18的外部形成集电极接触45。基于集电极接触45在半导体层32的边界外部的重新定位,因此无需基极与集电极接触隔离,从而可去除沟槽隔离区38。集电极接触45可穿过沟槽隔离区18及绝缘体埋层14到达半导体层32的宽下部58。在形成半导体层32以后,如上联系图3所述继续执行制程。
请参照图8A、8B,其中类似的附图标记表示图5中的类似特征,可更改装置构造以添加形成于深沟槽72中的沟槽隔离70。沟槽隔离70及深沟槽72穿过装置层12或沟槽隔离区18以浅穿透深度进入高电阻操作晶圆16中。深沟槽72可与用于体接触的插塞46的沟槽同时形成,并可于插塞46与沟槽隔离70的材料不同时通过独立的沉积制程来填充。可用介电质例如二氧化硅填充沟槽隔离70,或者可用介电质作为衬里并用多晶硅填充。沟槽隔离70可用以将装置结构40与充当装置结构48的CMOS装置隔离。
本发明的实施例允许利用高电阻操作晶圆通过单一SOI技术生产功率放大器、低噪声放大器以及开关。
上述方法用于集成电路芯片的制造中。制造者可以原始晶圆形式(也就是作为具有多个未封装芯片的单个晶圆)、作为裸芯片、或者以封装形式分配最终的集成电路芯片。在后一种情况中,芯片设于单芯片封装中(例如塑料承载件,其具有附着至母板或其它更高层次承载件的引脚)或者多芯片封装中(例如陶瓷承载件,其具有单面或双面互连或嵌埋互连)。在任何情况下,接着将该芯片与其它芯片、分立电路元件和/或其它信号处理装置集成,作为(a)中间产品例如母板的部分,或者作为(b)最终产品的部分。该最终产品可为包括集成电路芯片的任意产品,涉及范围从玩具及其它低端应用直至具有显示器、键盘或其它输入装置以及中央处理器的先进电脑产品。
本文中引用术语例如“垂直”、“水平”等作为示例来建立参考框架,并非意图限制。本文中所使用的术语“水平”被定义为与半导体衬底的传统平面平行的平面,而不论其实际的三维空间取向。术语“垂直”及“正交”是指垂直于如刚刚所定义的水平面的方向。术语“横向”是指水平平面内的维度。
特征可与另一个元件“连接”或“耦接”,它可与该另一个元件直接连接或耦接,或者可存在一个或多个中间元件。如果不存在中间元件,则特征可与另一个元件“直接连接”或“直接耦接”。如存在至少一个中间元件,则特征可与另一个元件“非直接连接”或“非直接耦接”。
对本发明的各种实施例所作的说明是出于说明目的,而非意图详尽无遗或限于所揭露的实施例。许多修改及变更对于本领域的普通技术人员显而易见,而不背离所述实施例的范围及精神。本文中所使用的术语经选择以最佳解释实施例的原理、实际应用或在市场已知技术上的技术改进,或者使本领域的普通技术人员能够理解本文中所揭露的实施例。
Claims (20)
1.一种利用包括高电阻操作晶圆的绝缘体上硅衬底形成半导体装置结构的方法,该方法包括:
在该高电阻操作晶圆中形成掺杂区;
形成穿过该绝缘体上硅衬底的装置层及绝缘体埋层延伸至该高电阻操作晶圆的第一沟槽,该掺杂区具有相对该第一沟槽横向延伸的该掺杂区的横向延伸部分;
在该第一沟槽内外延生长半导体层;
利用该半导体层的至少部分形成第一装置结构;
形成穿过该装置层及该绝缘体埋层延伸至该掺杂区的该横向延伸部分的第二沟槽;以及
在该第二沟槽中形成导电插塞,
其中,该掺杂区及该插塞包括体接触,以及
其中,该第一沟槽具有位于该装置层以及与该装置层相邻的该绝缘体埋层的部分内的具有第一宽度的第一部分,且该第一沟槽具有位于邻近该高电阻操作晶圆的该绝缘体埋层内的具有第二宽度的第二部分。
2.如权利要求1所述的方法,其中,该半导体层在邻近该高电阻操作晶圆处比邻近该装置层的顶部表面处具有较高的掺杂物浓度。
3.如权利要求1所述的方法,还包括:
利用该装置层形成第二装置结构。
4.如权利要求3所述的方法,其中,该第一装置结构为功率放大器。
5.如权利要求1所述的方法,其中,在该高电阻操作晶圆中形成该掺杂区包括:
将掺杂物注入该高电阻操作晶圆,以形成该掺杂区。
6.如权利要求5所述的方法,其中,该第一沟槽延伸穿过该装置层中的沟槽隔离区,以及形成该导电插塞包括:
用导电体填充该第二沟槽。
7.如权利要求1所述的方法,还包括:
在该半导体层上形成基极层;以及
在该半导体层中形成沟槽隔离区,以将该基极层与该半导体层中的集电极接触区隔离。
8.如权利要求1所述的方法,其中,该第一沟槽的该第二宽度小于该第一沟槽的该第一宽度。
9.如权利要求1所述的方法,其中,该第一沟槽的该第二宽度大于该第一沟槽的该第一宽度,以及还包括:
形成穿过该装置层及该绝缘体埋层延伸至该第一沟槽的该第二部分中的该半导体层的部分的集电极接触。
10.如权利要求1所述的方法,还包括:
邻近该第一沟槽形成穿过该装置层及该绝缘体埋层延伸至该高电阻操作晶圆中的深沟槽隔离。
11.如权利要求1所述的方法,其中,该第一沟槽与该第二沟槽相邻,且该掺杂区与该第一沟槽及该第二沟槽对齐。
12.一种利用具有高电阻操作晶圆、绝缘体埋层及装置层的绝缘体上硅衬底形成的半导体装置结构,该半导体装置结构包括:
半导体层,位于穿过该装置层及该绝缘体埋层延伸至该高电阻操作晶圆的第一沟槽中;
第一装置结构,至少部分位于该半导体层中;
掺杂区,位于该高电阻操作晶圆中,该掺杂区具有相对该第一沟槽横向延伸的该掺杂区的横向延伸部分;以及
插塞,位于穿过该装置层及该绝缘体埋层延伸至该掺杂区的该横向延伸部分的第二沟槽中,
其中,该掺杂区及该插塞包括体接触,以及
其中,该第一沟槽具有位于该装置层以及与该装置层相邻的该绝缘体埋层的部分内的具有第一宽度的第一部分,且该第一沟槽具有位于邻近该高电阻操作晶圆的该绝缘体埋层内的具有第二宽度的第二部分。
13.如权利要求12所述的半导体装置结构,其中,该半导体层在邻近该高电阻操作晶圆处比邻近该装置层的顶部表面处具有较高的掺杂物浓度。
14.如权利要求12所述的半导体装置结构,还包括:
利用该装置层形成第二装置结构,
其中,该第一装置结构为功率放大器。
15.如权利要求12所述的半导体装置结构,其中,该第一沟槽延伸穿过该装置层中的沟槽隔离区。
16.如权利要求12所述的半导体装置结构,还包括:
基极层,位于该半导体层上;
集电极接触区,位于该半导体层中;以及
沟槽隔离区,位于该半导体层中,该沟槽隔离区将该基极层与该集电极接触区隔离。
17.如权利要求12所述的半导体装置结构,其中,该第一沟槽的该第二宽度小于该第一沟槽的该第一宽度。
18.如权利要求12所述的半导体装置结构,其中,该第一沟槽的该第二宽度大于该第一沟槽的该第一宽度,以及还包括:
集电极接触,其穿过该装置层及该绝缘体埋层延伸至该第一沟槽的该第二部分中的该半导体层的部分。
19.如权利要求12所述的半导体装置结构,还包括:
深沟槽隔离,其邻近该第一沟槽穿过该装置层及该绝缘体埋层延伸至该高电阻操作晶圆中。
20.如权利要求12所述的半导体装置结构,其中,该第一沟槽与该第二沟槽相邻,且该掺杂区与该第一沟槽及该第二沟槽对齐。
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US10608124B2 (en) * | 2018-04-19 | 2020-03-31 | Qualcomm Incorporated | Back silicided variable capacitor devices |
US10600894B2 (en) * | 2018-07-03 | 2020-03-24 | Qualcomm Incorporated | Bipolar junction transistor and method of fabricating the same |
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US11271077B2 (en) * | 2020-03-03 | 2022-03-08 | Globalfoundries U.S. Inc. | Trap-rich layer in a high-resistivity semiconductor layer |
US11177345B1 (en) * | 2020-06-05 | 2021-11-16 | Globalfoundries U.S. Inc. | Heterojunction bipolar transistor |
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