CN106257685A - Apparatus structure for the silicon-on-insulator substrate with high resistance operation wafer - Google Patents
Apparatus structure for the silicon-on-insulator substrate with high resistance operation wafer Download PDFInfo
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- CN106257685A CN106257685A CN201610460390.XA CN201610460390A CN106257685A CN 106257685 A CN106257685 A CN 106257685A CN 201610460390 A CN201610460390 A CN 201610460390A CN 106257685 A CN106257685 A CN 106257685A
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- 239000012212 insulator Substances 0.000 title claims abstract description 48
- 239000000758 substrate Substances 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 claims abstract description 69
- 238000000034 method Methods 0.000 claims abstract description 51
- 238000002955 isolation Methods 0.000 claims description 11
- 239000002019 doping agent Substances 0.000 claims description 9
- 239000000126 substance Substances 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 5
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 90
- 238000004519 manufacturing process Methods 0.000 description 27
- 238000012545 processing Methods 0.000 description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 15
- 239000000463 material Substances 0.000 description 15
- 230000008569 process Effects 0.000 description 13
- 238000005530 etching Methods 0.000 description 12
- 238000000151 deposition Methods 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 7
- 239000013078 crystal Substances 0.000 description 6
- 230000008021 deposition Effects 0.000 description 5
- 239000000203 mixture Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000000737 periodic effect Effects 0.000 description 4
- 239000000047 product Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000012822 chemical development Methods 0.000 description 2
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- 230000008878 coupling Effects 0.000 description 2
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- 238000005859 coupling reaction Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000007792 gaseous phase Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000012071 phase Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 229910000967 As alloy Inorganic materials 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
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- 230000009977 dual effect Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 210000004349 growth plate Anatomy 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000000411 inducer Substances 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
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- 239000011241 protective layer Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- 238000003631 wet chemical etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/70—Bipolar devices
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Abstract
The present invention relates to the apparatus structure for the silicon-on-insulator substrate with high resistance operation wafer, its apparatus structure utilizing the silicon-on-insulator substrate including high resistance operation wafer and the method forming apparatus structure.Doped region is formed in this high resistance operation wafer.Form device layers and buried insulator layer through this silicon-on-insulator substrate to extend to this high resistance and operate the first groove of wafer.This doped region includes the lateral extension portions of this doped region that this first channel lateral extends relatively.At this first groove epitaxial growth semiconductor layer, and utilize this semiconductor layer be at least a partially formed apparatus structure.Form the second groove of this lateral extension portions extending to this doped region through this device layers and this buried insulator layer, and in this second groove, form conductive plunger.This doped region and this connector include that body contacts.
Description
Technical field
The present invention relates generally to semiconductor device and IC manufacturing, particularly relate to the manufacturer of bipolar junction transistor
Method and apparatus structure.
Background technology
In addition to other terminal uses, bipolar junction transistor is found in high frequency and high power applications.Especially, bipolar junction
Transistor npn npn can obtain specific terminal in wireless communication system and the amplifier of mobile device, switch and agitator and use.
Bipolar junction transistor can also be used for high speed logic circuits.Bipolar junction transistor is three terminal electronics, and it includes by not
Emitter stage, intrinsic base stage (intrinsic base) and colelctor electrode (collector) with semi-conducting material area definition.At this
In apparatus structure, intrinsic base stage is between emitter stage and colelctor electrode.Npn bipolar junction transistor can include constitute emitter stage and
The n-type semiconductor district of colelctor electrode, and constitute the p-type semiconductor material district of intrinsic base stage.Pnp bipolar junction transistor bag
Include composition emitter stage and the p-type semiconductor material district of colelctor electrode, and constitute the n-type semiconductor district of intrinsic base stage.Yu Gong
When making, base-emitter junction forward bias and base-collector junction reverse bias.Collector-emitter current can by base stage-
Emitter voltage controls.
Bipolar junction transistor needs manufacture method and the apparatus structure improved.
Summary of the invention
In one embodiment of the invention, it is provided that a kind of method is to utilize on the insulator including high resistance operation wafer
Silicon substrate forms apparatus structure.Doped region is formed in this high resistance operation wafer.Formed through this silicon-on-insulator substrate
Device layers and buried insulator layer extend to the first groove of this high resistance operation wafer.This doped region includes this first groove relatively
The lateral extension portions of horizontal expansion.At this first groove epitaxial growth semiconductor layer, and utilize this semiconductor layer extremely
Small part forms apparatus structure.Form this lateral extensions extending to this doped region through this device layers and this buried insulator layer
The second groove divided, and in this second groove, form conductive plunger.This doped region and this connector include that body contacts.
In one embodiment of the invention, utilization has the exhausted of high resistance operation wafer, buried insulator layer and device layers
On edge body, silicon substrate forms apparatus structure.This apparatus structure includes being located across this device layers and this buried insulator layer extends to this
Semiconductor layer in first groove of high resistance operation wafer.Apparatus structure is at least partly formed in this semiconductor layer.It is positioned at
Doped region in this high resistance operation wafer includes the lateral extension portions of this doped region that this first channel lateral extends relatively.
The connector being positioned in the second groove extends to this lateral extension portions of this doped region through this device layers and this buried insulator layer.
This doped region and this connector include that body contacts.
Accompanying drawing explanation
Be contained in and constitute this specification a part accompanying drawing explanation various embodiments of the present invention, and with made above
The general description of the present invention and the detailed description of embodiment made below together for explaining embodiments of the invention.
Fig. 1 to 4 display is in the continuous manufacture of the manufacturing method thereof manufacturing apparatus structure according to one embodiment of the present of invention
The sectional view of the part of the substrate in the stage.
Fig. 5 shows that an alternate embodiment according to the present invention is by manufacturing the substrate of the manufacturing method thereof processing of apparatus structure
The sectional view of part.
Fig. 6 shows that an alternate embodiment according to the present invention is by manufacturing the substrate of the manufacturing method thereof processing of apparatus structure
The sectional view of part.
Fig. 7 shows that an alternate embodiment according to the present invention is by manufacturing the substrate of the manufacturing method thereof processing of apparatus structure
The sectional view of part.
Fig. 8 A and 8B display is processed by manufacturing the manufacturing method thereof of apparatus structure according to an alternate embodiment of the present invention
The sectional view of substrate portions.
Detailed description of the invention
Refer to Fig. 1 and according to one embodiment of the present of invention, semiconductor-on-insulator (semiconductor-on-
insulator；SOI) substrate 10 includes device layers 12, buried insulator layer 14 and high resistance operation wafer 16.Device layers 12 is led to
Cross buried insulator layer 14 between and high resistance operation wafer 16 separates and significantly less thick than high resistance operates wafer 16.Device
Layer 12 is supported on the top surface 14a of buried insulator layer 14 and electrical with high resistance operation wafer 16 by buried insulator layer 14
Insulation.Buried insulator layer 14 can be made up of the body that is electrically insulated, and especially may make up by silicon dioxide (such as SiO2) oxygen that forms
Compound buried regions.High resistance operation wafer 16 can be characterized more than the resistivity of 1k Ω-cm, and can by high resistance silicon, sapphire,
Quartz, aluminium oxide or other suitable material composition.
By depositing hard mask, utilizing photoetching and etch process patterned hard mask and device layers 12 to define groove, to sink
Amass and be electrically insulated body to fill those grooves, to utilize chemical mechanical polishing manufacture procedure to planarize this body that is electrically insulated relative to this hard mask
And remove this hard mask and channel separating zone 18 can be formed in the device layers 12 of SOI substrate 10.In one embodiment, ditch
Groove isolation area 18 can be by by low-pressure chemical vapor deposition (low pressure chemical vapor phase
deposition；LPCVD) silicon dioxide (SiO deposited2) composition, and can pass completely through device layers 12 and arrive buried insulator layer
The top surface 14a of 14.
The top surface 12a and channel separating zone 18 of device layers 12 are formed dielectric layer 20.Dielectric layer 20 can be by electrically
Insulator forms, such as, utilize chemical gaseous phase to deposit (chemica vapor deposition；CVD) silicon dioxide deposited
(SiO2)。
The top surface of dielectric layer 20 is formed patterned mask 22.Mask 22 by applying and can pass through lithographic patterning
Sacrificial material layer composition.To this end, this sacrificial material layer can be made up of photoresist, this photoresist is applied by spin coating processing procedure, warp
Prebake conditions, it is exposed to through radiation, the postexposure bake of photomask projection and utilizes chemical development to develop, thus at groove
The patterned mask 22 in the precalculated position of the opening in isolation area 18 is formed opening 24.
Wafer 16 can be operated at high resistance by the ion implanting introducing concentration of dopant in high resistance operation wafer 16
Middle formation doped region 26.The conduction type of doped region 26 is contrary with the conduction type of high resistance operation wafer 16.An enforcement
In example, this doped region receives concentration of dopant, the such as effectively alloy of the periodic chart III-th family of imparting p-type electric conductivity (such as
Boron), and high resistance operation wafer 16 comprises the N-shaped doping of group V of the periodic chart with the concentration effectively giving n-type conductivity
Thing (such as phosphorus (P), arsenic (As) or antimony (Sb)).Doped region 26 provides low-resistance region in high resistance operation wafer 16.
Removable mask 22 after forming doped region 26.If mask 22 is made up of photoresist, then mask 22 can pass through
Ashing or solvent peel off and follow-up manufacturing process for cleaning removes.
Refer to Fig. 2, wherein similar reference represents feature similar in Fig. 1, and follow-up at this manufacturing method thereof
In fabrication stage, using etch process definition groove 28, this groove extends to through channel separating zone 18 and buried insulator layer 14
The top surface of high resistance operation wafer 16.Groove 28 aligns with doped region 26.By using pad oxide and at groove
The etching mask of the opening with width W1 of the pre-position definition of 28 can form groove 28.To this end, this etching mask can
Including light-sensitive material, such as photoresist, its by spin coating processing procedure apply, through prebake conditions, be exposed to through photomask projection light,
Postexposure bake and utilize chemical development to develop, thus define etching mask.In the case of there is this etching mask, make
With etch process to form the groove 28 with width W1 in the position of this opening.This etch process can be with single etching step
Or multiple etching step performs, can be dependent on one or more etching chemistry materials, and can have the controlled of etching selectivity
Perform under the conditions of system, to prevent from invading in high resistance operation wafer 16.After forming groove 28 by this etch process, can move
Except this mask layer.If this mask layer is made up of photoresist, then this mask layer can be peeled off and follow-up by ashing or solvent
Conventional cleaning processes removes.
Doped region 26 (forming the part of body contact) has width W2, the width W2 width W1 more than groove 28.Doped region
The bigger width of 26 provides the lateral extension portions 27 of the doped region 26 of opposed channels 28 horizontal expansion.Ditch is filled at semiconductor layer
In the subsequent stage of fabrication that groove 28 is later, the lateral extension portions 27 of doped region 26 allows burying through device layers 12 and insulator
Layer 14 extends to be formed in the different grooves of doped region 26 connector.In this representative embodiment, doped region 26 merely transversely deviates
The side of groove 28.But, doped region 26 can be extended to provide lateral run-out in the both sides of groove 28.
Non-conductive clearance wall 30 be formed on the sidewall of groove 28 and can relatively high resistance operation wafer 16 top surface
16a extends vertically.The conforma layer being made up of the body that is electrically insulated deposition, such as by the silicon nitride of chemical gaseous phase deposition deposition
(Si3N4), and utilize anisotropic etching processing procedure (the such as reactive ion erosion preferentially removing this body that is electrically insulated from horizontal surface
Carve) shape this conforma layer, clearance wall 30 can be formed.
Utilize epitaxial growth process (such as selective epitaxial growth processing procedure) that semiconductor layer 32 can be formed inside groove 28.
Epitaxial growth is a kind of processing procedure, by this processing procedure deposited semiconductor layer on the single-crystal semiconductor material of high resistance operation wafer 16
The single-crystal semiconductor material of 32, and in this processing procedure, the semi-conducting material of semiconductor layer 32 replicates high resistance operation wafer
The crystal orientation of the monocrystal material of 16 and crystalline texture.During epitaxial growth, the semi-conducting material constituting colelctor electrode base 30 will obtain
Obtaining crystal orientation and the crystalline texture of the single-crystal semiconductor material of substrate 10, the single-crystal semiconductor material of this substrate serves as the mould of growth
Plate.Due to the selection character of selective epitaxial growth processing procedure, the semi-conducting material constituting semiconductor layer 32 will not self-insulating body surface
Face (top surface of the dielectric layer 20 existed when such as forming semiconductor layer 32) carries out epitaxially grown nucleation.
Semiconductor layer 32 comprises concentration of dopant, and it provides the composition with the conduction type contrary with doped region 26 partly to lead
Body material.In one embodiment, semiconductor layer 32 includes the V with the periodic chart of the concentration effectively giving n-type conductivity
The n-type dopant (such as phosphorus (P), arsenic (As) or antimony (Sb)) of race.Semiconductor layer 32 can include top 34 and with top 34 phase
Ratio has the bottom 36 of higher-doped substrate concentration, thus after alloy is activated to, compared with top 34, bottom 36 has relatively
High electrical electric conductivity.Concentration of dopant difference can be more than or equal to bottom 36 is carried out heavily doped magnitude.
Refer to Fig. 3, wherein similar reference represents feature similar in Fig. 2, and follow-up at this manufacturing method thereof
In fabrication stage, by depositing hard mask, utilizing photoetching and etch process to pattern this hard mask and semiconductor layer 32 with definition
Groove, deposition be electrically insulated body to fill this groove, to utilize chemical mechanical polishing manufacture procedure to planarize this relative to this hard mask electrical
Insulator and remove this hard mask and channel separating zone 38 can be formed in semiconductor layer 32.In one embodiment, groove
Isolation area 38 can be made up of the silicon dioxide deposited by low-pressure chemical vapor deposition.
Channel separating zone 38 extends only partly through the thickness of semiconductor layer 32.Especially, channel separating zone 38 is through partly leading
The top 34 of body layer 32 enters the bottom 36 of semiconductor layer 32.Channel separating zone 38 is positioned at the laterally inboard of clearance wall 30, with by
The part of the part on the top 34 of semiconductor layer 32 and the bottom 36 of semiconductor layer 32 in channel separating zone 38 and clearance wall 30 it
Between define collector contact 45.
Apparatus structure 40 is by the front-end process (front-end-of-line at this processing procedure；FEOL) part utilizes half
Conductor layer 32 is formed, and in this represents embodiment, utilizes the top 34 of semiconductor layer 32 to be formed.Apparatus structure 40 can be bipolar
Junction transistor, it includes emitter stage 41, colelctor electrode in the top 34 that is positioned at semiconductor layer 32 and be vertically positioned at emitter stage
Base layer 42 between 41 and colelctor electrode.If the two of which of emitter stage finger, colelctor electrode and base stage or whole three
All be made up of different semi-conducting materials, then apparatus structure 40 is referred to alternatively as heterojunction bipolar transistor (heterojunction
bipolar transistor；HBT).Apparatus structure 40 can be configured to power amplifier.
Base layer 42 is separated by the channel separating zone 38 within semiconductor layer 32 with collector contact 45.Base layer 42 can be by
Semi-conducting material forms, and such as alloy silicon-germanium (SiGe) has the silicon in 95 atomic percents to 50 atomic percent range
(Si) germanium (Ge) content in content and 5 atomic percents to 50 atomic percent range.The Ge content of base layer 42 can edge
The thickness direction of base layer 42 is gradual change (graded) and/or step (graded).Base layer 42 can include alloy, such as, have
By to form semi-conducting material effective imparting p-type electric conductivity the III-th family selected from periodic chart p-type dopant (such as boron) with
And (optionally) carbon (C) is to suppress the mobility of this p-type dopant.By low-temperature epitaxy growth processing procedure, at semiconductor layer 32
Top surface on can form base layer 42.
Refer to Fig. 4, wherein similar reference represents feature similar in Fig. 3, and follow-up at this manufacturing method thereof
In fabrication stage, can offer groove 44, this groove extends to high resistance operation through channel separating zone 18 and buried insulator layer 14
The lateral extension portions 27 of the doped region 26 in wafer 16.Optional protective layer such as silicon nitride can be applied, to be formed at this groove
Cladding system structure 40 during processing procedure.The connector 46 of body contact is formed in groove 44, and provides laterally prolonging to doped region 26
Extending portion divides the conductive path of 27.Connector 46 can be made up of polysilicon, and this polysilicon is doped to have and doping during depositing
The conduction type that district 26 is identical.In an alternative embodiment, connector 46 can be positioned away from collector contact 45 in a symmetrical
Apparatus structure 40 more than side on.Selectively, (such as metallic conductor, as with titanium nitride for available different electric conductor
The tungsten of lining) fill groove 44.Connector 46 can be formed by inlaying (damascene) processing procedure, in the case, at etching groove
Before 44, above wafer and apparatus structure 40, form flat dielectric matter.As an alternative, groove 44 and connector 46 can form dress
Formed before putting structure 40.
During the FEOL portion of this processing procedure, the region, surface of SOI substrate 10 at least part of on replicate doping
Channel separating zone 38 in district 26, semiconductor layer 32, semiconductor layer 32 and apparatus structure 40.Difference in SOI substrate 10
Position can form another apparatus structure 48.Apparatus structure 48 can be that the low noise including another bipolar junction transistor is put
Big device, the switch being made up of field-effect transistor, field-effect transistor, passive device (such as resistor or capacitor), variable
Electric capacity etc..
Then middle-end technique (middle-of-line is performed；And backend process (back-end-of-line MOL)；BEOL)
Processing procedure, it includes that silicide forms, formed contact and the wiring of the local interlinkage structure to apparatus structure 40,48 and formed
The dielectric layer of interconnection structure, via connector and the wiring coupled with apparatus structure 40,48 by this local interlinkage structure.Such as
Other active such as diode, resistor, capacitor, variable capacitance and inducer and passive component can be integrated in this interconnection
In structure and can be used in integrated circuit.
Refer to Fig. 5, wherein similar reference represents feature similar in Fig. 2 and according to an alternate embodiment,
Groove 28 can be formed with top 54 and the bottom 52 narrower than top 54.The narrow lower portion 52 of groove 28 has width W3 and groove 28
Top 54 there is width W1, width W1 more than width W3.The part of the bottom 36 of the semiconductor layer 32 adjacent with doped region 26
The shape of 56 narrow lower portions 52 meeting groove 28.
In one embodiment, the condition of etch process on the top 56 of groove 28 is formed through controlling so that only portion, top 54
Divide through buried insulator layer 14 and high resistance operation wafer 16 and doped region 26 will not be through to.Utilizing patterned mask 22 shape
After becoming the top 54 of groove 28, the narrow lower portion 52 of groove 28 can be formed by applying another etching mask, with dual damascene figure
Case and etching mode, opening has the size mated with width W3.Clearance wall is being formed at bottom 52 and the top 54 of groove 28
30 and semiconductor layer 32 before formed.After forming clearance wall 30 and semiconductor layer 32, as above continue executing with described in contact Fig. 3
Processing procedure.
The change introducing narrow lower portion 52 being made groove 28 can effectively reduce collector-substrate cpacity and reduce area.
This reduces and is likely more important for Millimeter Wave Applications and allows to adjust collector-substrate cpacity.
Refer to Fig. 6, wherein similar reference represents feature similar in Fig. 2 and according to an alternate embodiment,
Groove 28 can be formed with the wide bottom 58 wider than top 54.Wide bottom 58 is positioned at the base portion of groove 28 and operates wafer with high resistance
16 and doped region 26 adjacent.The wide bottom 58 of groove 28 has width W4, the width W4 width W1 more than the top 54 of groove 28.
The part 60 of the bottom 36 of the semiconductor layer 32 adjacent with doped region 26 meets the shape of the wide bottom 58 of groove 28.
In one embodiment, by forming the top 54 of groove 28 and forming the wet-chemical that clearance wall 30 performs later
Etch process can form the wide bottom 58 of groove 28.Under formation semiconductor layer 32 is previously formed top 54 and the width of groove 28
Portion 58.This wet chemical etching processing procedure also adds deep trench 28, so that base portion prolongs jointly with high resistance operation wafer 16 and doped region 26
Stretch.After forming semiconductor layer 32, as above continue executing with processing procedure described in contact Fig. 3.
The wide bottom 58 of groove 28 can promote that the dislocation propagation terminating in the material of the semiconductor layer 32 in bottom 58 is to ditch
The periphery of groove 28.So, it is possible to decrease dislocation semiconductor layer 32 in the top 54 of groove 28 is propagated.
The width W2 of doped region 26 is more than the width W4 of the wide bottom 58 of groove 28.The bigger width of doped region 26 provides phase
Lateral extension portions 27 to the doped region 26 of wide bottom 58 horizontal expansion of groove 28.Semiconductor layer 32 fill groove 28 with
After subsequent stage of fabrication in, the lateral extension portions 27 of doped region 26 allows prolonging through device layers 12 and buried insulator layer 14
Extend formation connector in the different grooves of doped region 26.
Refer to Fig. 7, wherein similar reference represents feature similar in Fig. 6 and according to an alternate embodiment,
Channel separating zone 38 can be removed from the structure of apparatus structure 40 and collector contact 45 can be formed the outside of channel separating zone 18.
Based on collector contact 45 the reorientating of border outer of semiconductor layer 32, therefore without base stage and collector contact every
From, thus removable channel separating zone 38.Collector contact 45 may pass through channel separating zone 18 and buried insulator layer 14 arrives half
The wide bottom 58 of conductor layer 32.After forming semiconductor layer 32, as above continue executing with processing procedure described in contact Fig. 3.
Refer to Fig. 8 A, 8B, wherein similar reference represents the similar characteristics in Fig. 5, can change device structure with
Add the trench isolations 70 being formed in deep trench 72.Trench isolations 70 and deep trench 72 are through device layers 12 or channel separating zone
18 enter in high resistance operation wafer 16 with shallow penetration depth.The groove of the connector 46 that deep trench 72 can contact with for body is simultaneously
Formed, and can be filled by independent deposition manufacture process when connector 46 is different from the material of trench isolations 70.Available dielectric medium
The most silica-filled trench isolations 70, or available dielectric medium fills as lining and with polysilicon.Trench isolations 70 can
In order to apparatus structure 40 and the CMOS device serving as apparatus structure 48 are isolated.
Embodiments of the invention allow to utilize high resistance operation wafer by single SOI technology production power amplifier, low
Noise amplifier and switch.
Said method is in the manufacture of IC chip.Maker can be using original wafer form (namely as tool
Have the single wafer of multiple unpackaged chip), as bare chip or with the packing forms final IC chip of distribution.
In the later case, chip is located in single-chip package that (such as plastic carrier, it has and is attached to motherboard or other is higher
The pin of level bearing part) or multi-chip package in (such as pottery bearing part, it has single or double interconnection or is embedded into mutually
Even).Under any circumstance, then by this chip and other chip, discrete circuit element and/or other signal processing apparatus collection
Become, as the part of (a) intermediate products such as motherboard, or the part as (b) final products.These final products can be to include
Any products of IC chip, coverage from toy and other low-end applications until have display, keyboard or other
Input equipment and the advanced computer product of central processing unit.
Term cited herein such as " vertically ", " level " etc. set up reference frame as example, be not intended to limit.
Term used herein " level " is defined as the plane parallel with the conventional planar of Semiconductor substrate, regardless of whether it is actual
Three dimensions orientation.Term " vertically " and " orthogonal " refer to be perpendicular to the direction of horizontal plane as defined in just.Term is " horizontal
To " refer to the dimension in horizontal plane.
Feature can " be connected " with another element or " coupling ", and it can be directly connected to this another element or couple, or
One or more intermediary element can be there is in person.If there is no intermediary element, then feature " can be directly connected to " with another element
Or " directly coupling ".As there is at least one intermediary element, then feature can be with another element " indirect connection " or " non-immediate
Couple ".
Various embodiments of the present invention description is in order at illustration purpose, and is not intended to exhaustive or is limited to institute
The embodiment disclosed.Many modifications and changes are for it would be apparent to one of skill in the art that, without departing from described enforcement
The scope of example and spirit.Term used herein is selected to the principle of best interpretations embodiment, reality is applied or in city
Technological improvement on known technology, or make those of ordinary skill in the art it will be appreciated that enforcement disclosed herein
Example.
Claims (20)
1. utilization includes the method that the silicon-on-insulator substrate of high resistance operation wafer forms apparatus structure, the method bag
Include:
Doped region is formed in this high resistance operation wafer；
Form device layers and buried insulator layer through this silicon-on-insulator substrate and extend to the first of this high resistance operation wafer
Groove, this doped region has the lateral extension portions of this doped region that this first channel lateral extends relatively；
At this first groove epitaxial growth semiconductor layer；
Utilize this semiconductor layer is at least a partially formed first device structure；
Form the second groove of this lateral extension portions extending to this doped region through this device layers and this buried insulator layer；With
And
Conductive plunger is formed in this second groove,
Wherein, this doped region and this connector include that body contacts.
The most the method for claim 1, wherein this semiconductor layer operates this dress nearly near at wafer at this high resistance neighbouring
Put and there is at the top surface of layer higher concentration of dopant.
3. the method for claim 1, also includes:
This device layers is utilized to form the second apparatus structure.
4. method as claimed in claim 3, wherein, this first device structure is power amplifier.
The most the method for claim 1, wherein in this high resistance operation wafer, form this doped region to include:
Alloy is injected this high resistance operation wafer, to form this doped region.
6. method as claimed in claim 5, wherein, this first groove extends through the channel separating zone in this device layers, with
And form this conductive plunger and include:
This second groove is filled with electric conductor.
7. the method for claim 1, also includes:
This semiconductor layer is formed base layer；And
Channel separating zone is formed, this base layer to be separated with the collector contact in this semiconductor layer in this semiconductor layer
From.
The most the method for claim 1, wherein this first groove has and is positioned at this device layers and adjacent with this device layers
This buried insulator layer part in the Part I with the first width, this first groove has and is positioned at this high resistance neighbouring
The Part II with the second width in this buried insulator layer of operation wafer, and this second width is less than this first width.
The most the method for claim 1, wherein this first groove has and is positioned at this device layers and this buried insulator layer
The Part I with the first width in part, this first groove has this insulation being positioned at neighbouring this high resistance operation wafer
The Part II with the second width in body buried regions, and this second width is more than this first width, and also include:
Form this semiconductor layer in this Part II extending to this first groove through this device layers and this buried insulator layer
The collector contact of part.
10. the method for claim 1, also includes:
This first groove neighbouring formed through this device layers and this buried insulator layer extend in this high resistance operation wafer deep
Trench isolations.
11. the method for claim 1, wherein this first groove adjacent with this second groove, and this doped region with this
One groove and the alignment of this second groove.
12. 1 kinds of utilizations have the dress that the silicon-on-insulator substrate of high resistance operation wafer, buried insulator layer and device layers is formed
Putting structure, this apparatus structure includes:
Semiconductor layer, is located across this device layers and this buried insulator layer extends to this high resistance and operates the first groove of wafer
In；
First device structure, is at least partially disposed in this semiconductor layer；
Doped region, is positioned in this high resistance operation wafer, and this doped region has this doping that this first channel lateral extends relatively
The lateral extension portions in district；And
Connector, is located across this device layers and this buried insulator layer extends to second ditch of this lateral extension portions of this doped region
In groove,
Wherein, this doped region and this connector include that body contacts.
13. apparatus structures as claimed in claim 12, wherein, this semiconductor layer operates near at wafer at this high resistance neighbouring
At the top surface of this device layers nearly, there is higher concentration of dopant.
14. apparatus structures as claimed in claim 12, also include:
This device layers is utilized to form the second apparatus structure,
Wherein, this first device structure is power amplifier.
15. apparatus structures as claimed in claim 12, wherein, this first groove extends through the trench isolations in this device layers
District.
16. apparatus structures as claimed in claim 12, also include:
Base layer, is positioned on this semiconductor layer；
Collector contact district, is positioned in this semiconductor layer；And
Channel separating zone, is positioned in this semiconductor layer, this channel separating zone this base layer and this collector contact are separated from.
17. apparatus structures as claimed in claim 12, wherein, this first groove have be positioned at this device layers and with this device
The Part I with the first width in the part of adjacent this buried insulator layer of layer, this first groove have be positioned at neighbouring should
High resistance operation wafer this buried insulator layer in the Part II with the second width, and this second width less than this first
Width.
18. apparatus structures as claimed in claim 12, wherein, this first groove have be positioned at this device layers and with this device
The Part I with the first width in the part of adjacent this buried insulator layer of layer, this first groove have be positioned at neighbouring should
High resistance operation wafer this buried insulator layer in the Part II with the second width, and this second width more than this first
Width, and also include:
Collector contact, it extends to being somebody's turn to do in this Part II of this first groove through this device layers and this buried insulator layer
The part of semiconductor layer.
19. apparatus structures as claimed in claim 12, also include:
Deep trench isolation, it extends to this high resistance operation crystalline substance adjacent to this first groove through this device layers and this buried insulator layer
In circle.
20. apparatus structures as claimed in claim 12, wherein, this first groove is adjacent with this second groove, and this doped region
Align with this first groove and this second groove.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/745,704 | 2015-06-22 | ||
| US14/745,704 US10446644B2 (en) | 2015-06-22 | 2015-06-22 | Device structures for a silicon-on-insulator substrate with a high-resistance handle wafer |
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| Publication Number | Publication Date |
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| CN106257685A true CN106257685A (en) | 2016-12-28 |
| CN106257685B CN106257685B (en) | 2019-09-06 |
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| US (1) | US10446644B2 (en) |
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| CN113363309A (en) * | 2020-03-03 | 2021-09-07 | 格芯(美国)集成电路科技有限公司 | Trap rich layer in high resistivity semiconductor layer |
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| US10608124B2 (en) * | 2018-04-19 | 2020-03-31 | Qualcomm Incorporated | Back silicided variable capacitor devices |
| US10600894B2 (en) * | 2018-07-03 | 2020-03-24 | Qualcomm Incorporated | Bipolar junction transistor and method of fabricating the same |
| EP3671856B1 (en) * | 2018-12-21 | 2023-01-25 | IMEC vzw | A method for forming a group iii-v heterojunction bipolar transistor on a group iv substrate and corresponding heterojunction bipolar transistor device |
| US11177345B1 (en) * | 2020-06-05 | 2021-11-16 | Globalfoundries U.S. Inc. | Heterojunction bipolar transistor |
| FR3141798A1 (en) * | 2022-11-08 | 2024-05-10 | X-Fab France SAS | LOW NOISE AMPLIFIER |
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| TW201709338A (en) | 2017-03-01 |
| US10446644B2 (en) | 2019-10-15 |
| TWI657506B (en) | 2019-04-21 |
| CN106257685B (en) | 2019-09-06 |
| US20160372582A1 (en) | 2016-12-22 |
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