CN106252225A - The method preventing substrate impurity external diffusion - Google Patents
The method preventing substrate impurity external diffusion Download PDFInfo
- Publication number
- CN106252225A CN106252225A CN201610874737.5A CN201610874737A CN106252225A CN 106252225 A CN106252225 A CN 106252225A CN 201610874737 A CN201610874737 A CN 201610874737A CN 106252225 A CN106252225 A CN 106252225A
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- China
- Prior art keywords
- substrate
- oxide
- film
- external diffusion
- method preventing
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000000758 substrate Substances 0.000 title claims abstract description 57
- 238000009792 diffusion process Methods 0.000 title claims abstract description 24
- 239000012535 impurity Substances 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 title claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 10
- 238000001312 dry etching Methods 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052710 silicon Inorganic materials 0.000 abstract description 8
- 239000010703 silicon Substances 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000001052 transient effect Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- 208000033999 Device damage Diseases 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- APTZNLHMIGJTEW-UHFFFAOYSA-N pyraflufen-ethyl Chemical compound C1=C(Cl)C(OCC(=O)OCC)=CC(C=2C(=C(OC(F)F)N(C)N=2)Cl)=C1F APTZNLHMIGJTEW-UHFFFAOYSA-N 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Formation Of Insulating Films (AREA)
Abstract
The invention discloses a kind of method preventing substrate impurity external diffusion, be before epitaxial growth, first form oxide-film in side of substrate, carry out epitaxial growth the most again.Specifically comprising: the 1st step, the substrate that the back side has back of the body envelope oxide layer carries out oxide growth；2nd step, performs etching substrate face oxide-film.The present invention passes through to be formed the parcel of oxide-film in side of substrate, the problem that the impurity being avoided that in substrate when epitaxial growth causes silicon chip edge tube core electrical characteristics instability from sidewall to external diffusion.
Description
Technical field
The present invention relates to field of manufacturing semiconductor devices, particularly relate to a kind of TVS device manufacturing process prevents substrate
The method of impurity external diffusion.
Background technology
The glitch of voltage and electric current is to cause the main cause of electronic circuit and device damage, often brings nothing
The loss that method is estimated.These interference typically from the start-stop operation of power equipment, the instability of AC network, thunderbolt interference and
Static discharge etc..The appearance of a kind of dynamical circuit brake TVS makes glitch obtain effective suppression.TVS
(Transient Voltage Suppressor) or title transient voltage suppressor are to develop on stabilivolt Process ba-sis
A kind of new product got up, TVS and Zener stabilivolt can be used for voltage stabilizing, but Zener breakdown electric current is less, steady more than 10V
Pressure only 1mA, TVS is more many than Zener diode breakdown current comparatively speaking.Its circuit symbol and common voltage stabilizing two pole
Managing identical, profile is also as good as with general-purpose diode, and when the high energy impact events of moment is stood at TVS pipe two ends, it can be with high
Speed (up to 1x10-12 second) makes its impedance suddenly reduce, and absorbs a big electric current, by the voltage clamp of its go-and-retum simultaneously
One predetermined numerically, so that it is guaranteed that component below damages from the high-octane impact of transient state.The most extensively
For mobile phone, LCD module, and some more accurate handheld devices.The product particularly exporting Europe typically will add, as
One of Main Means of electrostatic defending.
In field of semiconductor manufacture, the manufacturing process of TVS, it will usually in one layer of concentration of heavily doped Grown very
Light epitaxial layer.In epitaxial layer growth process, silicon chip edge has substrate impurity and divides to external diffusion, the concentration affecting epitaxial layer
Cloth, as it is shown in figure 1, ultimately result in the TVS device formed on silicon chip, the tube core electrical characteristics being positioned at crystal round fringes are unstable.
Summary of the invention
The technical problem to be solved is to provide a kind of method preventing substrate impurity external diffusion.
For solving the problems referred to above, the method preventing substrate impurity external diffusion of the present invention, is before epitaxial growth,
First form oxide-film in side of substrate, carry out epitaxial growth the most again.
Further, described side of substrate oxide-film, the impurity being avoided that in substrate when epitaxial growth is outside from sidewall
Diffusion.
The method preventing substrate impurity external diffusion of the present invention, comprises the steps of:
1st step, the substrate that the back side has back of the body envelope oxide layer carries out oxide growth；
2nd step, performs etching substrate face oxide-film.
Further, the substrate of described 1st step is heavily doped substrate, oxide-film in the front of substrate and lateral growth,
Together with sealing oxide layer with the back of the body at the back side, substrate is wrapped up.
Further, described 2nd step, the oxide-film of substrate face is etched away, lateral oxidation film retains.
Further, described 2nd step, etching uses dry etching, or dry etching adds wet etching；When using dry method
When etching adds wet etching, the amount of wet etching is necessarily less than the thickness of oxide growth.
The method preventing substrate impurity external diffusion of the present invention, first generated oxide-film to substrate before epitaxial growth
Side is protected, and when epitaxial growth, lateral oxidation film can prevent the impurity in substrate to external diffusion, thus causes silicon chip limit
The problem that edge tube core electrical characteristics are unstable.
Accompanying drawing explanation
When Fig. 1 is external pressure growth, substrate impurity is to the schematic diagram of external diffusion.
Fig. 2 is the substrate schematic diagram of back side band back of the body envelope oxide layer.
Fig. 3 is the schematic diagram that silicon chip forms that silicon chip is wrapped up by oxide-film.
Fig. 4 is the schematic diagram after front side of silicon wafer oxide-film etching.
Fig. 5 is the inventive method flow chart.
Description of reference numerals
1 is substrate, and 2 is oxide-film.
Detailed description of the invention
The method preventing substrate impurity external diffusion of the present invention, is before epitaxial growth, first in side of substrate shape
Become oxide-film, carry out epitaxial growth the most again.Described side of substrate oxide-film, the impurity being avoided that in substrate when epitaxial growth
From sidewall to external diffusion.
Specifically comprise the steps:
1st step, the heavily doped substrate that the back side has back of the body envelope oxide layer carries out oxide growth；Oxide-film is at substrate
Front and lateral growth, wrap up substrate together with the back of the body envelope oxide layer at the back side.As shown in Figures 2 and 3.
2nd step, performs etching substrate face oxide-film.Etching uses dry etching, or dry etching adds wet method and carves
Erosion；When using dry etching to add wet etching, the amount of wet etching is necessarily less than the thickness of oxide growth.Etching is by substrate
The oxide-film in front etches away, and lateral oxidation film retains.
The method preventing substrate impurity external diffusion of the present invention, first generated oxide-film to substrate before epitaxial growth
Side is protected, and when epitaxial growth, lateral oxidation film can prevent the impurity in substrate to external diffusion, thus causes silicon chip limit
The problem that edge tube core electrical characteristics are unstable.
These are only the preferred embodiments of the present invention, be not intended to limit the present invention.Those skilled in the art is come
Saying, the present invention can have various modifications and variations.All within the spirit and principles in the present invention, any amendment of being made, equivalent
Replacement, improvement etc., should be included within the scope of the present invention.
Claims (6)
1. the method preventing substrate impurity external diffusion, it is characterised in that before epitaxial growth, is first formed in side of substrate
Oxide-film, carries out epitaxial growth the most again.
The method preventing substrate impurity external diffusion the most as claimed in claim 1, it is characterised in that: described side of substrate aoxidizes
Film, the impurity being avoided that in substrate when epitaxial growth from sidewall to external diffusion.
The method preventing substrate impurity external diffusion the most as claimed in claim 1, it is characterised in that: comprise the steps of:
1st step, the substrate that the back side has back of the body envelope oxide layer carries out oxide growth；
2nd step, performs etching substrate face oxide-film.
The method preventing substrate impurity external diffusion the most as claimed in claim 3, it is characterised in that: the substrate of described 1st step is
Heavily doped substrate, substrate, in the front of substrate and lateral growth, is wrapped up together with the back of the body envelope oxide layer at the back side by oxide-film.
The method preventing substrate impurity external diffusion the most as claimed in claim 3, it is characterised in that: described 2nd step, by substrate just
The oxide-film in face etches away, and lateral oxidation film retains.
The method preventing substrate impurity external diffusion the most as claimed in claim 3, it is characterised in that: described 2nd step, etching uses
Dry etching, or dry etching adds wet etching；When using dry etching to add wet etching, the amount of wet etching must be little
Thickness in oxide growth.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610874737.5A CN106252225A (en) | 2016-09-30 | 2016-09-30 | The method preventing substrate impurity external diffusion |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610874737.5A CN106252225A (en) | 2016-09-30 | 2016-09-30 | The method preventing substrate impurity external diffusion |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106252225A true CN106252225A (en) | 2016-12-21 |
Family
ID=57612420
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610874737.5A Pending CN106252225A (en) | 2016-09-30 | 2016-09-30 | The method preventing substrate impurity external diffusion |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106252225A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4662956A (en) * | 1985-04-01 | 1987-05-05 | Motorola, Inc. | Method for prevention of autodoping of epitaxial layers |
| US5834363A (en) * | 1996-03-28 | 1998-11-10 | Shin-Etsu Handotai Co., Ltd. | Method of manufacturing semiconductor wafer, semiconductor wafer manufactured by the same, semiconductor epitaxial wafer, and method of manufacturing the semiconductor epitaxial wafer |
| US6315826B1 (en) * | 1997-02-12 | 2001-11-13 | Nec Corporation | Semiconductor substrate and method of manufacturing the same |
-
2016
- 2016-09-30 CN CN201610874737.5A patent/CN106252225A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4662956A (en) * | 1985-04-01 | 1987-05-05 | Motorola, Inc. | Method for prevention of autodoping of epitaxial layers |
| US5834363A (en) * | 1996-03-28 | 1998-11-10 | Shin-Etsu Handotai Co., Ltd. | Method of manufacturing semiconductor wafer, semiconductor wafer manufactured by the same, semiconductor epitaxial wafer, and method of manufacturing the semiconductor epitaxial wafer |
| US6315826B1 (en) * | 1997-02-12 | 2001-11-13 | Nec Corporation | Semiconductor substrate and method of manufacturing the same |
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|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20161221 |