CN106250322A - A kind of method and apparatus writing data - Google Patents

A kind of method and apparatus writing data Download PDF

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Publication number
CN106250322A
CN106250322A CN201610666702.2A CN201610666702A CN106250322A CN 106250322 A CN106250322 A CN 106250322A CN 201610666702 A CN201610666702 A CN 201610666702A CN 106250322 A CN106250322 A CN 106250322A
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data
written
write request
lba
time attribute
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CN106250322B (en
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李劲松
谭春华
毛宏华
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to PCT/CN2017/079343 priority patent/WO2018028218A1/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)

Abstract

A kind of method and apparatus writing data of offer is provided, relates to technical field of data processing, in order at least to solve the problem that to storage array in the data of write inconsistent actual with main frame of the data of storage in non-volatile media.Storage array includes controller and non-volatile media；Method includes: the first write request including the first data to be written and LBA that controller Receiving Host sends, and after receiving the first write request, Receiving Host sends the second write request including the second data to be written and this LBA；It is that the first write request adds very first time attribute tags, it is that the second write request adds the second time attribute label, very first time attribute tags is for indicating controller to receive the time of the first write request, and the second time attribute label receives the time of the second write request for indicating controller；According to very first time attribute tags and the second time attribute label, the first data to be written and the second data to be written are write in the memory space corresponding to this LBA according to sequencing.

Description

A kind of method and apparatus writing data
Technical field
The present invention relates to technical field of data processing, particularly relate to a kind of method and apparatus writing data.
Background technology
Small computer system interface (small computer system is typically used between main frame and storage array Interface, SCSI) agreement communicates.Storage array includes controller and at least one non-volatile media, and controller includes Processor, caching and cache controller.
At present, the method writing data based on SCSI protocol is as follows: main frame sends write request to processor；Processor receives After this write request, send this write request to cache controller；Then the data that this write request is included by cache controller Write caching.Processor inquires can be to host response write response after these data store caching.Follow-up, cache controller meeting By these data write non-volatile media of storage in caching.Further, if main frame is not received by place in preset time period The write response that reason device is replied, then send Abort order to processor, with notifier processes device: this write request abandoned by main frame；Processor After receiving Abort order, inquire about these data and be the most written into caching；If these data have been written into caching, then processor To host response Abort order success, after main frame receives Abort order success, send overwrite request to processor, its In, the logical block addresses (logical block address, LBA) that this overwrite request includes includes with this write request LBA identical；If these data are not written to caching, then processor hangs Abort order, it may be assumed that processor wouldn't respond Abort Order.
In said method, if processor inquires these data and is not written to caching, then processor in preset time period Will not be to host response Abort order success, this can cause processor to reply Abort order success time-out；Due to SCSI protocol Middle regulation: main frame, after receiving Abort order success, could send overwrite request, therefore, said method meeting to processor Cause main frame before receiving Abort order success, it is impossible to send overwrite request to processor, say, that, it is impossible to this Write data in memory space corresponding to LBA, thus affect the seriality of host service.
In order to solve above-mentioned technical problem, a kind of implementation is as follows: processor is receiving the write request that main frame sends After, immediately to host response Abort order success.But, so there are the following problems in meeting: owing to cache processor is according to connecing The time order and function order receiving data to be written writes data in non-volatile media, therefore, if the overwrite request that processor receives The data included first are written into caching than the data that write request includes, then the data ratio that overwrite request can be caused to include is write The data that request includes first are written into non-volatile media, and in the case of being somebody's turn to do, the data that overwrite request includes can be by write request Including data cover, thus cause in non-volatile media data to storage array in the data of write actual with main frame of storage Inconsistent.
Summary of the invention
Embodiments of the invention provide a kind of method and apparatus writing data, permanent in order at least solve in storage array Property medium in the actual problem that the data of write are inconsistent in storage array of data and main frame of storage.
For reaching above-mentioned purpose, embodiments of the invention adopt the following technical scheme that
On the one hand, it is provided that a kind of method writing data, including: the first write request that controller Receiving Host sends, wherein, First write request includes the first data to be written and logical block addresses LBA of the first data to be written；Receive the first write request it After, the second write request that controller Receiving Host sends, wherein, the second write request includes the second data to be written and the second number to be written According to LBA, the LBA of the second data to be written and the LBA of the first data to be written identical；Then, controller is that the first write request is added Very first time attribute tags, and be that the second write request adds the second time attribute label, wherein, very first time attribute tags is used for Instruction controller receives the time of the first write request, and the second time attribute label is for indicating controller to receive the second write request Time；Follow-up, the first data to be written and second, according to very first time attribute tags and the second time attribute label, are treated by controller Write data according in the memory space corresponding to the LBA of the first data to be written in sequencing write non-volatile media.Wherein, Communication protocol between main frame and storage array can include but not limited to SCSI protocol.So, controller can be according to first Time attribute label and the second time attribute tag recognition go out to receive the first data to be written and the time order and function of the second data to be written Sequentially (that is: main frame reality writes the sequencing of data in storage array), therefore, controller can be suitable according to this time order and function First data to be written and the second data to be written are write corresponding to the LBA of the data to be written of first in non-volatile media by sequence successively In memory space, so that the data of storage to storage array in the data one of write actual with main frame in non-volatile media Cause.
Concrete, controller is that the first write request adds very first time attribute tags, and is that the second write request adds second Time attribute label, may include that controller, after receiving the first write request, is that the first write request adds very first time genus Property label；After receiving the second write request, it is that the second write request adds the second time attribute label.
During it should be noted that implement, controller can be at least in the first write request and the second write request Individual write request adds time attribute label, i.e. may recognize that controller receives the first write request and the order of the second write request；Also That is, the time attribute label of this at least one write request is used for representing that controller receives second after first receiving the first write request Write request.
A kind of possible implementation, controller is according to very first time attribute tags and the second time attribute label, by One data to be written and the second data to be written are according to corresponding to the LBA of the first data to be written in sequencing write non-volatile media Memory space in, may alternatively be: cache controller, according to very first time attribute tags and the second time attribute label, is deleted Except the first data to be written, and by depositing corresponding to the LBA of the first data to be written in the second data to be written write non-volatile media In storage space.
In a kind of possible implementation, the method also includes: the Abort order that controller Receiving Host sends, wherein, Abort order is used for notifying storage array: the first write request abandoned by main frame；Then, controller becomes to host response Abort order Merit；Then, controller, after host response Abort order success, receives the second write request.Concrete, if main frame is in advance If being not received by the write response about the first write request that processor is replied within the time period, then send Abort to controller Order, controller, can be immediately to host response Abort order success after receiving the Abort order that main frame sends (that is: controller is after receiving the Abort order that main frame sends, and determines that the first data to be written are write the most need not In the case of entering caching, to host response Abort order success).This possible implementation provides a kind of main frame and storage The method writing data in the scene communicated by SCSI protocol between array.
A kind of possible implementation, the method may include that very first time attribute tags includes the bag that controller receives Include the number of times of the write request of the LBA of the first data to be written；Second time attribute label includes that what controller received includes that second treats Write the number of times of the write request of the LBA of data.This optional implementation provides the side of implementing of a kind of time attribute label Formula, is certainly not limited to this.
A kind of possible implementation, controller includes processor and caching；In the case of Gai, controller Receiving Host sends The first write request, may include that the first write request that processor Receiving Host sends.The sent at processor Receiving Host After one write request, the method can also include: processor determines that the LBA in caching does not comprise and the first number to be written in gathering According to LBA time, the LBA of the first data to be written is write LBA set；Wherein, LBA set includes meeting pre-conditioned write request The LBA included；Meeting pre-conditioned write request is that finger processor receives and included data to be written do not write slow The write request deposited.In the case of Gai, controller be that the second write request adds the second time attribute label, may include that processor exists When inquiring the LBA comprising the second data to be written in LBA set, it is that the second write request adds the second time attribute label.This can Can implementation provide and a kind of judge that whether the second write request is the mode of overwrite request, and determining that the second write request is It is that the second write request adds the second time attribute label on the basis of overwrite request.
A kind of possible implementation, controller can also include cache controller；Controller is according to very first time attribute First data to be written and the second data to be written are write non-volatile media according to sequencing by label and the second time attribute label In the first data to be written the memory space corresponding to LBA in, may include that cache controller is according to very first time attribute mark Sign and the second time attribute label, by the first data to be written in the first data to be written and the second data to be written write caching In memory space corresponding to LBA；Then, the first data to be written and the second data to be written are write forever by cache controller successively The memory space corresponding to LBA of the first data to be written in property medium.Concrete, cache controller first treating in the buffer Write and corresponding for LBA a memory space of data stores the first data to be written and very first time attribute tags, and in the buffer Another corresponding for this LBA memory space in store the second data to be written and the second time attribute label.
A kind of possible implementation, in the buffer, LBA correspondence M the memory space of the first data to be written, M >=2, M is Integer；M memory space alignment processing device respectively receives the sequencing of write request.In the case of Gai, cache controller be according to First data to be written and the second data to be written are write first in caching by one time attribute tags and the second time attribute label In memory space corresponding to the LBA of data to be written, may include that cache controller is according to very first time attribute tags and second Time attribute label, stores the first data to be written and the second data to be written in the different memory spaces in M memory space.Should In optional implementation, the time order and function order of mechanism and processor reception data to be written that cache controller writes data has Closing, the time order and function order of the data to be written received with cache controller is unrelated.
A kind of possible implementation, in the buffer, LBA correspondence M the memory space of the first data to be written, M >=2, M is Integer.In the case of Gai, cache controller be according to very first time attribute tags and the second time attribute label, by the first data to be written With in the memory space corresponding to the LBA of the first data to be written in the second data to be written write caching, may include that caching control Device processed stores in very first time attribute tags and the second time attribute label, and the different memory spaces in M memory space Store the first data to be written and the second data to be written.In this optional implementation, cache controller writes mechanism and the place of data The time order and function order that reason device receives data to be written is unrelated, with the time order and function order of the data to be written that cache controller receives Relevant.
On the other hand, it is provided that a kind of storage array, including controller and at least one non-volatile media；Controller is used for: The first write request that Receiving Host sends, the first write request includes the logical blocks ground of the first data to be written and the first data to be written Location LBA；After receiving the first write request, the second write request that Receiving Host sends, the second write request includes the second number to be written Identical according to the LBA with the second data to be written, the LBA of the second data to be written and the LBA of the first data to be written；It is that the first write request adds Add very first time attribute tags, and be that the second write request adds the second time attribute label；Very first time attribute tags is used for referring to Show that controller receives the time of the first write request, the second time attribute label for indicate controller receive the second write request time Between；According to very first time attribute tags and the second time attribute label, by the first data to be written and the second data to be written according to elder generation After in the memory space corresponding to LBA of the first data to be written that is sequentially written in non-volatile media.
A kind of possible implementation, controller can be also used for: the Abort order that Receiving Host sends, wherein, Abort order is used for notifying that the first write request abandoned by storage array main frame；To host response Abort order success.In the case of Gai, Controller specifically may be used for: after host response Abort order success, receives the second write request.
A kind of possible implementation, what very first time attribute tags included that controller receives includes the first data to be written The number of times of the write request of LBA；Second time attribute label includes that the writing of the LBA including the second data to be written that controller receives please The number of times asked.
A kind of possible implementation, controller includes processor and caching；Processor is used for: Receiving Host send the One write request.Processor can be also used for: determines when the LBA in caching does not comprise the LBA with the first data to be written in gathering, The LBA of the first data to be written is write LBA set；Wherein, LBA set includes meeting what pre-conditioned write request included LBA；Wherein, meeting pre-conditioned write request is that finger processor receives and included data to be written do not write caching Write request.Processor can be also used for: inquire LBA set in comprise the second data to be written LBA time, be second write please Seek interpolation the second time attribute label.
A kind of possible implementation, controller also includes cache controller；Cache controller is used for: according to the very first time First data to be written and the second data to be written are write the first number to be written in caching by attribute tags and the second time attribute label According to LBA corresponding to memory space in；First data to be written and the second data to be written are write in non-volatile media successively The memory space corresponding to LBA of the first data to be written.
A kind of possible implementation, in the buffer, LBA correspondence M the memory space of the first data to be written, M >=2, M is Integer；M memory space alignment processing device respectively receives the sequencing of write request.In the case of Gai, buffer control implement body can For: according to very first time attribute tags and the second time attribute label, in the different memory spaces in M memory space Store the first data to be written and the second data to be written.
A kind of possible implementation, in the buffer, LBA correspondence M the memory space of the first data to be written, M >=2, M is Integer.In the case of Gai, buffer control implement body may be used for: storage very first time attribute tags and the second time attribute label, And the different memory spaces in M memory space store the first data to be written and the second data to be written.
Another aspect, embodiments provides a kind of storage array, and it is real that this storage array can realize said method Executing the function performed by the storage array in example, described function can be realized by hardware, it is also possible to performed corresponding by hardware Software realize.Described hardware or software include the corresponding module of one or more above-mentioned functions.
In a kind of possible design, the structure of this storage array includes that controller is connected at least with this controller One non-volatile media and transceiver, this processor is configured to support that this storage array performs corresponding merit in said method Energy.This transceiver is used for supporting this storage array and other network elements, such as with main frame, between communication.Storage array also may be used To include memorizer, this memorizer is for coupling with processor, and it preserves the necessary programmed instruction of this device and data；Wherein, This memorizer can be non-volatile media, it is also possible to be the arbitrary storage device in addition to this non-volatile media.
Another aspect, embodiments provides a kind of communication system, and this system includes main frame, and above-mentioned aspect institute Any one storage array stated.
Another further aspect, embodiments provides a kind of computer-readable storage medium, is used for saving as above-mentioned storage array Computer software instructions used, this computer software instructions could be included for performing the program designed by above-mentioned aspect.
It is to be appreciated that any one storage array of above-mentioned offer or computer-readable storage medium are used to perform to be carried above The method writing data of confession, therefore, its beneficial effect that can reach refers to the presented above side writing data accordingly Beneficial effect in method, here is omitted.
Accompanying drawing explanation
A kind of system architecture schematic diagram that the technical scheme that Fig. 1 provides by the embodiment of the present invention is suitable for；
The mutual schematic diagram of a kind of method writing data that Fig. 2 provides for the embodiment of the present invention；
A kind of process schematic writing data that Fig. 3 (a) provides for the embodiment of the present invention；
Fig. 3 (b) writes the process schematic of data for the another kind that the embodiment of the present invention provides；
Fig. 4 (a) writes the process schematic of data for the another kind that the embodiment of the present invention provides；
Fig. 4 (b) writes the process schematic of data for the another kind that the embodiment of the present invention provides；
Fig. 4 (c) writes the process schematic of data for the another kind that the embodiment of the present invention provides；
Fig. 4 (d) writes the process schematic of data for the another kind that the embodiment of the present invention provides；
Fig. 5 writes the mutual schematic diagram of the method for data for the another kind that the embodiment of the present invention provides；
The structural representation of a kind of storage array that Fig. 6 provides for the embodiment of the present invention；
The structural representation of the another kind of storage array that Fig. 7 provides for the embodiment of the present invention.
Detailed description of the invention
The technical scheme that the embodiment of the present invention provides is applied in system architecture as shown in Figure 1, the system bag shown in Fig. 1 Including main frame and storage array, wherein, main frame is mainly used in controlling computing, and storage array is mainly used in storage and manages and main frame phase The data closed.Storage array can be the hardware entities with complete operating system, it is also possible to for software, the present embodiment is with storage Array is to illustrate as a example by the hardware entities with complete operating system.Storage array can include controller and at least one Non-volatile media.Controller includes that (central processing unit, CPU referred to herein as " process central processing unit Device "), caching and cache controller.Wherein, processor, is the control centre of storage array.Caching be between central processing unit and High-speed memory between non-volatile media, is mainly used in promoting the readwrite performance of storage.Cache controller is in caching Data be managed, example, may be used for writing data in caching, and will caching write permanent at the data that store In medium.Non-volatile media is also known as non-volatile memory medium, and when its maximum feature is powered off, content remains to keep.
Communication protocol between main frame and storage array can be SCSI protocol.Wherein, SCSI protocol is a kind of based on C/S The communication protocol of (client/server, client/server) framework；Wherein, client computer is also referred to as trigger (initiator), for sending request instruction to scsi target device (target).In the main frame communication with storage array, one As, main frame serves as the role of trigger, and the controller of storage array serves as the role of scsi target device.
Embodiments providing a kind of method and apparatus writing data, its ultimate principle is: the control of storage array First write request of the LBA including the first data to be written and the first data to be written that device Receiving Host sends, and receiving the After one write request, receive second write request of the LBA including the second data to be written and the second data to be written；It it is the first write request Add very first time attribute tags, and be that the second write request adds the second time attribute label, wherein, the first data to be written The LBA of LBA and the second data to be written is identical, very first time attribute tags for indicate controller receive the first write request time Between, the second time attribute label receives the time of the second write request for indicating controller.So, controller can be according to first Time attribute label and the second time attribute tag recognition go out to receive the first data to be written and the time order and function of the second data to be written Sequentially (that is: main frame reality writes the sequencing of data in storage array), therefore, controller can be suitable according to this time order and function First data to be written and the second data to be written are write corresponding to the LBA of the data to be written of first in non-volatile media by sequence successively In memory space, so that the data of storage to storage array in the data one of write actual with main frame in non-volatile media Cause.
The terms "and/or", a kind of incidence relation describing affiliated partner, can there are three kinds of passes in expression System, such as, A and/or B, can represent: individualism A, there is A and B, individualism B these three situation simultaneously.It addition, herein Middle character "/", typicallys represent the forward-backward correlation relation to liking a kind of "or"." first " and " second " herein etc. be in order to More clearly distinguish different objects, do not do any other and limit." multiple " herein refer to two or more.
Below in conjunction with the Figure of description of the embodiment of the present invention, the technical scheme providing the embodiment of the present invention is said Bright.Obviously, described is a part of embodiment of the present invention rather than whole embodiments.
As in figure 2 it is shown, be the mutual schematic diagram of a kind of method writing data that the embodiment of the present invention provides, it is applied to main frame Sending in the scene of write request to controller, the method includes:
S101: main frame sends the first write request to controller.Wherein, the first write request includes the first data to be written and first The LBA of data to be written.
S102: main frame sends the second write request to controller.Wherein, the second write request includes the second data to be written and second The LBA of data to be written, the LBA of the first data to be written and the LBA of the second data to be written are identical.
Assume that between main frame and storage array, the transmission times of the overwrite request for same LBA of negotiation is N, wherein, N >=1, N are integers.So: if N=1, then the first write request is the LBA including the first data to be written that main frame sends to controller First time write request, the second write request is the overwrite request of the LBA including the second data to be written that main frame sends to controller. If N >=2, then the first write request can be that write for the first time of the LBA including the first data to be written that main frame sends to controller please Asking, in the case of being somebody's turn to do, the second write request can be arbitrary the weight of the LBA including the second data to be written that main frame sends to controller Write request；Or, the first write request can be the n-th weight of the LBA including the first data to be written that main frame sends to controller Write request, wherein, n can be less than any value of N；In the case of Gai, the second write request can be that main frame sends to controller Including the n-th+i the overwrite request of the LBA of the second data to be written, wherein, n+i≤N, i are integers.If being not added with explanation, hereafter In all illustrate as a example by N=1.
Non-volatile media can include one or more memory space, the corresponding physical address of each memory space, often The corresponding LBA of individual physical address.The LBA (i.e. the LBA of the second data to be written in S102) of the first data to be written in S101 Can be the arbitrary LBA in non-volatile media, the LBA that i.e. the arbitrary memory space in non-volatile media is corresponding.
First data to be written are identical with the second data possibility to be written, it is also possible to different.This is because: main frame can be according to need Revise the data in the memory space corresponding to arbitrary LBA in write non-volatile media.Assume to send out main frame to controller The moment sending the first write request was labeled as the first moment, and the moment that main frame sends the second write request to controller is labeled as second Moment；So, if from the first moment to the time period in the second moment in, the first data to be written in main frame unmodified write S101 The memory space corresponding to LBA in data, then the first data to be written are identical with the second data to be written；If from the first moment to In the time period in the second moment, in the memory space corresponding to LBA of first data to be written in host modifications write S101 Data, then the first data to be written are different from the second data to be written.
The first write request that S103: controller Receiving Host sends and the second write request, and be that the first write request adds the One time attribute tags, is that the second write request adds the second time attribute label.
Concrete, controller, after receiving the first write request, is that the first write request adds very first time attribute tags； After receiving the second write request, it is that the second write request adds the second time attribute label.
The present embodiment is receive by controller to say as a example by 2 write requests including same LBA that main frame sends Bright, actual when realizing, based on the example in S102, if N >=2, then controller be likely to be received that main frame sends 3 or 3 More than include the write request of same LBA, should in the case of, controller can after receiving each write request including this LBA, Time attribute label is added for this write request.
Very first time attribute tags can be any one represent controller receive the first write request time character or Character string, for example, it may be the number of times of the write request of the LBA including the first data to be written of controller reception.Second time belonged to Property label can be that any one represents that controller receives the character of time or the character string of the second write request, for example, it may be The number of times of the write request of the LBA including the second data to be written that controller receives.
S104: controller is according to very first time attribute tags and the second time attribute label, by the first data to be written and Two data to be written are according in the memory space corresponding to the LBA of the first data to be written in sequencing write non-volatile media.
The method writing data that the embodiment of the present invention provides, what controller elder generation Receiving Host sent includes the first data to be written With first write request of the LBA of the first data to be written, and be first write request add very first time attribute tags, then, control Device receives second write request of the LBA including the second data to be written and the second data to be written, and is that the second write request adds second Time attribute label, so, controller can go out receive according to very first time attribute tags and the second time attribute tag recognition (that is: main frame reality writes the priority of data in storage array to the time order and function order of the first data to be written and the second data to be written Sequentially), therefore, the first data to be written and the second data to be written can be write successively forever by controller according to this time order and function order For a long time in the memory space corresponding to LBA of the first data to be written in property medium, so that the number of storage in non-volatile media According to storage array in the data consistent of write actual with main frame.
It should be noted that the embodiment of the present invention be all with controller be first write request add very first time attribute mark Signing, be to illustrate as a example by the second write request adds the second time attribute label, actual when realizing, controller can be first Write request adds time attribute label with at least one write request in the second write request, and in the case of being somebody's turn to do, above-mentioned S103 can be replaced It is changed to following steps: the first write request that controller Receiving Host sends and the second write request, and is the first write request and second At least one write request in write request adds time attribute label, and wherein, the time attribute label of at least one write request is used In representing that controller first receives the first write request and receives the second write request again.
Based on the example in S101 and S102, if N=1, then during processor is the first write request and the second write request extremely A few write request adds time attribute label, can distinguish processor and receive the first write request and the time of the second write request Sequencing.When implementing, it is first time write request that main frame and disk array can consult at least one write request in advance (the i.e. first write request), overwrite request (the i.e. second write request), or write request and overwrite request for the first time.
Based on the example in S101 and S102, if N >=2, in theory, in order to ensure in non-volatile media the data of storage with The actual data consistent of write in disk array of main frame, it is only necessary to receive processor for the last time carries this LBA's Overwrite request adds time attribute label, can ensure that what cache controller identified that processor receives for the last time carries this The overwrite request of LBA, thereby may be ensured that writing processor in the most backward non-volatile media of cache controller receives for the last time To the overwrite request carrying this LBA；It practice, owing to processor does not knows whether this overwrite request that main frame sends is A rear overwrite request (unless this overwrite request is n-th overwrite request) is therefore, usually, in order to realize conveniently, permissible Time attribute label is all added for each overwrite request carrying this LBA；Certainly, when implementing, it is also possible to for carrying LBA's Write request and each overwrite request carrying this LBA all add time attribute label for the first time.
Optionally, controller includes processor and caching, and wherein, caching can include one or more memory space, often The corresponding physical address of individual memory space, one or more physical address can a corresponding LBA.In the case of Gai, at S101 Afterwards, the method can also include:
S101a: main frame sends Abort order to processor, to notify storage array: the first write request abandoned by main frame.
SCSI protocol specifies: processor receives write request that main frame sends and inquires cache controller and this write After the data to be written write caching that request includes, can be to host response write response；If main frame does not has within preset time period Have and receive the write response that processor is replied, then send Abort order to processor.Wherein, main frame is within preset time period Be not received by processor reply the reason about the write response of the first write request be probably following any one: processor does not also have Have the first data to be written write caching；Processor is writing the data into caching；First data to be written are write by processor Enter caching, and to host response about the write response of the first write request.
Based on this, if S101a may include that main frame be not received by within preset time period processor reply about The write response of the first write request, then send Abort order to processor.
This Abort order that S101b: processor Receiving Host sends, and to host response Abort order success.
In embodiments of the present invention, processor, can be immediately to main frame after receiving the Abort order that main frame sends Reply Abort order success；That is: processor is after receiving the Abort order that main frame sends, and determines that first treats need not Write in the case of data are written into caching the most, to host response Abort order success.
After S102a: main frame receives this Abort order success that processor sends, send overwrite request to processor； Wherein, this overwrite request can be the second write request.
When implementing, the second write request can also is that main frame includes for arbitrary time of transmission after sending the first write request The overwrite request of the LBA of the second data to be written.Example, after main frame receives this Abort order success that processor sends, Overwrite request is sent to processor；If main frame be not received by within preset time period processor reply about overwrite request Response, then can send Abort order to processor again, after main frame receives this Abort order successfully that processor sends, Again send overwrite request to processor, this overwrite request is the second write request.
In above-described embodiment, it is all to enter as a example by the overwrite request that the second write request is the LBA including the second data to be written Row explanation, actual when realizing, processor can determine whether the second write request is overwrite request as follows: processor Receiving the first write request that main frame sends, and inquiring in the LBA set in caching not storage the first write request and include The first data to be written LBA in the case of, the LBA of these the first data to be written is write caching, wherein, LBA set includes full The LBA that sufficient pre-conditioned write request includes, meeting pre-conditioned write request is that finger processor receives and included Data to be written do not write the write request of caching；So, after processor receives the second write request, can be somebody's turn to do by inquiry Whether caching stores the LBA of the second data to be written that the second write request includes, and storage has second to write in determining caching In the case of the LBA of the second data to be written that request includes, determining that the second write request is overwrite request, wherein, first is to be written The LBA of the LBA of data and the second data to be written is identical.
If time attribute label includes the number of times of the write request including this LBA that processor receives, then optional based on this Implementation, S103 can be realized by the following two kinds mode:
Optional implementation 1: processor is receiving the second write request and inquiring storage in caching and have second write please After seeking the LBA of second included data to be written, it is that the second write request adds the second time attribute label.
Example, it is assumed that processor in chronological sequence order continuously receives successively and includes the write request 1 of LBA1, includes The write request 2 of LBA2, include the write request 3 of LBA2 and include the write request 4 of LBA1；So, distribute if processor is write request 1 Time attribute label be " 1 ", to represent that write request 1 is the first time write request including LBA1 that processor receives, be then The time attribute label of write request 4 distribution is " 2 "；If the time attribute label that processor is write request 2 distribution is " 1 ", it is then The time attribute label of write request 3 distribution is " 2 ", as shown in table 1.
Table 1
Write request LBA Time attribute label
Write request 1 LBA1 1
Write request 2 LBA2 1
Write request 3 LBA2 2
Write request 4 LBA1 2
Optional implementation 2: whether processor, when receiving the second write request, has not stored second in query caching The LBA (i.e. need not determine whether the second write request is overwrite request) of the second data to be written that write request includes, is directly Two write requests add the second time attribute label.
Example, it is assumed that processor in chronological sequence order continuously receives successively and includes the write request 1 of LBA1, includes The write request 2 of LBA2, include the write request 3 of LBA2 and include the write request 4 of LBA1；So, distribute if processor is write request 1 Time attribute label be " 1 ", to represent that write request 1 is the first time write request that processor receives, be then write request 2,3,4 The time attribute label of distribution is respectively " 2 ", " 3 ", " 4 ", as shown in table 2.
Table 2
Write request LBA Time attribute label
Write request 1 LBA1 1
Write request 2 LBA2 2
Write request 3 LBA2 3
Write request 4 LBA1 4
It should be noted that due in above-mentioned optional implementation 1 maximum of time attribute label be according to rewriting Maximum number of rewrites in mechanism determines, such as, if the maximum number of rewrites in rewriting mechanism is N, then time attribute label Maximum be N+1；And the maximum of the time attribute label in above-mentioned optional implementation 2 is to processor according to main frame The total degree of write request sent determines, such as, if the total degree of write request that main frame sends to processor is W, then time The maximum of attribute tags is W.Usually, W is much larger than N, so, each time attribute in above-mentioned optional implementation 2 Memory space shared by label is empty much larger than the storage shared by each time attribute label in above-mentioned optional implementation 1 Between, therefore, the less scene of number of times of the write request that above-mentioned optional implementation 2 sends to processor be applicable to main frame.
Optionally, controller can also include cache controller, and in the case of being somebody's turn to do, S104 may include that
S104a: cache controller is according to very first time attribute tags and the second time attribute label, by the first data to be written In memory space corresponding to the LBA of the first data to be written in caching with the second data to be written write, then by the first number to be written According to the memory space write successively with the second data to be written corresponding to the LBA of the data to be written of first in non-volatile media.
Concrete, corresponding for LBA a memory space of cache controller the first data to be written in the buffer stores Storage the in first data to be written and very first time attribute tags, and another corresponding for this LBA memory space in the buffer Two data to be written and the second time attribute label.
Optionally, actual when realizing, above-mentioned S104a can be replaced by S104':
S104': cache controller, according to very first time attribute tags and the second time attribute label, deletes the first number to be written According to, and by the memory space corresponding to the LBA of the first data to be written in the second data to be written write non-volatile media.
It should be noted that be that a write request in the first write request and the second write request adds the time based on processor Attribute tags.Example, if processor is the first write request adds very first time attribute tags, then cache controller is in the buffer The first data to be written corresponding for LBA a memory space in store the first data to be written and very first time attribute tags, and Another corresponding for this LBA memory space in the buffer stores the second data to be written.Add if processor is the second write request Add the second time attribute label, then corresponding for LBA a memory space of cache controller the first data to be written in the buffer In middle storage first data to be written, and another corresponding for this LBA memory space in the buffer store the second data to be written and Second time attribute label.
Optionally, in the buffer, corresponding M the memory space of LBA in S101 with S102, M >=2, M is integer.Further Optionally, can determine the value of M according to maximum number of rewrites, example, if maximum number of rewrites is N, the most each LBA is permissible Corresponding N+1 memory space, it may be assumed that in the buffer, the number of the memory space that each LBA is corresponding at least can store include same Data included by the first time write request of LBA and each overwrite request, such guarantee writes the same LBA of caching every time The corresponding data not packet loss in memory space.
Based on this, S103 can be realized by following either type, and wherein, implementations below is all with very first time attribute Label includes the number of times of the write request of the LBA including the first data to be written that controller receives, and the second time attribute label includes Illustrate as a example by the number of times of the write request of the LBA including the second data to be written that controller receives.
Mode 1:M memory space alignment processing device respectively receives the time order and function order of write request；Cache controller is pressed According to very first time attribute tags and the second time attribute label, the LBA of the first data to be written in the buffer and the second number to be written According to different memory spaces corresponding for LBA in store the first data to be written and the second data to be written.
In this optional implementation, the mechanism that cache controller writes data receives the time of data to be written first with processor Rear order is relevant, and the time order and function order of the data to be written received with cache controller is unrelated.
As shown in Fig. 3 (a) and Fig. 3 (b), it is assumed that the time order and function order receiving data to be written according to processor is treated first Write data and the second data to be written be ranked up after obtain sequence 1: the first data to be written, the second data to be written；M memory space Including the first memory space and the second memory space, and receive the time order and function order row of write request according to corresponding processor Sequence 3: the first memory space, the second memory space is obtained after row.So, cache controller writes the process of data in caching In, no matter caching whether receive the time order and function order of data to be written be sequence 1, cache controller all is deposited to M according to sequence 1 Storage writes data in space, it may be assumed that writes the first data to be written in the first memory space, and writes second in the second memory space Data to be written.Wherein, in Fig. 3 (a), it is sequence 2: the second number to be written that cache controller receives the time order and function order of data to be written According to, the first data to be written, in Fig. 3 (b), it be to be still sequence 1 that cache controller receives the time order and function order of data to be written.
Based on mode 1, in S104a, the first data to be written and the second data to be written are write forever by cache controller successively In the memory space corresponding to LBA of the first data to be written in property medium, may include that cache controller is according to M storage Space alignment processing device respectively receives the time order and function order of write request, the data to be written of storage in this M memory space is depended on In the memory space corresponding to LBA of the first data to be written of secondary write non-volatile media.Such as, based on above-mentioned example, caching Controller writes non-volatile media according to the data to be written (the i.e. first data to be written) of storage in sequence 3 first the first memory space In the memory space corresponding to LBA of the first data to be written, then (i.e. second treats by the data to be written of storage in the second memory space Write data) write non-volatile media the first data to be written the memory space corresponding to LBA in.
Based on mode 1, in S104', cache controller deletes the first data to be written, and by permanent for the second data to be written write In the memory space corresponding to LBA of the first data to be written in property medium, may include that cache controller is according to M storage Space respectively alignment processing device receives the time order and function order of write request, deletes M memory space stores have data non- Data in later memory space, and storage is had the data write non-volatile media in last memory space of data The first data to be written the memory space corresponding to LBA in.Such as, based on above-mentioned example, cache controller will according to sequence 3 In first memory space, the data to be written (the i.e. first data to be written) of storage are deleted, and to be written by store in the second memory space In the memory space corresponding to LBA of the first data to be written of data (the i.e. second data to be written) write non-volatile media.
Mode 2: cache controller storage very first time attribute tags and the second time attribute label, and the in the buffer The LBA of one data to be written and the different memory spaces corresponding for LBA of the second data to be written store the first data to be written and second Data to be written.
In this optional implementation, the mechanism that cache controller writes data receives the time of data to be written first with processor Rear order is unrelated, and the time order and function order of the data to be written received with cache controller is relevant.
As shown in Fig. 4 (a) to Fig. 4 (d), it is assumed that the time order and function order receiving data to be written according to processor is treated first Write data and the second data to be written be ranked up after obtain sequence 1: the first data to be written, the second data to be written；And M storage sky Between include the first memory space and the second memory space, at least one write request includes the first write request and the second write request.That , during cache controller writes data in caching, no matter to receive the time order and function of data to be written suitable for cache controller Sequence is sequence 1 or sequence 2 (i.e. sequence 2: the second data to be written, the first data to be written), and cache controller all can be first Memory space writes the first data to be written and very first time attribute tags, and in the second memory space, writes the second number to be written According to the second time attribute label；Or, the first memory space writes the second data to be written and the second time attribute label, and The first data to be written and very first time attribute tags is write in the second memory space.Wherein, in Fig. 4 (a) and Fig. 4 (b), caching It is sequence 2: the second data to be written, the first data to be written that controller receives the time order and function order of data to be written, Fig. 4 (c) and Fig. 4 D (), it is still for sequence 1 that cache controller receives the time order and function order of data to be written.
Based on mode 2, in S104a, the first data to be written and the second data to be written are write forever by cache controller successively In the memory space corresponding to LBA of the first data to be written in property medium, may include that cache controller is according to the very first time First data to be written and the second data to be written are write in non-volatile media by attribute tags and the second time attribute label successively In the memory space corresponding to LBA of the first data to be written.Based on above-mentioned example, cache controller is according to very first time attribute mark Sign and sequence 1 determined by the second time attribute label, then, to be written by corresponding memory space the first of storage according to sequence 1 Data and the second data to be written write in the memory space corresponding to LBA of the data to be written of first in non-volatile media successively.
Based on mode 2, in S104', cache controller deletes the first data to be written, and by permanent for the second data to be written write In the memory space corresponding to LBA of the first data to be written in property medium, may include that cache controller is according to the very first time Attribute tags and the second time attribute label, delete the first data to be written, and by the second data to be written write non-volatile media The first data to be written the memory space corresponding to LBA in.Based on above-mentioned example, cache controller is according to very first time attribute Sequence 1 determined by label and the second time attribute label, and then, (i.e. first treats to delete non-final data to be written in sequence 1 Write data), and by be written for first in last data to be written in sequence 1 (the i.e. second data to be written) write non-volatile media In memory space corresponding to the LBA of data.
It should be noted that the technical scheme being provided above is all with controller be the first write request add first time Between attribute tags, be to illustrate as a example by the second write request adds the second time attribute label, actual when realizing, it is also possible to by Main frame is that the first write request adds very first time attribute tags, is that the second write request adds the second time attribute label.This situation Under, above-mentioned S101-S103 can be replaced by following steps: main frame is that the first write request adds very first time attribute tags, is the Two write requests add the second time attribute label, then send the first write request, the second write request, very first time genus to controller Property label and the second time attribute label.Wherein, main frame can send write request respectively by two message and be somebody's turn to do to controller The time attribute label of write request, it is also possible to the time attribute label of write request is included in this write request and is sent to control Device.Such as, main frame includes the LBA of the first data to be written, the first data to be written and to the first write request that controller sends One time attribute tags, the second write request includes the LBA of the second data to be written, the second data to be written and the second time attribute mark Sign.
Below by a concrete example, the method writing data provided above is illustrated.
As it is shown in figure 5, a kind of mutual schematic diagram of method writing data provided for the embodiment of the present invention.Side shown in Fig. 5 Method includes:
S501: main frame sends the first write request to processor, and the first write request includes that the first data to be written are to be written with first The LBA of data.
S502: processor receives the first write request, and whether stores the LBA of these the first data to be written in query caching.
The most then perform S503；If it is not, then perform S504.
S503: processor is that the first write request adds very first time attribute tags.
The LBA of the first data to be written is write in the LBA set of caching by S504: processor, and the first data to be written is sent out Give cache controller.
Owing to the present embodiment being the number of times of write request receiving with time attribute label for processor and including same LBA is Example illustrates, and therefore, if processor performing after S502, first carries out S503 and performs S504 again, then processor is first to write Request adds very first time attribute tags to represent that the first write request is that processor receives for the 1st time and includes this first data to be written The write request of LBA.
S505: cache controller receives the first data to be written, and according to very first time attribute tags by the first data to be written In the memory space corresponding to LBA of the first data to be written in write caching.
Actual when realizing, processor inquires the first data to be written written into LBA pair of the first data to be written in caching After in the memory space answered, can be to host response write response.
S506: if main frame is in the preset time period in the moment sending the first write request, does not receives the first write request corresponding Write response, then to processor send Abort order.
S507: processor receives Abort order, and to host response Abort order success.
S508: main frame receives Abort order success, and sends the second write request to processor.Second write request includes Two data to be written and the LBA of the second data to be written.
S509: whether store the LBA of these the second data to be written that the second write request includes in processor query caching.
In the present embodiment, owing in S503, processor stores the LBA of the first data to be written the most in the buffer, and this The LBA of two the data to be written and LBA of the first data to be written is identical, and therefore, the judged result of S509 is "Yes".
S510: processor is that the second write request adds the second time attribute label, and is sent to delay by the second data to be written Memory controller.
Based on the example in S504, in S510, processor is that the second write request adds the second time attribute label with table Show that the second write request is the write request that processor receives the LBA including these the second data to be written for the 2nd time.
S511: cache controller receives the second data to be written, and according to the second time attribute label by the second data to be written In the memory space corresponding to LBA of the first data to be written in write caching.
The sequencing of S505 with S508-S511 is not limited by the embodiment of the present invention, for example, it is possible to first carry out S505 performs S508-S511 again, it is also possible to first carries out S508-S511 and performs S505 again, it is also possible to performing appointing of S508-S511 S505 is performed while one step.
First data to be written and the second data to be written are write first in non-volatile media by S512: cache controller successively In memory space corresponding to the LBA of data to be written.
The above-mentioned scheme mainly provided the embodiment of the present invention from angle mutual between main frame and storage array is carried out Introduce.It is understood that main frame and storage array are in order to realize above-mentioned functions, it comprises each function of execution the hardest Part structure and/or software module.Those skilled in the art should be readily appreciated that, retouches in conjunction with the embodiments described herein The unit of each example stated and algorithm steps, the present invention can come real with the combining form of hardware or hardware and computer software Existing.Certain function performs in the way of hardware or computer software drive hardware actually, depends on the specific of technical scheme Application and design constraint.Each specifically should being used for can be used different methods to described by realization by professional and technical personnel Function, but this realization is it is not considered that beyond the scope of this invention.
The embodiment of the present invention can carry out the division of functional module according to said method example to storage array, such as, and can Each functional module is divided, it is also possible to two or more functions are integrated in a processing module with each function corresponding In.Above-mentioned integrated module both can realize to use the form of hardware, it would however also be possible to employ the form of software function module realizes.Need It is noted that in the embodiment of the present invention that the division to module is schematic, is only a kind of logic function and divides, actual real Can there is other dividing mode now.
In the case of using integrated unit, Fig. 6 shows the one of storage array involved in above-described embodiment Possible structural representation.Storage array 6 may include that processing module 602 and communication module 603.Processing module 602 is for right The action of storage array 6 is controlled management, and such as, processing module 602 is for supporting that storage array 6 performs the S103 in Fig. 2 And S104；S502, S503, S504, S505, S509, S510, S511, S512 in Fig. 5, and/or for skill described herein Other process of art.Communication module 603 is for supporting the communication of storage array 6 and other network entities, such as with Fig. 1 or Fig. 5 Shown in functional module or network entity between communication.Storage array 6 can also include: memory module 601, is used for storing The program code of storage array and data.
Wherein, the processor (i.e. CPU) during processing module 1302 can include the system shown in Fig. 1 and cache controller. Processing module 1302 can also be CPU, digital signal processor (digital signal processor, DSP), special integrated Circuit (application-specific integrated circuit, ASIC), field programmable gate array (field Programmable gate array, FPGA) or other PLDs, transistor logic, hardware component or Its combination in any of person.It can realize or perform the various exemplary logic block combined described by the disclosure of invention, Module and circuit.Processing module 1302 can also be to realize the combination of computing function, such as, comprise one or more microprocessor Combination, combination of DSP and microprocessor etc..Communication module 603 can be transceiver, transmission circuit or communication interface etc..Deposit Storage module 601 can be the caching in the system shown in Fig. 1 and non-volatile media, or other any one memorizeies or multiple deposit The combination of reservoir.
When processing module 602 is the processor in the system shown in Fig. 1 and cache controller, communication module 603 is transmitting-receiving Device, storage when memory module 601 is the caching in the system shown in Fig. 1 and non-volatile media, involved by the embodiment of the present invention Array can be as shown in Figure 7.
As it is shown in fig. 7, storage array 7 may include that processor 701, cache controller 702, transceiver 703, permanent Medium 704, caching 705 and bus 706；Wherein, processor 701, cache controller 702, transceiver 703, non-volatile media 704 and caching 705 be connected with each other by bus 706；Bus 706 can be Peripheral Component Interconnect standard (peripheral Component interconnect, PCI) bus or EISA (extended industry standard Architecture, EISA) bus etc..Described bus can be divided into address bus, data/address bus, control bus etc..For ease of Represent, Fig. 7 only represents with a thick line, it is not intended that an only bus or a type of bus.
Step in conjunction with the method described by the disclosure of invention or algorithm can realize in the way of hardware, it is possible to Realize in the way of being to be performed software instruction by processing module.Software instruction can be made up of corresponding software module, software Module can be stored on random access memory (random access memory, RAM), flash memory, read only memory (read Only memory, ROM), Erasable Programmable Read Only Memory EPROM (erasable programmable ROM, EPROM), electricity can EPROM (electrically EPROM, EEPROM), depositor, hard disk, portable hard drive, read-only optical disc (CD-ROM) or in the storage medium of other form any well known in the art.A kind of exemplary storage medium coupled to place Reason device, thus enable a processor to from this read information, and information can be write to this storage medium.Certainly, storage Medium can also be the ingredient of processor.Processor and storage medium may be located in ASIC.It addition, this ASIC can position In core network interface equipment.Certainly, processor and storage medium can also be present in core network interface as discrete assembly and set In Bei.
Those skilled in the art it will be appreciated that in said one or multiple example, merit described in the invention Can be able to realize by hardware, software, firmware or their combination in any.When implemented in software, can be by these functions It is stored in computer-readable medium or is transmitted as the one or more instructions on computer-readable medium or code. Computer-readable medium includes computer-readable storage medium and communication media, and wherein communication media includes being easy to from a place to separately One local any medium transmitting computer program.Storage medium can be universal or special computer can access any Usable medium.
Above-described detailed description of the invention, has been carried out the purpose of the present invention, technical scheme and beneficial effect further Describe in detail, be it should be understood that the detailed description of the invention that the foregoing is only the present invention, be not intended to limit the present invention Protection domain, all on the basis of technical scheme, any modification, equivalent substitution and improvement etc. done, all should Within being included in protection scope of the present invention.

Claims (14)

1. the method writing data, it is characterised in that be applied in storage array, described storage array includes controller and extremely A few non-volatile media；Described method includes:
The first write request that described controller Receiving Host sends, described first write request includes the first data to be written and described the Logical block addresses LBA of one data to be written；
After receiving described first write request, the second write request that the described controller described main frame of reception sends, described second Write request includes the second data to be written and the LBA of described second data to be written, the LBA of described second data to be written and first to be written The LBA of data is identical；
Described controller is that described first write request adds very first time attribute tags, and is that described second write request adds second Time attribute label；Described very first time attribute tags is used for the time indicating described controller to receive described first write request, Described second time attribute label receives the time of described second write request for indicating described controller；
Described controller is according to described very first time attribute tags and described second time attribute label, by described first number to be written According to the LBA institute writing described first data to be written in described non-volatile media with described second data to be written according to sequencing In corresponding memory space.
Method the most according to claim 1, it is characterised in that described controller receive described first write request it After, described method also includes:
Described controller receives the Abort order that described main frame sends, and wherein, described Abort order is used for notifying described storage Array: described first write request abandoned by described main frame；
Described controller is to described host response Abort order success；
Described controller receives described second write request, including:
Described controller, after described host response Abort order success, receives described second write request.
Method the most according to claim 1 and 2, it is characterised in that described very first time attribute tags includes described control The number of times of the write request of the LBA including described first data to be written that device receives；Described second time attribute label includes described The number of times of the write request of the LBA including described second data to be written that controller receives.
Method the most according to claim 3, it is characterised in that described controller includes processor and caching；Described control The first write request that device Receiving Host sends, including:
Described processor receives described first write request that described main frame sends；
After described processor receives described first write request that described main frame sends, described method also includes:
Described processor determines when the LBA in described caching does not comprise the LBA with described first data to be written in gathering, by institute The LBA stating the first data to be written writes described LBA set；Wherein, described LBA set includes meeting in pre-conditioned write request Including LBA；Wherein, described meet pre-conditioned write request and refer to that described processor receives and included to be written Data do not write the write request of described caching；
Described controller is that described second write request adds the second time attribute label, including:
During the LBA that described processor comprises described second data to be written in inquiring described LBA set, writing for described second please Seek interpolation the second time attribute label.
Method the most according to claim 4, it is characterised in that described controller also includes cache controller；Described control Device is according to described very first time attribute tags and described second time attribute label, by described first data to be written and described second Data to be written are empty according to the storage corresponding to the LBA of described first data to be written in the sequencing described non-volatile media of write In between, including:
Described cache controller, according to described very first time attribute tags and described second time attribute label, is treated described first Write data and described second data to be written write the memory space corresponding to LBA of described first data to be written in described caching In；
Described first data to be written and described second data to be written are write described non-volatile media by described cache controller successively In the memory space corresponding to LBA of described first data to be written.
Method the most according to claim 5, it is characterised in that in described caching, LBA pair of described first data to be written Answering M memory space, M >=2, M is integer；Described M memory space corresponding described processor respectively receives the priority of write request Sequentially；
Described cache controller, according to described very first time attribute tags and described second time attribute label, is treated described first Write data and described second data to be written write the memory space corresponding to LBA of described first data to be written in described caching In, including:
Described cache controller, according to described very first time attribute tags and described second time attribute label, is deposited at described M Different memory spaces in storage space store described first data to be written and described second data to be written.
Method the most according to claim 5, it is characterised in that in described caching, LBA pair of described first data to be written Answering M memory space, M >=2, M is integer；
Described cache controller, according to described very first time attribute tags and described second time attribute label, is treated described first Write data and described second data to be written write the memory space corresponding to LBA of described first data to be written in described caching In, including:
Described cache controller stores described very first time attribute tags and described second time attribute label, and at described M Different memory spaces in memory space store described first data to be written and described second data to be written.
8. a storage array, it is characterised in that include controller and at least one non-volatile media；Described controller is used for:
The first write request that Receiving Host sends, described first write request includes the first data to be written and described first data to be written Logical block addresses LBA；
After receiving described first write request, receiving the second write request that described main frame sends, described second write request includes Second data to be written and the LBA of described second data to be written, the LBA and the LBA of the first data to be written of described second data to be written Identical；
Add very first time attribute tags for described first write request, and add the second time attribute mark for described second write request Sign；Described very first time attribute tags receives the time of described first write request, when described second for indicating described controller Between attribute tags for indicate described controller receive described second write request time；
According to described very first time attribute tags and described second time attribute label, by described first data to be written and described Two data to be written are according to the storage corresponding to the LBA of described first data to be written in the sequencing described non-volatile media of write In space.
Storage array the most according to claim 8, it is characterised in that
Described controller is additionally operable to: receiving the Abort order that described main frame sends, wherein, described Abort order is used for notifying institute State main frame described in storage array and abandon described first write request；To described host response Abort order success；
Described controller specifically for: to described host response Abort order success after, receive described second write request.
Storage array the most according to claim 8 or claim 9, it is characterised in that described very first time attribute tags includes described The number of times of the write request of the LBA including described first data to be written that controller receives；Described second time attribute label includes The number of times of the write request of the LBA including described second data to be written that described controller receives.
11. storage arrays according to claim 10, it is characterised in that described controller includes processor and caching；
Described processor is used for: receive described first write request that described main frame sends；
Described processor is additionally operable to: determines in the set of the LBA in described caching and does not comprise and the LBA of described first data to be written Time, the LBA of described first data to be written is write described LBA set；Wherein, described LBA set includes meeting pre-conditioned The LBA that write request includes；Wherein, described meet pre-conditioned write request and refer to that described processor receives and wrapped The data to be written included do not write the write request of described caching；
Described processor is additionally operable to: during the LBA comprising described second data to be written in inquiring described LBA set, for described Second write request adds the second time attribute label.
12. storage arrays according to claim 11, it is characterised in that described controller also includes cache controller；
Described cache controller is used for: according to described very first time attribute tags and described second time attribute label, by described First data to be written and described second data to be written write depositing corresponding to the LBA of described first data to be written in described caching In storage space；Described first data to be written and described second data to be written are write successively described in described non-volatile media The memory space corresponding to LBA of one data to be written.
13. storage arrays according to claim 12, it is characterised in that in described caching, described first data to be written LBA correspondence M memory space, M >=2, M is integer；Described M memory space corresponding described processor respectively receives write request Sequencing；
Described cache controller specifically for: according to described very first time attribute tags and described second time attribute label, Different memory spaces in described M memory space store described first data to be written and described second data to be written.
14. storage arrays according to claim 13, it is characterised in that in described caching, described first data to be written LBA correspondence M memory space, M >=2, M is integer；
Described cache controller specifically for: store described very first time attribute tags and described second time attribute label, and Different memory spaces in described M memory space store described first data to be written and described second data to be written.
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