CN106233460A

CN106233460A - Semiconductor device and manufacture method thereof including the redistributing layer thickeied

Info

Publication number: CN106233460A
Application number: CN201580020681.0A
Authority: CN
Inventors: C.M.斯坎伦; C.毕晓普
Original assignee: Deca Technologies Inc
Current assignee: Deca Technologies USA Inc
Priority date: 2014-03-10
Filing date: 2015-03-09
Publication date: 2016-12-14
Also published as: HK1232338A1

Abstract

The invention provides a kind of method manufacturing semiconductor packages, described method may be included in and forms multiple thick redistributing layer (RDL) trace above the active surface of multiple semiconductor element, and the plurality of thick redistributing layer trace is electrically connected to the contact pad on the plurality of semiconductor element；Segmentation includes the plurality of semiconductor element of the plurality of thick RDL trace；The plurality of semiconductor element of segmentation is arranged on the top of temporary carrier, and the described active surface of wherein said multiple semiconductor elements deviates from described temporary carrier orientation；Above the described active surface of each sealant material being arranged in the plurality of semiconductor element and at least four side surface, above the plurality of thick RDL trace and above described temporary carrier；Form the through hole through described sealant material, with at least one trace in the RDL trace relative to the plurality of thickening of exposure of described sealant material；Remove described temporary carrier, and split the plurality of semiconductor element.

Description

Semiconductor device and manufacture method thereof including the redistributing layer thickeied

The cross reference of related application

This application claims the entitled " Wafer-Level-Chip-Scale-Packages submitted on March 10th, 2014 With Thick Redistribution Layer Traces (has the wafer level chip scale envelope of thick redistributing layer trace Dress) " the rights and interests of US provisional patent No.61/950,743；And the application or the title of December in 2014 submission on the 29th For " (tube core is positioned at top and fully molding to Die Up Fully Molded Fan-Out Wafer Level Packaging Fan-out wafer level encapsulates) " U.S. Patent application No.14/584, the part continuity of 978, and U.S. Patent application No.14/ 584,978 is entitled " the Die Up Fully Molded Fan-Out Wafer Level of JIUYUE in 2013 submission on the 12nd The Packaging encapsulation of fan-out wafer level of top and fully molding (tube core be positioned at) " U.S. Patent application No.14/024,928 Continuity, and be distributed as patent No.8, the U.S. Patent application No.14/024 of 922,021,928 are JIUYUE in 2012 30 Submit to entitled " Die Up Fully Molded Fan-Out Wafer Level Packaging (and tube core be positioned at top and The fully fan-out wafer level encapsulation of molding) " U.S. Patent Application Serial No.13/632, the part continuity of 062, and having sent out The U.S. Patent application No.13/632,062 of behavior patent No.8,535,978 is the entitled of December in 2011 submission on the 30th The U.S. Patent application No.13/341 of " Fully Molded Fan-Out (fan-out of abundant molding) ", the part continuity of 654, It is distributed as patent No.8,604,600, and require the entitled " Fan-Out submitted on July 18th, 2012 Semiconductor Package (fan-out-type semiconductor package part) " the US provisional patent No.61/672,860 submission date Rights and interests, the disclosure of this application is incorporated by herein accordingly.

Technical field

The disclosure relates generally to semiconductor device, more particularly, and the redistributing layer (RDL) relating to comprise thickening The board-like encapsulation of embedded semiconductor die package.

Background technology

Semiconductor device is prevalent in modern electronic product.Semiconductor device is in the quantity of electronic unit and density side There is difference in face.Discrete-semiconductor device generally comprises a type of electronic unit, such as light emitting diode (LED), small-signal Transistor, resistor, capacitor, inducer and power metal oxide semiconductor field-effect transistor (MOSFET).Integrated Semiconductor device generally includes hundreds of to millions of electronic units.The example of integrated-semiconductor device includes microcontroller, micro- Processor, charge-coupled image sensor (CCD), solaode and DMD (DMD).

Semiconductor device perform broad range function, such as signal processing, supercomputing, launch and receive electromagnetism letter Number, control electronic equipment, convert sunlight into electric power and for television indicator create visual projection.Semiconductor device exists In the field of amusement, communication, Power convert, network, computer and consumer goods.Semiconductor device exist in Military Application, In aviation, automobile, industrial control unit (ICU) and office equipment.

Semiconductor device makes full use of the electrical properties of semi-conducting material.The atomic structure of semi-conducting material allows by executing Added electric field or base current or handle its electrical conductivity by doping process.Doping process adds impurities to semi-conducting material In with handle and control semiconductor device electrical conductivity.

Semiconductor device includes active and passive electric structure.Active including bipolar transistor and field-effect transistor The flowing of structure control electric current.By changing doped level and electric field or the applying of base current, transistor promotes or limits electricity The flowing of stream.Passive structures including resistor, capacitor and inducer produces voltage necessary to the various electric functions of execution And the relation between electric current.Passive structures and active structure are electrically connected to form circuit, and described circuit makes semiconductor device energy Enough perform supercomputing and other useful functions.

Semiconductor device is usually and uses two complicated manufacturing process (that is, front end manufactures and rear end manufacture) to make Making, each manufacturing process may relate to hundreds of step.Front end manufactures and relates to forming multiple half on the surface of semiconductor crystal wafer Conductor tube core.Each semiconductor element is the most identical and includes being formed by being electrically connected with source block and passive component Circuit.Rear end manufactures and relates to splitting single semiconductor element from product wafer and encapsulating this tube core to provide structure to prop up Hold and be environmentally isolated." semiconductor element " refers to odd number and the word of both forms of plural number as the term is employed herein, and therefore May refer to single semiconductor device and multiple semiconductor device.

One target of semiconductor manufacturing is to produce less semiconductor device.Less device generally consumes less merit Rate, has higher performance, and can be produced more efficiently.It addition, less semiconductor device has less occupying Area, this is desired for less end product.Less transistor can be realized by improving front-end process Core size, thus obtain that there is small volume, the semiconductor element of active and passive component that density is higher.Backend process is permissible The semiconductor packages with less occupied area is obtained by electrical interconnection and the improvement of encapsulating material.

A kind of method of the back-end processing more effectively producing the semiconductor device of encapsulation is to use board-like encapsulation, is wherein permitted Multiple semiconductor tube core is formed in panel and is handled simultaneously under the level of restructuring wafer or panel.Board-like encapsulation can be used for Rear end manufactures, and is used for forming embedded die package.For encapsulating the board-like encapsulation of a kind of form of semiconductor element it is FOWLP.FOWLP relates to multiple semiconductor elements " facing down " active surface placing or making semiconductor element towards interim load Body or substrate (such as interim tape carrier) orientation.(such as epoxy moulds by sealant for semiconductor element and substrate or carrier Compound) use the most compression molded technique Overmolded.After the moulding, remove carrier tape, attach most importance to expose to be formed together The active surface of multiple semiconductor elements of group wafer.Subsequently, at restructuring wafer or the top of panel, formed to generally include and divide again Wafer level chip scale encapsulation (WLCSP) of layer of cloth (RDL) piles up interconnection structure.Then, formation above interconnection structure is being piled up Conductive projection is as BGA (BGA), and BGA is attached to wafer of recombinating.After forming BGA, segmentation restructuring wafer is single to be formed Only semiconductor device or encapsulation.

Summary of the invention

Therefore, on the one hand, the present invention can be the method manufacturing semiconductor package part, and the method may be included in multiple partly to be led Forming multiple thick redistributing layer (RDL) trace above the active surface of body tube core, multiple thick redistributing layer traces are electrically connected to many Contact pad on individual semiconductor element.The multiple semiconductor elements including multiple thick RDL trace can be split.Segmentation Multiple semiconductor elements may be mounted to that the top of temporary carrier, the active surface of multiple semiconductor elements are directed away from temporarily Carrier.Sealant material may be provided at the active surface of each in multiple semiconductor element and the upper of at least four side Above side, multiple thick RDL trace and above temporary carrier.The through hole through sealant material can be formed expose relative to close At least one trace in multiple thickening RDL traces of envelope agent material.Removable temporary carrier, and divisible multiple quasiconductor Tube core.

The method manufacturing semiconductor device may also include the multiple thick RDL trace forming thickness or height more than 5 microns, and Utilizing laser ablation method to form the through hole through sealant material, wherein this sealant material is a kind of non-photo-imaging material. The method can also include, for each in multiple semiconductor elements, multiple thick RDL traces are formed as fan-in structure, described In the occupied area of multiple thick RDL trace each in they corresponding semiconductor elements.The method can also include being formed Being connected to the electrical interconnection of at least one trace thickeied described, wherein electrical interconnection extends to the outside of semiconductor package part, Electrical interconnection is made to be formed as lower protruding block metallization (UBM) pad, land grid array (LGA) pad, Quad Flat No-leads (QFN) weldering Dish or projection.The method can also include electrical interconnection is directly attached to multiple thick RDL trace.The method can be additionally included in multiple Back side epoxy coating or dielectric film is formed on the back side relative with active surface of semiconductor element.

On the other hand, the present invention can be a kind of method manufacturing semiconductor package part, and the method is included in transistor Forming multiple thick RDL trace above the active surface of core, multiple thick RDL traces are connected to connecing on semiconductor element active surface Touch pad.Sealant material may be provided at the active surface of semiconductor element and the top of at least four side and multiple thickness Above RDL trace.At least one trace in the RDL trace of multiple thickenings can be exposed relative to sealant material.Electricity can be formed Cross tie part is also connected at least one trace thickeied.

The method manufacturing semiconductor device may also include the multiple thick RDL trace forming thickness or height more than 5 microns, and The through hole utilizing laser ablation method to be formed through sealant material to expose in multiple thickening RDL traces relative to sealant material At least one trace, wherein sealant material is a kind of non-photo-imaging material.The method may also include formation thickness or height The degree multiple thick RDL trace more than 20 microns so that the height of thick RDL trace is more than the minimum widith of thick RDL trace, and passes through Grind at least one trace in the RDL trace exposing multiple thickenings relative to sealant material.The method can also include for Each in multiple semiconductor elements forms multiple thick RDL trace, and the plurality of thick RDL trace is at they corresponding quasiconductors In the occupied area of each in tube core.The method can also include forming the electricity being connected at least one trace thickeied described Cross tie part, wherein electrical interconnection extends to the outside of semiconductor package part, make electrical interconnection be formed as UBM pad, LGA pad, QFN pad or projection.The method may also include formation fan-out formula and piles up cross tie part, and this structure is arranged on thick RDL trace and electricity is mutual Even between part.The method can be additionally included on the back side relative with active surface of multiple semiconductor element formation back side epoxy and be coated with Layer or dielectric film.The method can be additionally included in single step, and sealant material is arranged on the active surface of semiconductor element Above the top of at least four side and multiple thick RDL trace.The method can also include when semiconductor element is natural half During semiconductor wafer a part of, above the active surface of this semiconductor element, form multiple thick RDL trace, and will comprise multiple The semiconductor element of thick RDL trace separates from natural wafer.

In yet another aspect, the present invention can be a kind of semiconductor package part, and this semiconductor package part can include being arranged on half With the multiple thick RDL traces being arranged in semiconductor element occupied area above conductor die active surface, it is arranged on quasiconductor Above the active surface of tube core and at least four side and be arranged on the sealant material above multiple thick RDL trace, and The conductive interconnection part of a part at least one trace being connected in multiple thickening RDL trace, plurality of thickening RDL trace In at least one trace this part relative to sealant material expose.

Semiconductor package part can also include thickness or the height multiple thick RDL trace more than 5 microns.Multiple thick RDL traces Thickness or height comparable width big.Multiple thick RDL traces may be provided in the occupied area of semiconductor element.At transistor Back side epoxy coating or dielectric film can be formed on the back side relative with active surface of core.

From the point of view of specification, drawings and the claims book, above-mentioned aspect and other aspects, features and advantages are for this The those of ordinary skill in field will be apparent from.

Accompanying drawing explanation

Figure 1A to Fig. 1 E shows according to the multiple semiconductor elements that embodiment of the disclosure, the plurality of semiconductor element Including the thick RDL conductive trace for semiconductor package part or embedded die package.

Fig. 2 A to Fig. 2 G shows to be formed and includes the semiconductor package part of thick RDL conductive trace or embedded die package The view of method.

Fig. 3 shows the cross-sectional side view of the embodiment of the semiconductor package part including thick RDL conductive trace.

Fig. 4 shows the cross-sectional side view of another embodiment of the semiconductor package part including thick RDL conductive trace.

Fig. 5 A to Fig. 5 D shows to be formed and includes the semiconductor package part of thick RDL conductive trace or embedded die package The view of method.

Fig. 6 shows the cross-sectional side view of another embodiment of the semiconductor package part including thick RDL conductive trace.

Fig. 7 shows the cross-sectional side view of another embodiment of the semiconductor package part including thick RDL conductive trace.

Fig. 8 shows the cross-sectional side view of another embodiment of the semiconductor package part including thick RDL conductive trace.

Fig. 9 shows the cross-sectional side view of another embodiment of the semiconductor package part including thick RDL conductive trace.

Figure 10 shows that the cross-sectional side of another embodiment of the semiconductor package part including thick RDL conductive trace regards Figure.

Figure 11 shows that the cross-sectional side of another embodiment of the semiconductor package part including thick RDL conductive trace regards Figure.

Figure 12 shows that the cross-sectional side of another embodiment of the semiconductor package part including thick RDL conductive trace regards Figure.

Detailed description of the invention

The disclosure is included in below with reference to the one or more embodiments in the description of accompanying drawing, wherein similar digital table Show same or analogous assembly.It will be appreciated by those skilled in the art that this specification be intended to alternative form, modification and Equivalent way, these alternative forms, modification and equivalent way can be included in is propped up by disclosure subsequently and accompanying drawing Within the spirit and scope of the disclosure that the claims held and equivalents thereof are limited.

In the following description, set forth many specific detail, such as particular configuration, compositions and technique etc., in order to put forward For thorough understanding of this disclosure.In other instances, well-known technique and manufacturing technology are described the most in particular detail, In order to avoid unnecessarily obscuring the disclosure.Additionally, the various embodiments shown in accompanying drawing are exemplary expression, it is not necessarily to scale Draw.

As used herein term " ... top ", " ... between ", " ... on " refer to one layer relative to other layers Relative position.Deposition or be arranged on a layer above or below another layer and directly can contact with this another layer and maybe can have one Individual or multiple intermediate layers.Deposition or be arranged on one layer of interlayer and directly can contact with this layer and maybe can have one or more centre Layer.Comparatively speaking, the second layer " on " ground floor contact with this second layer.

Semiconductor device is usually and uses two complicated manufacturing process (that is, front end manufactures and rear end manufacture) to make Make.Front end manufactures and relates to forming multiple tube core on the surface of semiconductor crystal wafer.Each tube core on wafer includes active electronic Parts and passive electrical components, these electronic units are electrically connected to form functional circuit.Active electronic component, such as transistor and Diode, has the ability controlling electric current flowing.Passive electrical components, such as capacitor, inducer, resistor and transformator, Produce in the relation performed between voltage and current necessary to circuit function.

By series of process step, including doping, deposition, photoetching, etch and polish and on semiconductor wafer surface Form passive component and active parts.Doping process is drawn in semi-conducting material by the technology of such as ion implanting or thermal diffusion Enter impurity.In active device, doping process changes the electrical conductivity of semi-conducting material, thus semi-conducting material is transformed into insulation Body, conductor, or the electrical conductivity of semi-conducting material is dynamically changed in response to electric field or base current.Transistor comprises doping Type and the different region of degree, described region is arranged to make transistor can apply electric field or base stage electricity as required Promote or limit the flowing of electric current during stream.

By there is the layer of material of different electrical property to be formed with source block and passive component.Can be by partly by quilt Various deposition techniques determined by deposition material type form these layers.Such as, thin film deposition can relate to chemical gaseous phase deposition (CVD), physical vapour deposition (PVD) (PVD), electrolysis plating and electroless plating.Typically by each pattern layers to form active portion The part of the electrical connection between part, passive component or parts.These layers can use photoetching process to pattern.Patterning is basic behaviour Make, remove the part of top layer on semiconductor wafer surface by it.Can use photoetching process, photomask, mask, oxide or Metal removal, lithoprinting and mould printing and microlithography remove the part of semiconductor crystal wafer.Photoetching process bag Include in reticle mask (reticle) or photomask, to form pattern and transfer the pattern onto layer to be patterned and the most partly lead In the surface layer of body wafer.In two-step process, photoetching process is formed with source block and passive component on the surface of semiconductor crystal wafer Horizontal size.First, during the pattern on reticle mask or photomask is transferred to photoresist oxidant layer.Photoresist is Light-sensitive material, this light-sensitive material can experience structure and qualitative change when being exposed to light.Change the structure of photoresist Occur as negative effects photoresist or positivity effect photoresist with the process of character.Secondly, photoresist Layer is transferred in crystal column surface.This transfer removes, in etching, the part that semiconductor crystal wafer top layer is not covered by photoresist Shi Fasheng.Alternatively, some type of material patterns by directly depositing material in region or space, This region or space are formed by photoresist, or by use such as electroless plating and electrolysis plating technology previous deposition/ Etch process is formed.The chemical property of photoresist makes, not covered by photoresist of semiconductor crystal wafer top layer Part be removed or added by plating while, photoresist keep essentially completed and opposing be chemically etched solution Or Plating chemistry removal.According to use specific resist and desired as a result, it is possible to amendment shape, expose and remove photic The technique of resist, and remove a part for semiconductor crystal wafer or add the technique of a part of wafer to.

In negative effects photoresist, photoresist be exposed to light and in the technique of referred to as polymerization from Solvable situation changes into insoluble situation.In polymerization, unpolymerized material is exposed to light or energy source and polymer is formed Anti-etching cross-linked material.In most of negative resists, polymer is polyisoprene.Go with chemical solvent or developing agent Except soluble fraction (being i.e. not exposed to the part of light) stays corresponding with the opaque pattern on reticle mask in resist layer Hole.The mask that pattern is present in zone of opacity is referred to as clear-field mask.

In positivity effect photoresist, photoresist is exposed to light and from phase in the technique that referred to as light dissolves Insoluble situation is changed into more readily soluble situation.In light dissolves, relatively immiscible resist is exposed to suitable luminous energy Measure and be converted into more solvable state.The light of resist dissolves part can be removed by the solvent in developing process.Basic Positive photoresist polymer is phenol-formaldehyde polymer, also referred to as phenol-formaldehyde novolaRs resin.Use chemical solvent Or developing agent removal soluble fraction (being i.e. exposed to the part of light) stays and the transparent pattern on reticle mask in resist layer Corresponding hole.The mask that pattern is present in transparent region is referred to as dark-field mask.

Behind the top not covered by photoresist removing semiconductor crystal wafer, remove its remaining part of photoresist Point, leave the layer of patterning.

Alternatively, when material to be patterned self has heliosensitivity, photoresist can not used Photoetching process is completed in the case of agent.In this case, use spin coating, lamination or other suitable deposition techniques by light-sensitive material It is coated on device surface.Then, in the operation of commonly referred to exposure, make to use up and pattern is transferred to photosensitive material from photomask Material.In one embodiment, the part using solvent light in light-sensitive material to be irradiated is removed or development, thus exposes underlying bed Part.Alternatively, in another embodiment, the part that non-light in light-sensitive material is irradiated by solvent is used Remove or development, thus expose the part of underlying bed.The remainder of photosensitive film becomes the permanent sections of device architecture.Existing Deposit a thin layer material on some patterns to amplify the pattern of lower section and form uneven smooth surface.Manufacture less and more The active parts of intensive packaging and passive component need the surface of uniform flat.Polish and can be used to remove material also from crystal column surface Manufacture the surface of uniform flat.Polish and relate to coming wafer polishing surface with polishing pad.Abrasive material and eroding chemical are in the polishing phase Between be added to crystal column surface.Alternatively, abrasion is used or not eroding chemical to polish.? In some embodiments, by using abrasive belt grinding machine, standard wafer mill back of the body machine, surface lapping machine or other similar machines to realize Purely mechanic abrasion.The mechanism of abrasive material and the corrosiveness of chemicals are combined, remove any irregular pattern, thus obtain Surface to uniform flat.

Rear end manufactures and relates to product wafer cutting or be divided into independent semiconductor element, then encapsulation semiconductor element with Support for structure and be environmentally isolated.For dividing semiconductor tube core, the non-functional of saw lanes or line can be referred to as along wafer District's cutting crystal wafer.Laser cutting tool or saw blade is used to split wafer.After singulation, independent semiconductor element is installed to bag Include for the package substrate with the pin or contact pad of other system component connection.Then will be formed on a semiconductor die Contact pad is connected to the contact pad in encapsulation.Available solder projection, stud bumps, electrocondution slurry, redistributing layer or wire bond Realize electrical connection.It is deposited in encapsulation to provide physical support and electric isolution by sealant or other molding materials.Then will become It is available for other system parts that product encapsulation is inserted in electrical system and makes the functional of semiconductor device.

Electrical system can be to use semiconductor device to perform the autonomous system of one or more electric function.As separately Outer a kind of selection, electrical system can be the subassembly of bigger system.Such as, electrical system can be cell phone, individual number Word assistant (PDA), digital camera (DVC) or a part for other electronic communication equipments.Alternatively, it is electrically System can be video card, NIC or other signal processing cards that may be inserted into computer.Semiconductor package part can include micro- Processor, memorizer, special IC (ASIC), logic circuit, analog circuit, RF circuit, discrete device or other partly lead Body tube core or electronic unit.In order to make product be accepted by market, miniaturization and lightweight are necessary.Between semiconductor device Distance must be reduced to make higher density.

By combining one or more semiconductor package part on single substrate, pre-constructed unit can be attached to electronics by manufacturer In device and system.Because semiconductor package part includes the function of complexity, it is possible to use less expensive parts and streamline Manufacturing process manufactures electronic device.Obtained device is unlikely out of order and manufacturing cost is lower, thus reduces The cost of consumer.

In the following discussion, the formation with reference to single die FOWLP describes some embodiment, but embodiment of the disclosure It is not limited to this.Embodiment of the disclosure and can be used for any board-like package application, including single die application, Multi-core module, embedding In tube core in printed substrate panel or the tube core of PCB, module and certain combination of passive component or module one or many Certain combination of individual device cell and other parts.In one aspect, embodiment of the disclosure can eliminate or reduce because of spell Device cell or the misalignment of miscellaneous part during plate and the encapsulation that causes or the yield loss of modular assembly.The opposing party Face, embodiment of the disclosure and can maintain and encapsulate or module profile is consistent, and need not change UBM pad or the position of BGA ball Put.Maintain and encapsulation or module profile is consistent can the most as one man realize, such as final products encapsulation, test Socket etc..In yet another aspect, embodiments of the invention can allow to have on device cell less bond pad openings.

Figure 1A shows the plane graph of the semiconductor crystal wafer 20 with the base substrate materials 22 for structure support, this base Plinth backing material is such as, but not limited to silicon, germanium, GaAs, indium phosphide or carborundum.Multiple semiconductor elements or parts 24 are formed On wafer 20, separated, as mentioned above by wafer area passive, between tube core or saw lanes 26.Saw lanes 26 provides cutting zone Semiconductor crystal wafer 20 to be divided into single semiconductor element 24.

Figure 1B shows the viewgraph of cross-section of a previous part at semiconductor crystal wafer 20 shown in the plane graph of Figure 1A.Often Individual semiconductor element 24 has the back side or back surface 28 and the active surface 30 contrary with the back side.Active surface 30 includes simulation electricity Road or digital circuit, it is achieved active for formed in tube core and be electrically interconnected according to electrical design and the function of semiconductor element Device, passive device, conductive layer and dielectric layer.Such as, circuit can include one or more transistor, diode and active Other circuit units formed in surface 30, to realize analog circuit or digital circuit, such as DSP, ASIC, memorizer or other Signal processing circuit.Semiconductor element 24 may also comprise the integrated passive devices (IPD) for RF signal processing, such as inductance Device, capacitor and resistor.

Use PVD, CVD, electrolysis plating, electroless plating or other suitable metal deposition process on active surface 30 Square one-tenth conductive layer 32.Conductive layer 32 can be one or more layers aluminum (Al), copper (Cu), stannum (Sn), nickel (Ni), gold (Au), Silver (Ag) or other suitable conductive materials.Conductive layer 32 as the circuit being electrically connected on active surface 30 contact pad or Bond pad works.Conductive layer 32 is formed as contact pad, with the border first of semiconductor element 24 apart from setting side by side Put, as shown in fig. 1b.Alternatively, conductive layer 32 is formed as contact pad, and described contact pad is with multirow Skew, so that the first row contact pad is configured to border the first distance with tube core, and replaces with the first row The second row contact pad be configured to the border second distance with tube core.In another embodiment, conductive layer 32 can Being formed as contact pad, described contact pad is set to the array format in the region, whole surface across semiconductor element 24.According to The configuration of semiconductor element and design, full array contact pads be formed as the rule across the whole surface of semiconductor element 24 or Irregular pattern.Similarly, relative to each other, the size of contact pad, shape or orientation can also be irregular, and can Including the conductive material of certain length, this conductive material is across the active surface 30 laterally route signal of semiconductor element 24.

Figure 1B also show the optional insulating barrier or passivation layer formed above the active surface 30 of semiconductor element 24 36.Insulating barrier 36 can be conformably applied to semiconductor element 24, and has the bottom surface consistent with the profile of semiconductor element 24 Or first surface.Insulating barrier 36 has the top planar surface relative with first surface or the second flat surface 37.Insulating barrier 36 is permissible It is organic layer or inorganic layer, and includes the actinodielectric resist of one or more layers low solidification temperature, photosensitive compound resist, layer Polymerisable compounds film, solder mask resist film, liquid mold compound, silicon dioxide (SiO2), silicon nitride (Si3N4), oxynitriding Silicon (SiON), aluminium oxide (Al2O3) or there is the other materials of similar insulating properties and architectural characteristic.Available printing, rotation Painting, spraying, lamination or other suitable technique carry out depositing insulating layer 36.Laser ablation, etching or other suitable works can be passed through Skill removes a part for insulating barrier 36, thus the configuration and design according to semiconductor element exposes the bottom surface of opening 38 and partly lead The contact pad 32 of body tube core 24.Insulating barrier 36 can be patterned into passing completely through the opening 38 that insulating barrier 36 extends, at this Insulating barrier 36 also can optionally be solidified afterwards.

Fig. 1 C shows conductive layer or the RDL including multiple thick RDL trace 40, and the plurality of thick RDL trace 40 can use Patterning and metal deposition process, such as sputter, be electrolysed plating and electroless plating formed.Thick RDL trace 40 can be to include planting One or more layers Al, Cu, Sn, Ni, Au, Ag of crystal layer, barrier layer and adhesive layer or other suitable conductive materials.Thick RDL Trace 40 may be electrically connected to contact pad 32.According to the Design and Features of semiconductor element 24, other portions of thick RDL trace 40 Point, such as each RDL trace can be electrically to share or electrical isolation.

Fig. 1 C shows an embodiment, wherein thick RDL trace 40 can by first deposit pattern afterwards interim insulating barrier or Passivation layer 42 is formed.Insulating barrier 42 can be conformably applied to semiconductor element 24, insulating barrier 36 or both, and have with Semiconductor element 24, insulating barrier 36, or the first surface that both profile is consistent.Insulating barrier 42 can have relative with first surface The second flat surface.Insulating barrier 42 can be organic layer or inorganic layer, and includes photosensitive Jie of one or more layers low solidification temperature Electricity resist, photosensitive compound resist, lamination compound film, solder mask resist film, liquid mold compound, SiO2, Si3N4, SiON, Al2O3, polyimides or there is the other materials of similar insulating properties and architectural characteristic.Available printing, Spin coating, spraying, lamination or other suitable technique carry out depositing insulating layer 36.Insulating barrier 42 can be patterned into passing completely through absolutely The opening of edge layer, and expose contact pad 32 by insulating barrier 36 if present.Insulating barrier 36 also can be by optionally Solidification, and a part for the permanent structure of final semiconductor package part can be formed.Alternatively, insulating barrier 36 can be temporary layer (such as, photoresist oxidant layer), and it is the most just removed, and is formed without the one of semiconductor element final structure Part.Insulating barrier 42 can be at the disposed thereon of insulating barrier 36, and maybe when omitting optional insulating barrier 36, insulating barrier 42 can be at quasiconductor The top of tube core 24 contacts deposition.A part for insulating barrier 42 can be removed by laser, or is photoresist when it During oxidant layer, it can be made to expose and removed by etching developing process.Then, if there is thick RDL trace 40, it can be in insulation Being removed in part and opening 38 of layer 42 is formed.Opening in opening 38 and insulating barrier 42 can be formed in the same time, it is possible to Formed in the different time.Whole traces 40 of thick RDL can be formed in the same time, or the some of conductive layer can be in difference Time formed.After thick RDL trace 40 is formed, the most removable insulating barrier 42.

Complete thick RDL trace 40 can be thick RDL layer, this thickness RDL layer include for by the signal of telecommunication from semiconductor element The 24 multiple thick RDL traces being routed to the multiple points outside semiconductor package part, this semiconductor package part includes semiconductor element. Can be normal or perpendicular to measuring thickness or the height of thick RDL trace 40 on the z direction in x direction and y direction, z direction is across crystalline substance The top surface (including the active surface 30 of semiconductor element 24) of circle 20 extends, as shown in Figure 1A.Therefore, thick RDL trace 40 Thickness or highly may begin at the top surface 37 of insulating barrier 36, and on the direction contrary with back surface 28, from active surface to Upper extension or be extended active surface to the top surface 42 of thick RDL, thus form thickness T2.Alternatively, thick The thickness of RDL trace 40 or highly may begin at the active surface 30 of semiconductor element 24, and in the direction contrary with back surface 28 On, upwardly extend or be extended active surface from active surface to the top surface 42 of thick RDL, thus form thickness T2.Thickness The height of T1 and thickness T2 is more than 4 μm, or more than 5 μm, 10 μm, 20 μm, 30 μm or 35 μm.In certain embodiments, thick RDL mark The thickness of line 40 is in the range of 4 μm to 35 μm or 5 μm to 30 μm.Forming thick RDL trace 40 can be by only using a kind of work Skill and structure are achieved with using kinds of processes and structure (such as to form independent redistributing layer and independent perpendicular interconnection part (such as post or copper post)) beneficial effect that could realize.

In Fig. 1 D, semiconductor crystal wafer 20 carrys out flattened surface through the optional grinding operation of grinding machine 46, and reduces quasiconductor The thickness of wafer.Chemical etching can also be used for removing and polish semiconductor crystal wafer 20.

Fig. 1 E shows after the final thickness realizing semiconductor crystal wafer 20, can shape on the back side or lower surface of wafer 20 Become optional insulating barrier or passivation layer 50, to cover the back surface 28 of semiconductor element 24.Insulating barrier 50 can be epoxy film, lead Thermal epoxy, epoxy resin, the epoxy film of B-staged, there is ultraviolet (UV) B-staged of optional acrylic polymer Film, dielectric film or other suitable materials.Insulating barrier 50 may be provided at the whole back side 28 or the most whole of semiconductor element 24 Above the back side 28, and can be in direct contact with it, what therefore its occupied area was substantially equal to semiconductor element 24 occupies face Long-pending.After Fig. 1 E is also shown in applying insulating barrier 50, saw blade or laser cutting tool 52 can be used semiconductor die by saw lanes 26 Circle 20 is divided into single semiconductor element 24.Owing to thick RDL trace 40 can be at semiconductor element from its natural semiconductor crystal wafer Just being formed above semiconductor element 24 before 20 segmentations, therefore thick RDL trace is formed as fan-in interconnection structure, and it accounts for Area or region is had to be less than or are contained in occupied area or the region of each corresponding semiconductor tube core 24.

Fig. 2 A shows the temporary carrier or substrate 56 supported for structure, and it contains temporarily or sacrifice base material, such as silicon, Polymer, rustless steel or other suitable low cost rigid materials.Optional intermediate layer or two-sided tape 58 are as temporary bond film Or etching stopping layer is formed at above carrier 56.In one embodiment, carrier 56 can be to be included in adhesive tape periphery supporting adhesive tape The circular membrane framework of the open core of 58.Alternatively, as in figs. 2 a and 2b, carrier 56 can be Not having the flat board of open central area, this flat board supports adhesive tape 58 across the upper surface of carrier 56.Multiple benchmark alignment marks Can be positioned in or be attached on substrate 56 or intermediate layer 58, for semiconductor element 24 is appropriately positioned in carrier 56. Alternatively, the part in substrate 56 or intermediate layer 58 can be removed or labelling, to form benchmark.

Fig. 2 A also show the semiconductor element 24 from Fig. 1 E, and it is faced up and is installed to carrier 56 and intermediate layer 58, its back side 28 and insulating barrier 50 deviate from carrier orientation towards substrate orientation, active surface 30.Pickup and placement operation can be used Or other suitably operate the top that semiconductor element 24 is placed on carrier 36.Nominal or predetermined according to semiconductor element Position and spacing position semiconductor element 24 relative to benchmark 39.Semiconductor element 24 is installed to carrier 56 so that partly lead Body tube core is separated by space or gap 60 when being installed to above carrier 56, and this can be that the interconnection structure subsequently formed (is such as fanned Go out interconnection structure) provide a region as a part for final semiconductor package part.The size in gap 60 includes sufficiently large Region, for mounting semiconductor or parts alternatively in the semiconductor package part subsequently formed.

Fig. 2 B illustrates that sealant 62 is by slurry printing, compression molded, transmission molding, liquid sealant molding, lamination, very Dead level conjunction, spin coating or other suitable application devices deposition.Specifically, Fig. 2 B shows mould 64, its multiple sidewalls 66 with Top or top board 65, carrier 56 semiconductor element 24 in encapsulating mold together with intermediate layer 58 is used for encapsulation subsequently.Mould 64 may also include and carrier 56 are placed above and can contact the bottom of sidewall 66.In one embodiment, carrier 56 and intermediate layer 58 bottom mold portion that can be used as packaging technology subsequently.Alternatively, semiconductor element 24, carrier 56 and centre Layer 58 may be provided in the mould including some (such as, top and bottom).By moving mould around semiconductor element 24 Tool 64, or move in mould alternatively by by semiconductor element, mould 64 is got together.

Fig. 2 B also illustrates that mould 64 utilizes cavity or open space 70 to carry out encapsulating semiconductor tube core 24.Cavity 70 is at mould 64 And extend between semiconductor element 24 and intermediate layer 58.The certain volume that is provided above at semiconductor element 24 and carrier 56 Sealant 62.Entrance 68 can be the air vent that sealant 62 does not provides effusion path.Sealant 62 can be that polymer is combined Material, the epoxy resin such as with implant, the epoxy acrylate with implant or there is the polymerization of Suitable fillers Thing.Space requirement according to cavity 60 deducts by shared by semiconductor element 24 and any extra semiconductor device that may be present Region measure the volume of sealant 62.Sealant 62 is arranged on semiconductor element 24 over and around, and is arranged on Between two sidewalls 64.Sealant 62 may also be arranged on thick RDL trace 40 over and around so that utilizes identical sealant With sealant is arranged between the two or more thick RDL traces of RDL by packaging technology.Sealant 62 can be with thick RDL trace Sidewall contact so that single sealant 62 can directly contact semiconductor element 24 and thick RDL trace 40, and along transistor The side of core 24 and thick RDL trace 40 extends, thus is arranged on above side and the active surface of semiconductor element.

The top 65 of mould 64 can be moved along sidewall 66 towards sealant 62 and semiconductor element 24, until top contact seals Agent makes sealant 62 be uniformly dispersed and be uniformly distributed in the cavity 70 around semiconductor element 24.In order to cover equably The viscosity of the optional sealant 62 of lid and high temperature, such as, relatively low viscosity and high temperature can accelerate sealant in molding, slurry printing With flowing during spin coating.Also the temperature of sealant 62 can be controlled in cavity 70, to promote the solidification of sealant.Semiconductor element 24 are embedded in sealant 62, the most not only will not conduct electricity, but also protection semiconductor device is from external module in the environment And pollutant effects.

When using vacuum compression molding, sacrifice release film may be provided at the top 65 of cavity 70 and sidewall 66 with in cavity Sealant 62 between, to prevent sealant from adhering to or being attached to top and the sidewall of cavity.When using other kinds of molding Time (such as, transmission molding), it is convenient to omit sacrifice release film, and sealant 62 can contain releasing agent, or available releasing agent The inner surface of cavity 70 is processed, to prevent sealant to be attached to the inner surface of mould.

In fig. 2 c, being removed from mould 64 by semiconductor element 24, at this moment sealant 62 is as panel or embedded tube core Panel 72.Panel 72 optionally experiences solidification process, so that sealant 62 solidifies.Can pass through chemical etching, mechanical stripping, CMP, mechanical lapping, baking the affected part after applying some drugs, ultraviolet, laser scanning, wet stripping or other suitable technique remove carrier 56 and intermediate layer 58, thus expose the back surface 76 of the sealant relative with the front surface 78 of sealant 62.In one embodiment, at carrier 56, before intermediate layer 58 or both of which are removed, curing sealant 62 partially or completely.Alternatively, After carrier 56, intermediate layer 58 or both of which are removed, can curing sealant 62 partially or completely.

The back surface 76 of panel 72 can be substantially coplanar with the back surface 77 of insulating barrier 50.Back surface 76 and back surface 77 all may be used Expose by removing carrier 56 and intermediate layer 58.After removing carrier 56 and intermediate layer 58, Fig. 2 C illustrate sealant 62 around Semiconductor element 24 in embedded die panel 72 is arranged.Panel 72 can have occupied area or the shape of any shapes and sizes Shape factor, described shapes and sizes allow and are conducive to forming semiconductor package part institute as described in more detail below The subsequent treatment needed.As non-limitative example, the form factor that panel 72 can have is similar to 300 millimeters of (mm) semiconductor dies The form factor of circle, and there is the circular occupied area of a diameter of 300mm.Panel 72 also can have any other required chi Very little, and can have variously-shaped or form, such as rectangle or square.In one embodiment, panel 72 can be in this area Known restructuring wafer.

Fig. 2 C illustrates that panel 72 can use grinding machine 80 to be ground operation, removes surface to reduce the thickness of panel 72 78, and expose a part (such as, the surface 44 of RDL trace) for thick RDL trace 40, and expose sealant 62 or panel 72 New front surface 82, this front surface 82 is substantially coplanar with the surface 44 of RDL trace 40.It is also possible to use chemical etching to remove and grind A part for sealant 62 in surface plate 72.Therefore, RDL trace 40 energy of the contact pad 32 of semiconductor element 24 it is connected to Enough expose on the surface 82 of panel 72 relative to sealant 62, with in semiconductor element 24 and the semiconductor packages subsequently formed Electrical connection is provided between the multiple points outside part.Owing to reducing sealant to expose the thick RDL trace 40 that thickness is T1 The thickness of 62, therefore the thickness of the sealant 62 above the active surface 30 of semiconductor element 24 also can be equal to or the most first-class In thickness T1.The thickness being arranged on the insulating barrier 50 above semiconductor element 24 back surface 28 may be alternatively formed to and thickness T1 is equal or of substantially equal so that the thickness of the insulating barrier 50 being arranged on the back surface 28 of semiconductor element 24 can be with sealant The final thickness of 62 is similar or equal, and this sealant 62 is arranged on above active surface 30, thus offsets encapsulation power also Reduce warpage.

In the embodiment that a part for thick RDL trace 40 exposes by using grinding machine 80 to grind, thick RDL trace 40 Thickness is substantially equal to or is in the range of 15-35 μm or 20-30 μm.A part at thick RDL trace 40 is passed through to make In other embodiments exposed with laser ablation, as discuss about Fig. 5 A, the thickness of thick RDL trace 40 is smaller than The thickness of thickness RDL trace 40 when exposing thick RDL trace 40 by grinding.As a non-limitative example, when thick RDL trace 40 when exposing by laser ablation or other non-ground technique, and the thickness of thick RDL trace 40 is substantially equal to or is in In the range of 4-20 μm.As used herein, be substantially equal to may be included on the thickness of thick RDL trace 40 plus or deduct 1 μm, 2 μm or 3 μm, and the thickness less than 1 μm.

Fig. 2 D also show another embodiment, and wherein the semiconductor element 24 from Fig. 1 E is installed to carry by face down Body 56 and intermediate layer 58, its active surface 30 deviates from carrier orientation towards carrier orientation, the back side 28.Pickup can be used and place behaviour Make or other suitably operate the top that semiconductor element 24 is placed on carrier 56.When thick RDL trace 40 is at semiconductor element The top of 24 is formed and was connected to by thickness RDL trace 40 before being placed on by semiconductor element above carrier 36 or intermediate layer 38 During contact pad 32, semiconductor element 24 is probably favourable with the configuration installation of face down, and thickness T1 provides foot Enough side-play amounts, to allow to be arranged on by sealant 62 from the thick top surface 44 of RDL trace 40, the active table of semiconductor element 24 In top surface 37 initial thickness, height or the side-play amount of face 30 or insulating barrier 36.

Fig. 2 D also illustrates that mould 64 can use cavity 70 encapsulating semiconductor tube core 24, to be similar to above for described in Fig. 2 B Method use certain volume sealant 62 encapsulate semiconductor element 24.

In Fig. 2 E, being removed from mould 64 by semiconductor element 24, at this moment sealant 62 is as panel or embedded tube core Panel 92.Panel 72 can have occupied area or the form factor of any shapes and sizes, and described shapes and sizes allow and have It is beneficial to form the subsequent treatment needed for semiconductor package part as described in more detail below.As non-limiting example Son, the form factor that panel 72 can have is similar to the form factor of 300mm semiconductor crystal wafer, and has a diameter of 300mm's Circular occupied area.Panel 72 also can have any other required size, and can have variously-shaped or form, such as square Shape or square.In one embodiment, panel 72 can be restructuring wafer as known in the art.

Panel 92 optionally experiences solidification process, so that sealant 62 solidifies.Can pass through chemical etching, mechanical stripping, CMP, mechanical lapping, baking the affected part after applying some drugs, ultraviolet, laser scanning, wet stripping or other suitable technique remove carrier 56 and intermediate layer 58, thus expose the front surface 96 of the sealant relative with the back surface 98 of sealant 62.In one embodiment, at carrier 56, before intermediate layer 58 or both of which are removed, curing sealant 62 partially or completely.Alternatively, After carrier 56, intermediate layer 58 or both of which are removed, can curing sealant 62 partially or completely.

After removing carrier 56 and intermediate layer 58, Fig. 2 E illustrates that the front surface 96 of panel 92 can be with the surface of RLD trace 40 44 is substantially coplanar.Therefore, the RDL trace 40 of the contact pad 32 being connected to semiconductor element 24 can exist relative to sealant 62 Expose on the surface 96 of panel 92, with between the multiple points outside semiconductor element 24 and the semiconductor package part that subsequently forms Electrical connection is provided.

Fig. 2 E illustrates and grinding machine 80 can be used to make panel 92 experience grinding operation, removes table to reduce the thickness of panel 92 Face 98, and expose a part for the back surface 28 of semiconductor element 24.It is also possible to use chemical etching and remove and polish panel 72 In the part of sealant 62.The thickness reducing panel 92 can be carried out before or after removing carrier 56 and adhesive tape 58.? In some embodiments, sealant 62 directly can contact with the back surface 28 of semiconductor element 24, and is removing or grinding-in agent During retain sealant 62 thickness so that be provided above certain thickness sealant 62 at back surface 28.At some In embodiment, the thickness staying the sealant above back surface 28 can be equal or substantially equal to thickness T1, or is arranged on half The thickness of the sealant above the active surface 30 of conductor tube core.Therefore, the sealant above back surface 28 and active surface 30 Relative thickness can be equal or approximately equal, with balance power on the encapsulation opposite side subsequently formed, thus reduce or Warpage in littleization encapsulation.

Fig. 2 F illustrates that accumulation interconnection structure 106 can be formed, with semiconductor element 24 He above panel 72 or panel 92 There is provided between the RDL trace 44 and the multiple points outside the semiconductor package part subsequently formed that thicken and electrically connect.Therefore, exist subsequently Process shown in Fig. 2 F and Fig. 2 G can proceed by from the panel 72 being shown in Fig. 2 B and Fig. 2 C, or from being shown in Fig. 2 D and figure Panel 92 in 2E proceeds by.But, for convenience's sake, Fig. 2 F and Fig. 2 G is described relative to panel 72.Heap Long-pending interconnection structure 106 can include multiple RDL with RDL trace, and described RDL trace may be constructed of fan-out interconnection structure Point.Piling up interconnection structure 106 can be by various insulating barriers or the deposition of passivation layer and patterning, and the deposition of various conductive layer Formed with patterning.

Fig. 2 F shows the non-limitative example piling up interconnection structure, and wherein insulating barrier 108 is conformably applied to seal Agent 62 and the top surface 44 of thick RDL trace 42, and the first surface of insulating barrier 108 can be with sealant 62 and thick RDL trace 42 The profile of top surface 44 consistent.Insulating barrier 108 can have the flat surface of second relative with first surface.Insulating barrier 108 can wrap Actinodielectric resist containing one or more layers low solidification temperature, photosensitive compound resist, liquid crystal polymer (LCP), lamination Compound film, there is the insulation paste of implant, solder mask resist film, liquid mold compound, granular mold compound, polyamides Imines, benzocyclobutene (BCB), polybenzoxazoles (PBO), SiO2, Si3N4, SiON, Ta2O5, Al2O3 or have similar Insulating properties and the other materials of architectural characteristic.Available printing, spin coating, spraying, lamination or other suitable technique deposit Insulating barrier 108.Subsequently, UV exposure can be used to carry out the most again developing or other suitable techniques pattern and solidify insulating barrier 108.A part for insulating barrier 108 can be removed by laser ablation, etching or other suitable technique, thus according to quasiconductor The configuration of tube core 24 and design and final semiconductor package part, form the portion of the top surface 44 exposing thick RDL trace 42 The opening divided.

Conductive layer 110 can be patterned and be deposited on thick RDL trace 42, sealant 62 and the top of insulating barrier 108, and with They contact.Conductive layer 110 can be one or more layers Al, Cu, Sn, Ni, Au, Ag or other suitable conductive material, And can include in kind of a crystal layer, adhesive layer and barrier layer one or more.The deposition of conductive layer 110 may utilize PVD, CVD, electricity Electrolytic plating, electroless plating or other suitable technique.It is exhausted that opening in insulating barrier 108 can pass completely through above thick RDL trace 40 Edge layer extends.Conductive layer 110 can work as the RDL including multiple RDL trace, and the plurality of RDL trace contributes to being electrically connected Connect and extend to the multiple points outside semiconductor element 24 from semiconductor element 24 and thick RDL conductive trace 40.At insulating barrier 108 Opening in the part of conductive layer 110 that formed can form vertical interconnecting structure or through hole, thus provided by insulating barrier 108 It is electrically interconnected.And show the non-limitative example piling up interconnection structure 106 including single RDL 110 in fig. 2f, Pile up in interconnection structure 106, between conductive layer 114 and thick RDL 40, also can form additional RDL, thus be at transistor Between multiple points outside core 24 and semiconductor element 24, route signal provides extra motility.

Fig. 2 F also illustrates that insulating barrier or passivation layer 112 are conformably applied to insulating barrier 108 and conductive layer 110, and with absolutely Edge layer 108 is consistent with the profile of conductive layer 110.It is against corrosion that insulating barrier 112 can comprise one or more layers photosensitive low solidification temperature dielectric Agent, photosensitive compound resist, LCP, lamination compound film, there is the insulation paste of implant, solder mask resist film, liquid are moulded Seal compound, granular mold compound, polyimides, BCB, PBO, SiO2, Si3N4, SiON, Ta2O5, Al2O3 or there is class As insulating properties and the other materials of architectural characteristic.Available printing, spin coating, spraying, lamination or other suitable technique are come Depositing insulating layer 112.Subsequently, UV exposure can be used to carry out the most again developing or other suitable techniques pattern and solidify absolutely Edge layer 112.A part for insulating barrier 112 can be removed by laser ablation, etching or other suitable technique, to be formed through absolutely The opening of the some exposing conductive layer 110 of edge layer.

Conductive layer 114 can be patterned and be deposited on conductive layer 110 and the top of insulating barrier 112, and contacts with them. Conductive layer 114 can be one or more layers Al, Cu, Sn, Ni, Au, Ag or other suitable conductive material.Conductive layer 114 The available PVD of deposition, CVD, electrolysis plating, electroless plating or other suitable technique.Opening in insulating barrier 112 (wherein can set It is equipped with conductive layer 114) may extend entirely through the insulating barrier above conductive layer 110.Can be formed in the opening of insulating barrier 112 and lead Electric layer 114 at least some of, and form vertical interconnecting structure or through hole, thus provided by insulating barrier 112 and be electrically interconnected with even Receive conductive layer 110.

Conductive layer 114 can include top or the surface being formed as pad 116.Pad 116 can include horizontal part, these parts Area more than the area of the opening formed in insulating barrier 112 so that the pad 116 of conductive layer 114 is on the top of insulating barrier 112 Surface or upper surface extend above.The periphery of the semiconductor package part that the pad 116 of conductive layer 114 can be in defeated Enter/export (I/O) cross tie part.Therefore, pad 116 is formed as lower protruding block metallization (UBM) pad, as hereinafter relative to figure 2G has carried out more detailed description, may be formed at relative to semiconductor element 24 and encapsulation I/O interconnect transmission signal it Between interface.Alternatively, pad 116 is formed as land grid array (LGA) pad, and LGA pad itself can be The I/O cross tie part that semiconductor package part after being positioned at is peripheral, and it is free of attachment to other I/O cross tie parts, such as solder is convex Block.Pad 116 can be the stacking of the multiple metal levels including adhesive layer, barrier layer, kind crystal layer and wetting layer.Pad 116 can Including one or more layers Ti, titanium nitride (TiN), titanium tungsten (TiW), Al, Cu, chromium (Cr), chromium-copper (CrCu), Ni, nickel vanadium (NiV), Pd, platinum (Pt), Au, Ag or other suitable materials, or the combination of these materials.In one embodiment, pad 116 can include TiW kind crystal layer, Cu kind crystal layer and Cu UBM layer.

Fig. 2 G illustrates that conductive bump material can be deposited over above pad 116, as indicated above, and pad 116 Can be UBM pad, during it serves as between semiconductor element 24 and the solder projection subsequently formed or other I/O interconnection structures Between conductive layer.Pad 116 can include UBM pad, and this UBM pad provides the low resistance to conductive layer 110 and thick RDL trace 40 mutual Even, and also can be that solder diffusion provides barrier, increase the wettability of solder.Can use evaporation process, electrolytic plating process, Electroless plating, reflux technique or silk-screen printing technique by conductive bump material above pad 116.Bump material is permissible It is Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and a combination thereof, together with optional flux solution.Such as, bump material can To be eutectic Sn/Pb, high kupper solder or lead-free solder.Suitable attachment or adhesion technique can be used bump material to be adhered to Pad 116.In one embodiment, by bump material is heated to more than its fusing point make bump material reflux to form ball Shape ball or projection 118.In some applications, make projection 118 secondary back, thus improve the electrical contact of itself and pad 116.Also may be used Projection 118 compression is adhered to pad 116.Projection 118 represents a type of mutual link that can be formed above pad 116 Structure.It is used as other interconnection structures, including electrocondution slurry, stud bumps, miniature projection or other electrical interconnections.It addition, be Formation Quad Flat No-leads (QFN) encapsulation or land grid array (LGA) encapsulation, can omit projection 118.

After Fig. 2 G is also shown in I/O cross tie part (such as, the projection 116) formation of packaging part, saw blade or laser can be used Cutting tool 120 splits panel or restructuring wafer 72, to form independent semiconductor package part or embedded die package 122。

Fig. 3 is shown and is sealed by the single semiconductor packages manufactured by the technique shown in Figure 1A to Fig. 2 G or embedded tube core Fill 122.Therefore, the method shown in Figure 1A to Fig. 2 G and semiconductor packages 122 show a kind of method, in the method, thick RDL Layer may be included in the fan-in type packed structures being formed and being in contact with it above semiconductor crystal wafer or natural device wafers.Thick RDL layer Can include multiple RDL trace, these RDL traces (in z direction that is, are perpendicular to the active surface of semiconductor element and have away from this Surface, source extend direction) on thickness or height be at least 20 μm.Also can such as be reduced by grinding technics or thinning half Semiconductor wafer or the thickness of natural device wafers.Epoxy film (such as, solder mask laminate film or tube core attachment epoxy film) can be executed It is added to the back side of semiconductor crystal wafer.Can be by semiconductor crystal wafer dicing being formed single semiconductor element or from quasiconductor Wafer separates single semiconductor element.

Technique shown in the device of Fig. 3 and Figure 1A to Fig. 2 G also show and can be applied to carry by release film or release band temporarily Body or temporary substrates.Multiple semiconductor elements can be placed in heads carrier surface in the form of an array, the most partly lead The active surface of body tube core deviates from carrier orientation, or is positioned at the position of face down alternatively.It is installed to carry Other fan-out-type structure can be enough placed at the interval between semiconductor element on body, and this fan-out-type structure is partly led at final It is connected to semiconductor element when being formed in body encapsulation.The compressible plastic packaging of semiconductor element, with the front surface of semiconductor die Or at least four side surface of active surface and semiconductor element.Insulating barrier or dielectric film may be provided at the back of the body of semiconductor element On surface.The thickness of the film being arranged on the back surface of semiconductor element can be similar to or equal to being arranged on having of semiconductor element Surface, source or on sealant, epoxy mold compound or the final thickness of laminate film.Semiconductor element after sealing Plastic packaging panel can be formed, this plastic packaging panel can be made sealant cures after carrier removes.After solidification, sealant can be made solid Change, then this sealant polished or grind, to guarantee all to come out in the surface of all thick RDL traces.Subsequently can be Form fan-out-type RDL packed structures and soldered ball on plastic packaging panel, and this fan-out-type RDL packed structures and soldered ball are connected or be electrically connected Receive the RDL trace of thickening.In certain embodiments, in order to form QFN or LGA package, soldered ball or projection can be saved.As separately Outer a kind of selection, can be applied to above plastic packaging panel by solder mask (whether dry film or the solder mask of liquid film) or directly apply To the top of plastic packaging panel, and by this soldermask pattern to form opening, thus expose the required portion of fan-in type thickness RDL trace Divide or the required part of fan-out-type RDL packed structures, soldered ball or projection can be placed in the opening of solder mask after this.So After, by the segmentation of this panel or individual devices can be divided into saw.

By forming semiconductor packages as shown in Figure 3, final semiconductor packages can include active surface, and with single At least four side surface that individual mold compound seals.Also mold compound can be arranged on around thick RDL trace, work as quasiconductor When tube core is still natural semiconductor crystal wafer a part of, this thickness RDL trace can be formed on a semiconductor die and electroplate.Will Semiconductor element and thick RDL trace face up after being placed on temporary carrier, can this semiconductor element of plastic packaging and thick RDL mark Line.Thick RDL trace can be exposed by a part part for molding being ground or being removed molding, thus manufacture sealing Fan-in type encapsulation.Deposition fan removing from mould structure can be built subsequently at the fan-in type thickness RDL superstructure sealed.So, with use Structures and methods (needing the second material or single plastic packaging underfill) before are compared, it is only necessary to a step just may be used It is more easily accomplished sealing or plastic packaging process.It addition, by removing sealant when exposing thick RDL trace or sealant being ground To known thickness, it is achieved thereby that the good control to package thickness, so make it possible to the thickness by regulating epoxy resin Degree improves or optimizes the warpage of semiconductor packages.

By forming semiconductor packages as above, for subsequently semiconductor element being placed on temporary carrier, just Need not overturn semiconductor element after natural wafer dividing semiconductor tube core.Upset tube core is needed (to place by saving A part for journey) this step, can at faster speed and lower equipment cost completes the placement of semiconductor element.Due in envelope The cost that during dress semiconductor element, semiconductor element is placed is the most significant, therefore reduces semiconductor element in encapsulation process The cost placed can bring the most cost-effective advantage.Similarly, forming thick RDL trace can be by only using a kind of work Skill and structure are achieved with using kinds of processes and structure (such as forming independent redistributing layer and vertically interconnection (such as copper post)) The beneficial effect that could realize.It is therefore advantageous that fan-out-type semiconductor packages can be formed, wherein fan-out-type RDL is piled up knot Structure is fully applied to mold compound.Therefore, semiconductor device as herein described and method, thus can owing to having above-mentioned advantage By provide a kind of than traditional fan-out-type structure, there is the low cost of additional designs motility can manufacturing process, it is possible to can replace The encapsulation technology of large volume, such as QFN encapsulation and flip chip ball grid array (FBGA).

Fig. 4 shows the single semiconductor packages or embedded die package 130 that the semiconductor packages 122 with Fig. 3 is similar. Semiconductor packages 130 is with the difference of semiconductor packages 122, and semiconductor packages 130 includes piling up interconnection structure 132, And do not include piling up interconnection structure 106.Therefore, with continued reference to Fig. 2 C or Fig. 2 E, can be by thickness conduction RDL trace 40 and sealing Agent 62 disposed thereon insulating barrier 134 being in contact with it forms accumulation interconnection structure 132.Insulating barrier 134 conformally can be applied To sealant 62 and the top surface 44 of thick RDL trace 42, and insulating barrier 134 has and sealant 62 and thickness RDL trace 42 The first surface that the profile of top surface 44 is identical.Insulating barrier 134 can have the flat surface of second relative with first surface.Insulating barrier 134 can comprise one or more layers photosensitive low solidification temperature dielectric resist, photosensitive compound resist, LCP, lamination compound film, Have the insulation paste of implant, solder mask resist film, liquid mold compound, granular mold compound, polyimides, BCB, PBO, SiO2, Si3N4, SiON, Ta2O5, Al2O3 or there is the other materials of similar insulating properties and architectural characteristic. Available printing, spin coating, spraying, lamination or other suitable technique carry out depositing insulating layer 134.Subsequently, UV exposure can be used so After carry out again developing or other suitable techniques pattern and solidify insulating barrier 134.Can pass through laser ablation, etching or other Suitably technique removes a part for insulating barrier 134, thus the configuration and design according to semiconductor packages 130 forms exposure The opening of the top surface 44 of thick RDL trace 42.In one embodiment, insulating barrier 134 can be organic passivation film or inorganic blunt Changing film, this film can help to prevent from losing reliability under electrical bias.

Fig. 4 also illustrates that and conductive bump material can be arranged on the top of thick conduction RDL trace 40 and be in direct contact with it.Can Use evaporation process, electrolytic plating process, electroless plating, reflux technique or silk-screen printing technique by conductive bump material Above pad 116.Bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and a combination thereof, together with optional weldering Agent solution is together.Such as, bump material can be eutectic Sn/Pb, high kupper solder or lead-free solder.Can use suitably attachment or Bump material is adhered to thick conduction RDL trace 40 by adhesion technique.In one embodiment, by bump material is heated to More than its fusing point make bump material backflow to form spherical ball or projection 136.In some applications, projection 136 secondary returning is made Stream, thus improve the electrical contact of itself and thick conduction RDL trace 40.Projection 136 compression also can be adhered to thick conduction RDL trace 40.Projection 136 represents a type of interconnection structure that can be formed above thickness conduction RDL trace 40.It is used as other mutual Link structure, including electrocondution slurry, stud bumps, miniature projection or other electrical interconnections.

Fig. 5 A to Fig. 5 D shows another embodiment of the method manufacturing the semiconductor packages comprising thick conduction RDL trace. Showing with continued reference to Fig. 2 B, Fig. 5 A and removed from mould 64 by semiconductor element 24, wherein sealant 62 is as panel or embedding Formula die panel 142.Panel 142 optionally experiences solidification process, so that sealant 62 solidifies.The back surface 146 of panel 142 Can be made up of the back surface 77 of the back surface 146 of sealant 62 and insulating barrier 50, wherein back surface 146 and back surface 77 relative to It is mutually substantially coplanar.Can be by removing carrier 56 and intermediate layer 58 exposes back surface 146 and the insulating barrier 50 of sealant 62 Back surface 77, as shown in Figure 5 B.As shown in Figure 5A, half sealant 62 can be arranged in embedded die panel 142 Around conductor tube core 24.Panel 142 can have occupied area or the form factor of any shapes and sizes, described shapes and sizes Allow and be conducive to forming the subsequent treatment needed for semiconductor package part as described in more detail below.As non-limit Property example processed, the form factor that panel 142 can have is similar to the form factor of 300mm semiconductor crystal wafer, and has a diameter of The circular occupied area of 300mm.Panel 142 also can have any other required size, and can have variously-shaped or shape Formula, such as rectangle or square.In one embodiment, panel 142 can be restructuring wafer as known in the art.

Fig. 5 A shows and grinding machine 150 can be used to make panel 142 experience grinding operation, to reduce the thickness of panel 142 and to move Remove or polish the front surface 148 of sealant 62.It is also possible to use chemical etching and remove and polish sealant 62 in panel 142 A part.Through grinding operation, sealant 62 can manufacture or manifest new front surface 152, and this surface configuration is on thick RDL trace 40 Side.New front surface 152 can be manifested by removing the thickness T3 of sealant 62 from the front surface 148 of sealant.Front surface 152 can Thickness or the distance of T4 is offset from the surface 44 of RDL trace 40.Alternatively, it is substantially equal to as desired thickness T4 When the thickness between front surface 148 controlled during trace 40 and plastic packaging or side-play amount, the thickness T4 of sealant can keep base Before this is identical, and grinding operation or chemical etching can be by polishing in the case of the basic thickness T4 not removing sealant 62 Surface 148, the thickness after making thickness T4 be substantially equal to plastic packaging.

Fig. 5 B show can pass through chemical etching, mechanical stripping, CMP, mechanical lapping, baking the affected part after applying some drugs, ultraviolet, laser scanning, Wet stripping or other suitable technique remove carrier 56 and intermediate layer 58 from panel 142, thus expose and before sealant 62 The back surface 146 of the sealant that surface 148 is relative.In one embodiment, at carrier 56, intermediate layer 58 or both of which quilt Before removing, curing sealant 62 partially or completely.Alternatively, carrier 56, intermediate layer 58 or this two After person is all removed, can curing sealant 62 partially or completely.Similarly, can grind or before polishing sealant 62 or Remove carrier 56 and intermediate layer 58 afterwards.

It is further illustrated in Fig. 5 B, laser ablation, etching or other suitable technique (such as, non-ground works can be passed through Skill) in the front surface 148 or front surface 152 of sealant 62, form opening 156.Opening 156 may extend entirely through sealant The part of 62, to expose at least some of (such as, the surface 44 of thick RDL trace) of thick RDL trace 40, thus contribute to After be electrically interconnected.Opening 156 can form sidewall 158 straight, bending, inclination or angled.Correspondingly, opening 156 Sidewall 158 also can be perpendicular to or be substantially perpendicular to front surface 148 or front surface 152 is formed.Opening 156 can have at panel The one or more width extended along x and y direction in the surface 152 of 142 or diameter W1.The shape of cross section of opening 156 can be Circular, oval, square, rectangle or any other shape, including elongated channels.The height of opening or sidewall 158 can be more than, Width W1 equal to or less than opening.In one embodiment, before making sealant 62 solidification, and carrier can removed 56, intermediate layer 58 or both before formed opening 156.Alternatively, after can solidifying making sealant 62, and And remove carrier 56, intermediate layer 58 or both after formed opening 156.By laser ablation or other non-ground works Skill makes in the embodiment that a part for thick RDL trace 40 exposes, and the thickness of thick RDL trace 40 is smaller than making thick RDL by grinding The thickness of thickness RDL trace 40 when trace 40 exposes.As a limiting examples, when by laser ablation or other non-ground When technique makes thick RDL trace 40 expose, the thickness of thick RDL trace 40 can include or be substantially equal to 4-20 μm, 4-15 μm, 4-10 Thickness in μm or 4-5 μ m.As used herein, it is substantially equal to can include adding and subtracting 1 μm, 2 μm or 3 μm, and less than 1 μ m。

Fig. 5 C show can be formed above panel 142 accumulation interconnection structure 160, with semiconductor element 24, thicken Electrical connection is provided between RDL trace 44 and the multiple points outside semiconductor packages that subsequently form.Piling up interconnection structure 160 can Including having multiple RDL of RDL trace, described RDL trace may be constructed a part for fan-out interconnection structure.Pile up interconnection structure 160 can by various insulating barriers or the deposition of passivation layer and patterning, and the deposition of various conductive layer and patterning formed.

Fig. 5 C shows the limiting examples piling up interconnection structure 160, is wherein conformally applied to close by insulating barrier 162 Envelope agent 62 and the top surface 44 of thick RDL trace 42, and insulating barrier 162 has and sealant 62 and the top table of thickness RDL trace 42 The first surface that the profile in face 44 is identical.Insulating barrier 162 can have the flat surface of second relative with first surface.Insulating barrier 162 One or more layers photosensitive low solidification temperature dielectric resist, photosensitive compound resist, LCP, lamination compound film can be comprised, have The insulation paste of implant, solder mask resist film, liquid mold compound, granular mold compound, polyimides, BCB, PBO, SiO2, Si3N4, SiON, Ta2O5, Al2O3 or there is the other materials of similar insulating properties and architectural characteristic.Can profit Depositing insulating layer 162 is carried out by printing, spin coating, spraying, lamination or other suitable technique.Subsequently, UV can be used to expose the most again Carry out developing or other suitable techniques pattern and solidify insulating barrier 162.Laser ablation, etching can be passed through or other are suitable Technique remove the part of insulating barrier 162, thus according to the configuration of semiconductor element 24 and design and final partly leading Body packaging part, forms the opening of the part of the top surface 44 exposing thick RDL trace 42.In certain embodiments, can seal Formed or insulating barrier 162 is set before agent 62 forms opening 158 so that opening is also cross insulating barrier 162 and sealant 62 And formed wherein.Alternatively, can be formed after forming opening 158 in sealant 62 or insulating barrier is set 162 so that the opening in insulating barrier extends only through insulating barrier and formed, and extend to the surface 44 of thick RDL trace 40.Conductive layer 164 Can be patterned and be deposited on thick RDL trace 42, sealant 62 and the top of insulating barrier 162, and contact with them.Conductive layer 164 can be one or more layers Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials, and can include kind of a crystal layer, One or more in adhesive layer and barrier layer.The deposition of conductive layer 164 may utilize PVD, CVD, electrolysis plating, electroless plating or its His suitable technique.The insulating barrier that opening in insulating barrier 162 can pass completely through above thick RDL trace 40 extends.Conductive layer 164 Can work as the RDL including multiple RDL trace, the plurality of RDL trace contributes to electrical connection from semiconductor element 24 He Thick RDL conductive trace 40 extends to the multiple points outside semiconductor element 24.The conduction formed in the opening of insulating barrier 162 A part for layer 164 can form vertical interconnecting structure or through hole, thus provided by insulating barrier 162 and be electrically interconnected.Although Fig. 2 C shows Go out to include the limiting examples piling up interconnection structure 160 of single RDL 164, but also can be in conductive layer 168 and thickness Extra RDL is formed, with outside semiconductor element 24 and this semiconductor element in accumulation interconnection structure 160 between RDL 40 Multiple points between for route signal provide additional flexibility.

Fig. 5 C also illustrates that insulating barrier or passivation layer 166 are conformably applied to insulating barrier 162 and conductive layer 164, and with absolutely Edge layer 108 is consistent with the profile of conductive layer 110.It is against corrosion that insulating barrier 166 can comprise one or more layers photosensitive low solidification temperature dielectric Agent, photosensitive compound resist, LCP, lamination compound film, there is the insulation paste of implant, solder mask resist film, liquid are moulded Seal compound, granular mold compound, polyimides, BCB, PBO, SiO2, Si3N4, SiON, Ta2O5, Al2O3 or there is class As insulating properties and the other materials of architectural characteristic.Available printing, spin coating, spraying, lamination or other suitable technique are come Depositing insulating layer 166.Subsequently, UV exposure can be used to carry out the most again developing or other suitable techniques pattern and solidify absolutely Edge layer 166.A part for insulating barrier 166 can be removed by laser ablation, etching or other suitable technique, to be formed through absolutely The opening of the some exposing conductive layer 164 of edge layer.

Conductive layer 168 can be patterned and be deposited on conductive layer 164 and the top of insulating barrier 166, and contacts with them. Conductive layer 168 can be one or more layers Al, Cu, Sn, Ni, Au, Ag or other suitable conductive material.Conductive layer 168 The available PVD of deposition, CVD, electrolysis plating, electroless plating or other suitable technique.Opening in insulating barrier 166 (is provided with Have conductive layer 168) may extend entirely through the insulating barrier above conductive layer 164.Conduction can be formed in the opening of insulating barrier 166 Layer 168 at least some of, and is formed vertical interconnecting structure or through hole, thus is provided by insulating barrier 166 and be electrically interconnected to connect To conductive layer 164.

Conductive layer 168 can include top or the surface being formed as pad 170.Pad 170 can include horizontal part, these parts Area more than the area of the opening formed in insulating barrier 166 so that the pad 170 of conductive layer 168 is on the top of insulating barrier 166 Surface or upper surface extend above.The pad 170 of conductive layer 168 can be I/O cross tie part, the semiconductor packages after being positioned at Peripheral.So, pad 170 is formed as UBM pad or LGA pad, and these pads are connected to the semiconductor package after being positioned at The I/O cross tie part that dress is peripheral, such as solder projection.Or alternatively, pad 170 itself can be I/O interconnection Part.Pad 170 can be the stacking of the multiple metal levels including adhesive layer, barrier layer, kind crystal layer and wetting layer.Pad 170 can Including one or more layers Ti, TiN, TiW, Al, Cu, Cr, CrCu, Ni, NiV, Pd, Pt, Au, Ag or other suitable materials, or The combination of these materials of person.In one embodiment, pad 170 can include TiW kind crystal layer, Cu kind crystal layer and Cu UBM layer.

Fig. 5 D illustrates that conductive bump material can be deposited over above pad 170, as indicated above, and pad 116 Can be UBM pad, during it serves as between semiconductor element 24 and the solder projection subsequently formed or other I/O interconnection structures Between conductive layer.Pad 170 can include UBM pad, and this UBM pad is formed and is connected to conductive layer 164 and the low electricity of thick RDL trace 40 Resistance cross tie part, and also can be that solder diffusion provides barrier and increases the wettability of solder.Evaporation process, electrolysis plating can be used Technique, electroless plating, reflux technique or silk-screen printing technique by conductive bump material above pad 170.Projection material Material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and a combination thereof, together with optional flux solution.Such as, projection Material can be eutectic Sn/Pb, high kupper solder or lead-free solder.Suitable attachment or adhesion technique can be used bump material It is adhered to pad 170.In one embodiment, by bump material is heated to more than its fusing point make bump material backflow with Form spherical ball or projection 172.In some applications, make projection 172 secondary back, thus improve its electricity with pad 170 and connect Touch.Also projection 172 compression can be adhered to pad 170.It is a type of that projection 172 representative can be formed above pad 170 Interconnection structure.It is used as other interconnection structures, including electrocondution slurry, stud bumps, miniature projection or other electrical interconnections.

After Fig. 5 D is also shown in I/O cross tie part (such as, the projection 170) formation of packaging part, saw blade or laser can be used Cutting tool 174 splits panel or restructuring wafer 142, to form independent semiconductor package part or embedded die package 176.Fig. 6 shows by the single semiconductor packages manufactured by the technique shown in Fig. 5 A to Fig. 5 D or embedded die package 176。

Fig. 7 shows the single semiconductor packages or embedded die package 180 that the semiconductor packages 176 with Fig. 6 is similar. Semiconductor packages 180 is different from semiconductor packages 176, eliminates accumulation interconnection structure 160.But encapsulation 180 includes sealant 182, this sealant includes back surface 184 and the front surface 186 relative with back surface.Back surface 184 and front surface 186 can It is substantially flat, and this back surface also can be substantially coplanar with the back surface 77 of insulating barrier 50.The front table of sealant 182 Surface 44 1 segment distance of thick RDL trace 40 can be deviateed in face 186 so that the thickness T5 of sealant 182 can be before sealant 182 Surface 186 extends to the surface 44 of thick RDL trace 40.

As further shown in Figure 7, laser ablation, etching or other suitable technique can be passed through through sealant 182 Front surface 186 forms multiple opening 188 in sealant 182.Opening 188 may extend entirely through a part for sealant 182, To expose at least some of (such as, the surface 44 of thick RDL trace) of thick RDL trace 40, thus contribute to carrying out electricity subsequently mutually Even.Opening 188 can form sidewall straight, bending, inclination or angled.Correspondingly, the sidewall of opening 188 also can be vertical In or be substantially perpendicular to front surface 186 and formed.Opening 188 can have in the front surface 186 of semiconductor packages 180 along x and y One or more width of direction extension or diameter W2.The shape of cross section of opening 188 can be circular, oval, square, rectangle Or any other shape, including elongated channels.The height of opening 188 can greater than, equal to or less than the width W2 of opening.One In individual embodiment, before can solidifying making sealant 182 or fully solidifying, and from semiconductor packages 24 and sealant 182 Remove carrier, intermediate layer or formation opening 188 before both.Alternatively, can be solidified it making sealant 182 After, and remove carrier, intermediate layer or both after formed opening 188.The size and dimension of opening 188 can be configured For being suitable to receive or docking conductive lug structure, as described in greater detail below.So, the size of opening 188, volume or transversal Area can be more than the size of opening 156, volume or the cross-sectional area shown in Fig. 5 B to Fig. 5 D.

Fig. 7 also show and conductive bump material can be arranged on the top of thick RDL trace 40 and be in contact with it.Steaming can be used Conductive bump material is arranged on thickness by depositing process, electrolytic plating process, chemical plating process, reflux technique or silk-screen printing technique Above RDL trace 40.Bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and a combination thereof, together with optional weldering Agent solution is together.Such as, bump material can be eutectic Sn/Pb, high kupper solder or lead-free solder.Can use suitably attachment or Bump material is adhered to thick RDL trace 40 by adhesion technique.In one embodiment, melt by bump material is heated to it Point is above makes bump material backflow to form spherical ball or projection 190.In some applications, make projection 190 secondary back, from And improve the electrical contact of itself and thick RDL trace 40.Projection 190 compression also can be adhered to thick RDL trace 40.Projection 190 represents The a type of interconnection structure that can be formed above thick RDL trace 40.It is used as other interconnection structures, including conductive paste Material, stud bumps, miniature projection or other electrical interconnections.

Fig. 8 shows the single semiconductor packages or embedded die package 194 that the semiconductor packages 180 with Fig. 7 is similar. Semiconductor packages 194 is different from semiconductor packages 180, eliminates insulating barrier 50.Fig. 8 shows and back surface 28 can expose as half A part for conductor encapsulation 194, and not there is the insulating barrier 50 being arranged on above the back surface 28 of semiconductor element 24.Quasiconductor Encapsulation 194 includes sealant 196, and this sealant includes back surface 198 and the front surface 200 relative with back surface.Back surface 198 Can be substantially flat with front surface 200, and this back surface also can be basic with the back surface 28 of semiconductor element 24 Upper coplanar.The front surface 200 of sealant 196 can deviate surface 44 1 segment distance of thick RDL trace 40 so that sealant 196 Thickness T6 can extend to the surface 44 of thick RDL trace 40 from the front surface 200 of sealant 196.

As further shown in Figure 8, laser ablation, etching or other suitable technique can be passed through through sealant 196 Front surface 200 forms multiple opening 202 in sealant 196.Opening 202 may extend entirely through a part for sealant 196, To expose at least some of (such as, the surface 44 of thick RDL trace) of thick RDL trace 40, thus contribute to carrying out electricity subsequently mutually Even.Opening 202 can form sidewall straight, bending, inclination or angled.Correspondingly, the sidewall of opening 202 also can be vertical In or be substantially perpendicular to front surface 200 and formed.Opening 202 can have in the front surface 200 of semiconductor packages 194 along x and y One or more width of direction extension or diameter W3.The shape of cross section of opening 202 can be circular, oval, square, rectangle Or any other shape, including elongated channels.The height of opening 202 can greater than, equal to or less than the width W3 of opening.One In individual embodiment, before can solidifying making sealant 196 or fully solidifying, and from semiconductor packages 24 and sealant 196 Remove carrier 56, intermediate layer 58 or formation opening 202 before both.Alternatively, sealant 196 can be made solid After change, and remove carrier, intermediate layer or both after formed opening 202.The size and dimension of opening 202 can quilt It is configured and adapted to receive or docking conductive lug structure, as described in greater detail below.So, the size of opening 202, volume or Cross-sectional area can be more than the size of opening 156, volume or the cross-sectional area shown in Fig. 5 B to Fig. 5 D.

Fig. 8 also show and conductive bump material can be arranged on the top of thick RDL trace 40 and be in contact with it.Steaming can be used Conductive bump material is arranged on thickness by depositing process, electrolytic plating process, chemical plating process, reflux technique or silk-screen printing technique Above RDL trace 40.Bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and a combination thereof, together with optional weldering Agent solution is together.Such as, bump material can be eutectic Sn/Pb, high kupper solder or lead-free solder.Can use suitably attachment or Bump material is adhered to thick RDL trace 40 by adhesion technique.In one embodiment, melt by bump material is heated to it Point is above makes bump material backflow to form spherical ball or projection 204.In some applications, make projection 204 secondary back, from And improve the electrical contact of itself and thick RDL trace 40.Projection 204 compression also can be adhered to thick RDL trace 40.Projection 204 represents The a type of interconnection structure that can be formed above thick RDL trace 40.It is used as other interconnection structures, including conductive paste Material, stud bumps, miniature projection or other electrical interconnections.

Fig. 9 shows the single semiconductor packages or embedded die package 208 that the semiconductor packages 194 with Fig. 8 is similar. Semiconductor packages 208 is different from semiconductor packages 194, including insulating barrier or passivation layer 210.Insulating barrier 210 can be epoxy film, Heat conductivity epoxy resin, epoxy resin, the epoxy film of B-staged, there are the UV-B rank of optional acrylic polymer Film, dielectric film or other suitable materials.Insulating barrier 210 can be arranged on the most whole back side of semiconductor packages 208 Side, therefore the occupied area of insulating barrier 210 is substantially equal to the occupied area of semiconductor packages 208 rather than such as Fig. 6 and Tu The semiconductor packages of 7 is substantially equal to the less occupied area of semiconductor element 24 area like that.Insulating barrier 210 can include back of the body table Face 212 and the front surface 214 relative with back surface.Back surface 212 and front surface 214 can be substantially flat, and should Front surface also can be substantially coplanar with the back surface 28 of the back surface 198 of sealant 196 and semiconductor element 24.

Figure 10 shows the single semiconductor packages or embedded die package that the semiconductor packages 180 with Fig. 7 is similar 218.Semiconductor packages 218 is different from semiconductor packages 194, and including insulating barrier or passivation layer 220, this insulating barrier or passivation layer can Including the first flat surface, this first surface is conformally applied to the front surface 200 of sealant 196 and directly contacts sealant 196 Front surface 200.Insulating barrier 220 can have the flat surface of second relative with first surface.Insulating barrier 220 can comprise one layer or many Layer photosensitive low solidification temperature dielectric resist, photosensitive compound resist, LCP, lamination compound film, have implant insulation slurry Material, solder mask resist film, liquid mold compound, granular mold compound, polyimides, BCB, PBO, SiO2, Si3N4, SiON, Ta2O5, Al2O3 or there is the other materials of similar insulating properties and architectural characteristic.Available printing, spin coating, spray Painting, lamination or other suitable technique carry out depositing insulating layer 220.Subsequently, UV exposure can be used to carry out the most again developing or other Suitably technique patterns and solidifies insulating barrier 220.In one embodiment, insulating barrier 220 can be organic passivation film or Inorganic passivating film, formed this film above sealant 196 by laser boring before forming opening 222, thus contributes to Prevent from losing reliability under electrical bias.

Laser ablation, etching or other the suitable technique front surface 186 through sealant 182 can be passed through at insulating barrier 220 and sealant 182 in formed opening 222.Opening 222 may extend entirely through of insulating barrier 220 and sealant 182 Point, to expose at least some of (such as, the surface 44 of thick RDL trace) of thick RDL trace 40, thus contribute to carrying out subsequently electricity Interconnection.Opening 220 can form sidewall straight, bending, inclination or angled.Correspondingly, the sidewall of opening 220 also can hang down Directly in or be substantially perpendicular to front surface 186 and formed.Opening 220 can have in the front surface 186 of semiconductor packages 218 along x The one or more width extended with y direction or diameter W4.The shape of cross section of opening 222 can be circular, oval, square, Rectangle or any other shape, including elongated channels.The height of opening 222 can greater than, equal to or less than the width W2 of opening. In one embodiment, before can solidifying making sealant 182 and insulating barrier 220 or fully solidifying, and from semiconductor package Fill 24 and sealant 182 remove carrier, intermediate layer or both before formed opening 222.Alternatively, can make Sealant 182 and insulating barrier 220 solidification after, and remove carrier, intermediate layer or both after formation opening 222. The size and dimension of opening 222 can be configured to be suitable to receive or docking conductive lug structure, as described in greater detail below.This Sample, the size of opening 222, volume or cross-sectional area can be more than the size of opening 156 shown in Fig. 5 B to Fig. 5 D, volume or transversal Area.

Figure 10 also show and conductive bump material can be arranged on thick RDL trace 40, sealant 182 and insulating barrier 220 Top is also in contact with it.Evaporation process, electrolytic plating process, chemical plating process, reflux technique or screen printing dataller can be used Conductive bump material is arranged on above thick RDL trace 40 by skill.Bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, Solder and a combination thereof, together with optional flux solution.Such as, bump material can be eutectic Sn/Pb, high kupper solder or nothing Kupper solder.Can use suitably attachment or adhesion technique that bump material is adhered to thick RDL trace 40.An embodiment In, make bump material backflow to form spherical ball or projection 224 by bump material is heated to more than its fusing point.At some In application, make projection 224 secondary back, thus improve the electrical contact of itself and thick RDL trace 40.Also can projection 224 be compressed viscous Close thick RDL trace 40.Projection 224 represents a type of interconnection structure that can be formed above thick RDL trace 40.Also can make Use other interconnection structures, including electrocondution slurry, stud bumps, miniature projection or other electrical interconnections.

Figure 11 shows the single semiconductor packages or embedded die package that the semiconductor packages 180 with Fig. 7 is similar 225.Semiconductor packages 225 is different from conductor encapsulation 180, and including conductive interconnection part 226, this conductive interconnection part is thick RDL 40 He Extend between multiple points outside semiconductor packages 225 and provide electrical interconnection to connect.Can be formed in opening 228 at least in part Conductive interconnection part 226.Laser ablation, etching or other the suitable technique front surface 186 through sealant 182 can be passed through close Envelope agent 182 forms opening 228.Opening 228 may extend entirely through a part for sealant 182, to expose thick RDL trace 40 At least some of (such as, the surface 44 of thick RDL trace), thus contribute to being electrically interconnected subsequently.Opening 228 can be formed directly , bending, tilt or angled sidewall.Correspondingly, before the sidewall of opening 228 also can be perpendicular to or be substantially perpendicular to Surface 186 is formed.Opening 220 can have or many extended in the front surface 186 of semiconductor packages 225 along x and y direction Individual width or diameter W5.The shape of cross section of opening 228 can be circular, oval, square, rectangle or any other shape, Including elongated channels.The height of opening 228 can greater than, equal to or less than the width W5 of opening.In one embodiment, opening The height of 228 is more than its width so that the conductive interconnection part 226 formed in opening 228 is configured to height more than width W5's Conductive pole.The height of conductive interconnection part 226 can be in 20-100 μ m or be substantially equal to 20-100 μm.An embodiment In, can solidify making sealant 182 or fully solidification before, and from semiconductor packages 24 and sealant 182 remove carrier, Intermediate layer or both before formed opening 228.Alternatively, after can solidifying making sealant 182, and Remove carrier, intermediate layer or formation opening 228 after both.

Also can form conductive interconnection part 226 so that a part for conductive interconnection part 226 is formed as pad 227.Pad 227 Can be adjacent with the front surface 186 of sealant 182, and its area is more than width W5 more than the area of opening 228, its width, makes The pad 227 obtaining conductive interconnection part 226 extends above at top surface or the upper surface of sealant 182 front surface 186.Conductive interconnection The pad 227 of part 226 can be I/O cross tie part, and the semiconductor packages after being positioned at is peripheral.Therefore, pad 227 is formed as UBM pad (is described in more detail), can relative to semiconductor element 24 and encapsulation I/O cross tie part transmission signal it Between formed interface.Alternatively, pad 227 is formed as LGA pad, and LGA pad can be in itself After the peripheral I/O cross tie part of semiconductor package part, and be free of attachment to other I/O cross tie part, such as solder projections.Pad 227 can be the stacking of the multiple metal levels including adhesive layer, barrier layer, kind crystal layer and wetting layer.Pad 227 can include one layer Or multilamellar Ti, TiN, TiW, Al, Cu, Cr, CrCu, Ni, NiV, Pd, Pt, Au, Ag or other suitable materials, or these materials The combination of material.In one embodiment, pad 227 can include TiW kind crystal layer, Cu kind crystal layer and Cu UBM layer.

Figure 11 also show conductive bump material can be arranged on sealant 182 and the top of conductive interconnection part 226 and with Its contact.Evaporation process, electrolytic plating process, chemical plating process, reflux technique or silk-screen printing technique can be used to conduct electricity Bump material is arranged on above conductive interconnection part 226.Bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and A combination thereof, together with optional flux solution.Such as, bump material can be eutectic Sn/Pb, high kupper solder or Pb-free coating Material.Can use suitably attachment or adhesion technique that bump material is adhered to conductive interconnection part 226.In one embodiment, Make bump material backflow to form spherical ball or projection 230 by bump material is heated to more than its fusing point.Should at some In with, make projection 230 secondary back, thus improve the electrical contact of itself and conductive interconnection part 226.Also can projection 230 be compressed viscous Close conductive interconnection part 226.Projection 230 represents a type of interconnection structure that can be formed above conductive interconnection part 226.Also Other interconnection structures can be used, including electrocondution slurry, stud bumps, miniature projection or other electrical interconnections.

Figure 12 shows the single semiconductor packages or embedded die package that the semiconductor packages 225 with Figure 11 is similar 234.Semiconductor packages 234 is different from semiconductor packages 225, and including insulating barrier or passivation layer 236, this insulating barrier or passivation layer can Including the first flat surface, this first surface is conformally applied to the front surface 186 of sealant 182 and directly contacts sealant 196 Front surface 200.Insulating barrier 236 can have the flat surface of second relative with first surface.Insulating barrier 236 can comprise one layer or many Layer photosensitive low solidification temperature dielectric resist, photosensitive compound resist, LCP, lamination compound film, have implant insulation slurry Material, solder mask resist film, liquid mold compound, granular mold compound, polyimides, BCB, PBO, SiO2, Si3N4, SiON, Ta2O5, Al2O3 or there is the other materials of similar insulating properties and architectural characteristic.Available printing, spin coating, spray Painting, lamination or other suitable technique carry out depositing insulating layer 236.Subsequently, UV exposure can be used to carry out the most again developing or other Suitably technique patterns and solidifies insulating barrier 236.In one embodiment, insulating barrier 236 can be organic passivation film or Inorganic passivating film, formed this film above sealant 182 by laser boring before forming opening 228, thus contributes to Prevent from losing reliability under electrical bias.In other embodiments, opening 228 can be formed before insulating barrier 236 is formed.

Otherwise, opening 228, conductive interconnection part 226, pad 227 and projection 230 can be with the encapsulation 225 described in Figure 11 above Appropriate section identical or essentially identical.

In the foregoing specification, it has been described that the various embodiments of the disclosure.But it will be apparent that without departing from appended On the premise of the present invention described in claims widely spirit and scope, these embodiments can be carried out various amendment And change.Therefore, the specification and drawings should be considered descriptive sense and non-limiting sense.

Claims

1. the method manufacturing semiconductor packages, including:

Forming multiple thick redistributing layer (RDL) trace above the active surface of multiple semiconductor elements, the plurality of thickness is divided again Layer of cloth trace is electrically connected to the contact pad on the plurality of semiconductor element；

Segmentation includes the plurality of semiconductor element of the plurality of thick redistributing layer trace；

The plurality of semiconductor element of segmentation is arranged on the top of temporary carrier, the institute of wherein said multiple semiconductor elements State active surface and deviate from described temporary carrier orientation；

The described active surface of each sealant material being arranged in the plurality of semiconductor element and at least four side Above surface, the plurality of thick redistributing layer trace and above described temporary carrier；

Form the through hole through described sealant material, to expose the redistribution of the multiple thickenings relative to described sealant material At least one trace in layer trace；

Remove described temporary carrier；And

Split the plurality of semiconductor element.

Method the most according to claim 1, also includes:

Form the plurality of thick redistributing layer trace that there is thickness or height more than 5 microns；And

Utilizing laser ablation to form the described through hole through described sealant material, wherein said sealant material is a kind of non-light Cause image forming material.

Method the most according to claim 2, is additionally included in the occupied area of each corresponding described semiconductor element, pin The plurality of thick redistributing layer trace is formed as fan-in type structure by each in the plurality of semiconductor element.

Method the most according to claim 3, also includes:

Forming the electrical interconnection being connected at least one trace thickeied, wherein said electrical interconnection extends to described semiconductor package The outside of dress；And

Described electrical interconnection is formed as enclosure cavity (UBM) pad, land grid array (LGA) pad, four flat nothings are drawn Line (QFN) pad or projection.

Method the most according to claim 4, also includes described electrical interconnection is directly attached to the plurality of thick redistribution Layer trace.

Method the most according to claim 4, is additionally included in the plurality of semiconductor element relative with described active surface The back side on form back side epoxy coating or dielectric film.

7. the method manufacturing semiconductor packages, including:

Forming multiple thick redistributing layer (RDL) trace above the active surface of semiconductor element, the plurality of thick RDL trace is even Receive the contact pad on the described active surface of described semiconductor element；

Sealant material is arranged on above the described active surface of described semiconductor element and at least four side surface and described Above multiple thick redistributing layer traces；

Expose relative at least one trace in the RDL trace of the plurality of thickening of described sealant material；And

Form the electrical interconnection being connected at least one trace thickeied described.

Method the most according to claim 7, also includes:

Laser ablation is utilized to form the through hole through described sealant material, to expose relative to described in described sealant material At least one trace in the redistributing layer trace of multiple thickenings, wherein said sealant material is a kind of non-photo-imaging material Material.

Method the most according to claim 8, also includes:

Form the plurality of thick redistributing layer trace that there is thickness or height more than 20 microns so that described thick redistributing layer mark The height of line is more than the minimum widith of described thick redistributing layer trace；And

Expose relative at least one in the redistributing layer trace of the plurality of thickening of described sealant material by grinding Trace.

Method the most according to claim 8, is additionally included in pin in the occupied area of each corresponding described semiconductor element Each in the plurality of semiconductor element is formed the plurality of thick redistributing layer trace.

11. methods according to claim 10, also include:

12. methods according to claim 11, also include that forming fan-out-type piles up interconnection structure, and described structure is arranged on institute State between thick redistributing layer trace and described electrical interconnection.

13. methods according to claim 11, are additionally included in the plurality of transistor relative with described active surface Back side epoxy coating or dielectric film is formed on the back side of core.

14. methods according to claim 11, are additionally included in single step to be arranged on sealant material and described partly lead Above the described active surface of body tube core and described at least four side surface and above the plurality of thick redistributing layer trace.

15. methods according to claim 7, also include:

When described semiconductor element is natural semiconductor crystal wafer a part of, at the described active surface of described semiconductor element Top forms the plurality of thick redistributing layer trace；And

From described natural wafer, segmentation includes the described semiconductor element of the plurality of thick redistributing layer trace.

16. 1 kinds of semiconductor packages, including:

Multiple thick redistributing layer (RDL) traces, described redistributing layer trace is arranged on above the active surface of semiconductor element, and And be arranged in the occupied area of described semiconductor element；

Sealant material, described sealant material is arranged on above described active surface, at least four of described semiconductor element Above side surface and above the plurality of thick redistributing layer trace；And

Conductive interconnection part, described conductive interconnection part is connected to one of at least one in the redistributing layer trace of the plurality of thickening Part, a described part at least one in the redistributing layer trace of wherein said multiple thickenings is relative to described sealant material Material exposes.

17. semiconductor packages according to claim 16, wherein said multiple thick redistributing layer traces have more than 5 microns Thickness or height.

18. semiconductor packages according to claim 17, wherein said multiple thick redistributing layer traces have more than width Thickness or height.

19. semiconductor packages according to claim 17, wherein said multiple thick redistributing layer traces are arranged on described half In the occupied area of conductor tube core.

20. semiconductor packages according to claim 19, are additionally included in the described quasiconductor relative with described active surface The back side epoxy coating formed on the back side of tube core or dielectric film.