CN106231304A - A kind of video decoding integer transform method based on one-dimensional quick dish algorithm improvement - Google Patents
A kind of video decoding integer transform method based on one-dimensional quick dish algorithm improvement Download PDFInfo
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- CN106231304A CN106231304A CN201610768264.0A CN201610768264A CN106231304A CN 106231304 A CN106231304 A CN 106231304A CN 201610768264 A CN201610768264 A CN 201610768264A CN 106231304 A CN106231304 A CN 106231304A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
- H04N19/12—Selection from among a plurality of transforms or standards, e.g. selection between discrete cosine transform [DCT] and sub-band transform or selection between H.263 and H.264
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- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
- H04N19/129—Scanning of coding units, e.g. zig-zag scan of transform coefficients or flexible macroblock ordering [FMO]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
- H04N19/17—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
- H04N19/176—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
- H04N19/18—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a set of transform coefficients
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
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Abstract
The invention discloses a kind of video decoding integer transform method based on one-dimensional quick dish algorithm improvement, the method includes: according to one-dimensional butterfly computation principle, successively input source is carried out rank transformation, row-column transform and line translation and obtains decoding matrix.This video decoding integer transform method is greatly saved the hardware resource of Video Codec, for saving product cost, has the economic benefit of reality, invention uses two-level pipeline structure, there is low delay characteristic, for the occasion that requirement of real-time is the highest, there is the biggest using value.
Description
Technical field
The present invention relates to a kind of video decoding integer transform method based on one-dimensional quick dish algorithm improvement.
Background technology
Conversion coefficient decoding is a very important link in hardware decoder, anti-including 4 × 4 during decoding
Dct transform, 4 × 4 brightness DC coefficient anti-Hadamard conversion, 2 × 2 chroma DC coefficients anti-Hadamard conversion.
At present, in video decodes, the conversion of this three class is that the content according to three transformation matrixs separately designs three hardware
Structure, so every kind conversion is required for a hardware fabric resources and supports, needs to consume substantial amounts of logical resource, and own
Logical resource within FPGA is very limited amount of, how to economize on resources and becomes the research emphasis of numerous scholar.
Summary of the invention
It is an object of the invention to provide a kind of video decoding integer transform method based on one-dimensional quick dish algorithm improvement,
With the problem solving to need in existing video decoding process to consume substantial amounts of logical resource.
For solving above-mentioned technical problem, the present invention provides a kind of video decoding based on one-dimensional quick dish algorithm improvement whole
Transformation of variables method, the method includes: according to one-dimensional butterfly computation principle, successively input source is carried out rank transformation, row-column transform and
Line translation obtains decoding matrix.
Further, the concrete alternative approach that input source carries out rank transformation is:
Utilize first selector MUX1 that the second row of input source and the input data of fourth line are selected, when the first choosing
When the value of the address end selecting device MUX1 is 1, the second row of first selector MUX1 output input source and the initial data of fourth line,
And carry out 4 × 4Hadamard conversion with the first row of input source and row data and obtain 4 × 4 matrixes；As first selector MUX1
The value of address end when being 0, the second row of first selector MUX1 output input source and fourth line move to right the value after, and with
The first row of input source and the third line data carry out inverse dct transform and obtain 4 × 4 matrixes.
Utilize second selector MUX2 that the first row of input source and the transformation results of the third line are selected, when the second choosing
When the value of the address end selecting device MUX2 is 1, carry out 2 × 2Hadamard conversion, the first row and the of second selector MUX2 output
The first row and the third line of being respectively input source of three row and with difference；When the address value of second selector MUX2 is 0, second
The first row of the output of selector MUX2 and the third line are that input source carries out 4 × 4Hadamard rank transformation/4 × 4 inverse DCT respectively
The first row after rank transformation and the third line.
Further, the matrix procession arrived after rank transformation is converted method particularly includes:
By ping-pong buffer mechanism, utilize the matrix procession conversion that row-column transform module ROW2COL will receive, will
The matrix received is stored in row-column transform module ROW2COL by row, then is obtained as row output by the matrix column received
Row-column transform matrix.
Further, described step S3 specifically includes:
Third selector MUX3 is utilized to select, the second row of the second matrix and the input data of fourth line when first
When the value of the address end of selector MUX1 is 1, third selector MUX3 exports second row and the 4th of described row-column transform matrix
The initial data of row, and carry out 4 × 4Hadamard conversion with the first row of described row-column transform matrix and the third line data and obtain
4 × 4 matrixes；When the value of the address end of third selector MUX3 is 0, the of third selector MUX3 output row-column transform matrix
After two row and fourth line move to right one.
Utilize the 4th selector MUX4 that the first row of row-column transform matrix and the transformation results of the third line are selected, when
When the value of the address end of the 4th selector MUX4 is 1, the first row and the third line of the 4th selector MUX4 output are row-column transform
The first row and the third line of matrix module output and with difference；When the value of the address end of the 4th selector MUX4 is 0, the 4th choosing
The data source of the first row and the third line respectively row-column transform matrix module output selecting device MUX4 output carries out 4 ×
The first row after the inverse DCT line translation of 4Hadamard line translation/4 × 4 and the third line, i.e. complete conversion process.
The invention have the benefit that the FPGA that the present invention is carried optimizes structure, video decoding integer can not only be applied to
The FPGA hardware of conversion realizes part, it is possible to be applied to the integer transform of video coding process, and this will be greatly saved video and compile solution
The hardware resource of code device, for saving product cost, has the economic benefit of reality, and invention uses two-level pipeline structure, tool
There is low delay characteristic, for the occasion that requirement of real-time is the highest, there is the biggest using value.
Accompanying drawing explanation
Fig. 1 is the structural representation of one embodiment of the invention.
Detailed description of the invention
Below the detailed description of the invention of the present invention is described, in order to those skilled in the art understand this
Bright, it should be apparent that the invention is not restricted to the scope of detailed description of the invention, from the point of view of those skilled in the art,
As long as various changes limit and in the spirit and scope of the present invention that determine, these changes are aobvious and easy in appended claim
Seeing, all utilize the innovation and creation of present inventive concept all at the row of protection.
Video decoding integer transform method based on one-dimensional quick dish algorithm improvement as shown in Figure 1, the method includes:
According to one-dimensional butterfly computation principle, successively input source is carried out rank transformation, row-column transform and line translation and obtain decoding matrix.
Wherein, above-mentioned input source is carried out rank transformation concrete alternative approach be:
Utilize first selector MUX1 that the second row of input source and the input data of fourth line are selected, when the first choosing
When the value of the address end selecting device MUX1 is 1, the second row of first selector MUX1 output input source and the initial data of fourth line,
And carry out 4 × 4Hadamard conversion with the first row of input source and row data and obtain 4 × 4 matrixes；As first selector MUX1
The value of address end when being 0, the second row of first selector MUX1 output input source and fourth line move to right the value after, and with
The first row of input source and the third line data carry out inverse dct transform and obtain 4 × 4 matrixes.
Utilize second selector MUX2 that the first row of input source and the transformation results of the third line are selected, when the second choosing
When the value of the address end selecting device MUX2 is 1, carry out 2 × 2Hadamard conversion, the first row and the of second selector MUX2 output
The first row and the third line of being respectively input source of three row and with difference；When the address value of second selector MUX2 is 0, second
The first row of the output of selector MUX2 and the third line are that input source carries out 4 × 4Hadamard rank transformation/4 × 4 inverse DCT respectively
The first row after rank transformation and the third line.
The above-mentioned matrix procession arrived to after rank transformation converts method particularly includes:
By ping-pong buffer mechanism, utilize the matrix procession conversion that row-column transform module ROW2COL will receive, will
The matrix received is stored in row-column transform module ROW2COL by row, then is obtained as row output by the matrix column received
Row-column transform matrix.
Above-mentioned row-column transform matrix is carried out line translation method particularly includes:
Third selector MUX3 is utilized to select, the second row of the second matrix and the input data of fourth line when first
When the value of the address end of selector MUX1 is 1, third selector MUX3 output the second row of row-column transform matrix and fourth line
Initial data, and carry out 4 × 4Hadamard conversion with the first row of row-column transform matrix and the third line data and obtain 4 × 4 squares
Battle array；When the value of the address end of third selector MUX3 is 0, third selector MUX3 output row-column transform matrix the second row and
After fourth line moves to right one.
Utilize the 4th selector MUX4 that the first row of row-column transform matrix and the transformation results of the third line are selected, when
When the value of the address end of the 4th selector MUX4 is 1, the first row and the third line of the 4th selector MUX4 output are row-column transform
The first row and the third line of matrix module output and with difference；When the value of the address end of the 4th selector MUX4 is 0, the 4th choosing
The data source of the first row and the third line respectively row-column transform matrix module output selecting device MUX4 output carries out 4 ×
The first row after the inverse DCT line translation of 4Hadamard line translation/4 × 4 and the third line, i.e. complete conversion process.
First rank transformation, the thinking of rear line translation are selected in whole invention.By previous analysis, it is known that 4 × 4 residual blocks are whole
Number dct transform matrix, 4 × 4Hadamard transformation matrix and 2 × 2Hadamard transformation matrix are all symmetrical matrixes, so
The structure completing subsequent rows conversion can use for reference the structure of rank transformation, completes line translation process.For 4 × 4 conversion, a clock
Cycle exports result row0～the row3 of a rank transformation, and the result of this rank transformation is kept in, and completes one after four clock cycle
Individual 4 × 4 matrix column conversion, carry out line translation, row-column transform module by row output a line value col0～col3 the most successively
ROW2COL uses " ping-pong buffer " mechanism, opens up two pieces of internal memory interval A and B, and the result of front 4 cycle rank transformations is stored in by row
In internal memory A, rear four cycles are stored in internal memory B by row, and for output, synthesize 4 × 4 square modules, in front four cycles
By the data in row output internal memory B, rear four cycles, by the data in row output internal memory A, the most only process first son one
Have the time delay in several cycle during block, after each cycle can export the result of a line translation, four clock cycle obtain one
The output matrix of individual 4 × 4.In like manner, for 2 × 2 conversion, a clock cycle exports result row0～the row1 of a rank transformation
(corresponding to row0, row2 port of row-column transform module ROW2COL), the result of this rank transformation is kept in, two clock weeks
After date completes 2 × 2 matrix column conversion, exports a line value col0～col1 (corresponding to ROW2COL by row the most successively
Col0, col2 port of module) carry out line translation, each cycle in period exports a line transformation results, and two clock cycle obtain
The output matrix of one 2 × 2.
Claims (4)
1. a video decoding integer transform method based on one-dimensional quick dish algorithm improvement, it is characterised in that the method bag
Include: according to one-dimensional butterfly computation principle, successively input source is carried out rank transformation, row-column transform and line translation and obtain decoding matrix.
Video the most according to claim 1 decoding integer transform method, it is characterised in that input source is carried out rank transformation
Concrete alternative approach is:
Utilize first selector MUX1 that the second row of input source and the input data of fourth line are selected, work as first selector
When the value of the address end of MUX1 is 1, the second row of first selector MUX1 output input source and the initial data of fourth line, and with
The first row of input source and the third line data carry out 4 × 4Hadamard conversion and obtain 4 × 4 matrixes；When first selector MUX1's
When the value of address end is 0, the second row and the fourth line of first selector MUX1 output input source move to right the value after, and with defeated
The first row and the third line data that enter source carry out inverse dct transform and obtain 4 × 4 matrixes；
Utilize second selector MUX2 that the first row of input source and the transformation results of the third line are selected, work as second selector
When the value of the address end of MUX2 is 1, carry out 2 × 2Hadamard conversion, the first row of second selector MUX2 output and the third line
The first row and the third line of being respectively input source and with difference；When the address value of second selector MUX2 is 0, second selects
The first row of the output of device MUX2 and the third line are that input source carries out the inverse DCT row change of 4 × 4Hadamard rank transformation/4 × 4 respectively
The first row after changing and the third line.
Video the most according to claim 2 decoding integer transform method, it is characterised in that to arriving after rank transformation
The conversion of matrix procession method particularly includes:
By ping-pong buffer mechanism, the matrix procession conversion utilizing row-column transform module ROW2COL to receive, will receive
To matrix be stored in row-column transform module ROW2COL by row, four clock cycle complete 4 × 4 matrix columns conversion, then
Line translation is carried out successively by row output a line value col0～col3.
Video the most according to claim 1 decoding integer transform method, it is characterised in that described step S3 specifically includes:
Utilize third selector MUX3 that the second row of the second matrix and the input data of fourth line are selected, when first selects
When the value of the address end of device MUX1 is 1, third selector MUX3 exports the second row of described row-column transform matrix and fourth line
Initial data, and carry out 4 × 4Hadamard conversion with the first row of described row-column transform matrix and the third line data and obtain 4 × 4
Matrix；When the value of the address end of third selector MUX3 is 0, the second row of third selector MUX3 output row-column transform matrix
Move to right the value after with fourth line, and carry out inverse dct transform obtain 4 with the first row and the third line data of row-column transform matrix
× 4 matrixes；
Utilize the 4th selector MUX4 that the first row of row-column transform matrix and the transformation results of the third line are selected, when the 4th
When the value of the address end of selector MUX4 is 1, the first row and the third line of the 4th selector MUX4 output are row-column transform matrix
The first row and the third line of module output and with difference；When the value of the address end of the 4th selector MUX4 is 0, the 4th selector
The first row of MUX4 output carries out 4 × 4Hadamard row with the data source of the third line respectively row-column transform matrix module output
The first row after conversion/4 × 4 inverse DCT line translations and the third line, i.e. complete conversion process.
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