CN106230292B - A kind of pwm pulse of three-level inverter puts wave method and controller - Google Patents
A kind of pwm pulse of three-level inverter puts wave method and controller Download PDFInfo
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- CN106230292B CN106230292B CN201610682654.6A CN201610682654A CN106230292B CN 106230292 B CN106230292 B CN 106230292B CN 201610682654 A CN201610682654 A CN 201610682654A CN 106230292 B CN106230292 B CN 106230292B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
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Abstract
The pwm pulse of three-level inverter provided by the present application puts wave method and controller, Feng Bohou is being carried out by the error event enforcement functionalities in the first variety of priority driven, pwm pulse is being forced to by the software enforcement functionalities in the second variety of priority driven puts wave moment ideal driving signal first；Again judge current state meet it is received put wave instruction in when putting wave condition, remove the first variety of priority driven and the second variety of priority driven enforcement functionalities；So that the pwm pulse of single-phase bridge arm is controlled each switching tube according to above-mentioned ideal driving signal, avoid the occurrence of burst pulse and the case where inner and outer tubes simultaneously turn on, and then avoids the problem of thus bring not can guarantee normal inverter, reliable, stable operation.
Description
Technical field
The present invention relates to three-level inverter technical fields more particularly to a kind of pwm pulse of three-level inverter to put wave
Method and controller.
Background technique
The advantages such as three-phase tri-level inverter system has voltage stress low, and output harmonic wave is low, can obtain higher defeated
Voltage out, thus the new energies field such as be widely used solar energy and wind energy.Fig. 1 is three-phase tri-level inverter
The circuit diagram of the single-phase bridge arm of system, comprising: four switching tubes (S1, S2, S3 and S4).The system generally uses three level carriers
PWM control method, for example with phase carrier wave SPWM control method, pass through single-phase modulating wave us(Optimal Decomposition us1And us2) and triangle
Carrier wave ucAfter being compared, export pwm pulse (PWM1, PWM2, PWM3 and PWM4), corresponding signal waveforms are referring to fig. 2.
In the practical application of the system, when inverter operates normally, it may occur that power grid falls or other disturbances,
Cause inverter to need to block pwm pulse (i.e. envelope wave) in short-term, after the stabilization of power grids or disturbance disappear, then decontrols PWM again
Pulse (puts wave), in the hope of inverter not off-grid.General envelope wave process is by DSP (Digital Signal
Processor, digital signal processor) ePWM module enabled by error event, pwm pulse is all forced to high shape
State, fast response time；Putting wave process accordingly is to be forced to height to pwm pulse by releasing error event, makes it by upper
It is exported after stating normally.The envelope wave region according to shown in dotted line frame in Fig. 3, corresponding pwm pulse output result is such as
Shown in Fig. 4.
It is available by Fig. 4, initially put the wave moment, in fact it could happen that the burst pulse as shown in Fig. 4 centre circle, due to electric power electricity
There is the limitation of minimum service time and minimum turn-off time in sub- device, this requires the pulse widths of PWM output cannot be unlimited
It is narrow；Pulse width is less than the minimum service time or minimum turn-off time of device, and device cannot normally be switched on or off, make be
Reliability of uniting reduces.In addition, putting wave initial time is also easy to appear inner tube (switching tube S2 or switching tube S3 as shown in figure 1) and outer
The case where pipe (switching tube S1 or switching tube S4 as shown in figure 1) simultaneously turns on, due to the otherness and driving letter of switching tube characteristic
The otherness of number transmission delay, it cannot be guaranteed that inner and outer tubes reliable conducting simultaneously has electric current if outer tube is connected prior to inner tube
It is easy to cause inner tube to bear entire busbar voltage in the case where afterflow；And then cause the resistance to pressure request of switch tube very high, it deposits
In greater risk.
Summary of the invention
In view of this, the present invention provides a kind of pwm pulses of three-level inverter to put wave method and controller, to solve
PWM puts that burst pulse occurs in wave and inner and outer tubes simultaneously turn on equal abnormal operating states in the prior art, leads to not guarantee
The problem of inverter is normal, reliable, stable operation.
To achieve the goals above, technical solution provided in an embodiment of the present invention is as follows:
A kind of pwm pulse of three-level inverter puts wave method, is applied to three-level inverter, the three-level inverter
Single-phase bridge arm include: the first switch tube being sequentially connected, second switch, third switching tube and the 4th switching tube；Wherein, institute
The collector for stating first switch tube is connected with the anode of power supply, the cathode phase of the emitter and the power supply of the 4th switching tube
Even；The pwm pulse of the three-level inverter puts wave method
Whether the current single-phase modulating wave of judgement is more than or equal to zero；
If the current single-phase modulating wave of judgement is more than or equal to zero, forcing the pwm pulse of the single-phase bridge arm is to make
The second switch conducting, the drive for being turned off the first switch tube, the third switching tube and the 4th switching tube
Dynamic signal；
If it is described to make that the current single-phase modulating wave of judgement less than zero, forces the pwm pulse of the single-phase bridge arm
The conducting of third switching tube, the driving letter for being turned off the first switch tube, the second switch and the 4th switching tube
Number；
Judge whether current state meets received put in wave instruction and put wave condition；
If judgement puts wave condition described in meeting, the pressure of the pwm pulse output to the single-phase bridge arm is removed.
Optionally, described to judge whether current state meets the received wave condition of putting put in wave instruction and include:
Judge whether current state is in triangular carrier rising edge；
Alternatively, judging whether current state is in triangular carrier failing edge.
Optionally, judge whether current state is before triangular carrier rising edge described further include:
If the fiducial value of presently described single-phase modulating wave be more than or equal to CMPR_En, by the single-phase modulating wave clipping in
CMPR_Limit；Wherein, CMPR_En is to preset to put wave moment corresponding triangular carrier count value, and CMPR_Limit is default width
Value, and 0 < CMPR_Limit < CMPR_En；
Alternatively, judging whether current state is before triangular carrier failing edge described further include:
If the fiducial value of presently described single-phase modulating wave be more than or equal to CMPR_En, by the single-phase modulating wave clipping in
CMPR_Limit；Wherein, CMPR_En is to preset to put wave moment corresponding triangular carrier count value, and CMPR_Limit is default width
Value, and Period > CMPR_Limit > CMPR_En, Period are triangular carrier peak value.
Optionally, after the pressure for removing the pwm pulse output to the single-phase bridge arm further include:
By initially putting wave Success Flag sets 1；
Before whether the current single-phase modulating wave of the judgement is more than or equal to zero further include:
Judge described initially to put whether wave Success Flag is equal to zero；
If the wave Success Flag of initially putting equal to zero, executes whether the current single-phase modulating wave of the judgement is greater than
In zero the step of.
Optionally, it is described judge current state whether meet it is received put wave instruction in put wave condition before also wrap
It includes:
Judge it is described it is received put wave instruction it is whether effective；
If judge it is described it is received put wave instruction effectively, execute and described judge whether current state meets and received put wave
In instruction the step of putting wave condition.
A kind of controller of three-level inverter is applied to three-level inverter, the single-phase bridge of the three-level inverter
Arm includes: the first switch tube being sequentially connected, second switch, third switching tube and the 4th switching tube；Wherein, it described first opens
The collector for closing pipe is connected with the anode of power supply, and the emitter of the 4th switching tube is connected with the cathode of the power supply；It is described
The controller of three-level inverter includes:
Memory, for storing single-phase modulating wave and triangular carrier；
Whether processor, the single-phase modulating wave for judging current are more than or equal to zero；If the current list of judgement
Phase modulating wave is more than or equal to zero, then forcing the pwm pulse of the single-phase bridge arm is that the second switch is connected, and makes described the
The driving signal that one switching tube, the third switching tube and the 4th switching tube are turned off；If judging currently described single-phase
For modulating wave less than zero, then forcing the pwm pulse of the single-phase bridge arm is that the third switching tube is connected, and makes the first switch
The driving signal that pipe, the second switch and the 4th switching tube are turned off；It is received to judge whether current state meets
It puts in wave instruction and puts wave condition；If judgement puts wave condition described in meeting, removes and the pwm pulse of the single-phase bridge arm is exported
Pressure.
Optionally, the processor is used to judge whether current state to meet received put in wave instruction and put wave condition
When, it is specifically used for:
Judge whether current state is in triangular carrier rising edge；
Alternatively, judging whether current state is in triangular carrier failing edge.
Optionally, the processor is also used to:
Judge whether current state is before triangular carrier rising edge, if presently described single-phase modulating wave described
Fiducial value is more than or equal to CMPR_En, then by the single-phase modulating wave clipping in CMPR_Limit；Wherein, CMPR_En is default puts
Wave moment corresponding triangular carrier count value, CMPR_Limit are default amplitude, and 0 < CMPR_Limit < CMPR_En；
Alternatively, judging whether current state is before triangular carrier failing edge, if presently described single-phase tune described
The fiducial value of wave processed is more than or equal to CMPR_En, then by the single-phase modulating wave clipping in CMPR_Limit；Wherein, CMPR_En is
Default to put wave moment corresponding triangular carrier count value, CMPR_Limit is default amplitude, and Period > CMPR_Limit >
CMPR_En, Period are triangular carrier peak value.
Optionally, the processor is also used to:
After the pressure for removing the pwm pulse output to the single-phase bridge arm, by initially putting wave Success Flag sets 1；
Before whether the current single-phase modulating wave of judgement is more than or equal to zero, judge described initially whether put wave Success Flag
Equal to zero；
If the wave Success Flag of initially putting judges whether current single-phase modulating wave is more than or equal to zero equal to zero.
Optionally, the processor is also used to:
Judge it is described it is received put wave instruction it is whether effective；
If judging, the received wave of putting is instructed effectively, judges whether current state meets received put in wave instruction
Put wave condition.
Optionally, the processor is digital signal processor.
Optionally, the memory is the memory being integrated in the digital signal processor.
The pwm pulse of the three-level inverter provided by the present application puts wave method, first determines whether current single-phase modulation
Whether wave is more than or equal to zero；If the current single-phase modulating wave of judgement is more than or equal to zero, the PWM of the single-phase bridge arm is forced
Pulse is that the second switch is connected, and keeps the first switch tube, the third switching tube and the 4th switching tube equal
The driving signal of shutdown；If the current single-phase modulating wave of judgement less than zero, forces the pwm pulse of the single-phase bridge arm to be
The third switching tube is connected, is turned off the first switch tube, the second switch and the 4th switching tube
Driving signal；Pwm pulse is forced to and puts wave moment ideal driving signal；Received wave is put judging that current state meets again
In instruction when putting wave condition, remove the pressure to the output of the pwm pulse of the single-phase bridge arm；At this point, the single-phase bridge arm
Pwm pulse will control each switching tube according to above-mentioned ideal driving signal, avoid the occurrence of burst pulse and inner and outer tubes simultaneously
The case where conducting, and then avoid the problem of thus bring not can guarantee inverter normal, reliable, stable operation；To next
When a control period, the pwm pulse of the three-level inverter can be according to normally relatively being exported.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is the circuit diagram for the single-phase bridge arm of three-phase tri-level inverter system that the prior art provides；
Fig. 2 is the signal waveforms for the single-phase bridge arm of three-phase tri-level inverter system that the prior art provides；
Fig. 3 is the envelope wave signal schematic representation for the single-phase bridge arm of three-phase tri-level inverter system that the prior art provides；
Fig. 4 is the envelope wave signal waveforms for the single-phase bridge arm of three-phase tri-level inverter system that the prior art provides；
Fig. 5 is the signal sequence that the single-phase modulating wave positive half cycle rising edge that one embodiment of the application provides puts wave pwm pulse
Figure；
Fig. 6 is that the single-phase modulating wave positive half cycle rising edge that another embodiment of the application provides puts the pressure of wave pwm pulse software
Signal timing diagram afterwards；
Fig. 7 is that the single-phase modulating wave positive half cycle rising edge that another embodiment of the application provides puts the pressure of wave pwm pulse software
And the signal timing diagram after optimizing；
When Fig. 8 is that the single-phase modulating wave negative half period rising edge that another embodiment of the application provides puts the signal of wave pwm pulse
Sequence figure；
Fig. 9 is that the single-phase modulating wave negative half period rising edge that another embodiment of the application provides puts the pressure of wave pwm pulse software
Signal timing diagram afterwards；
Figure 10 is that the single-phase modulating wave negative half period rising edge that another embodiment of the application provides puts the pressure of wave pwm pulse software
And the signal timing diagram after optimizing；
Figure 11 is that the pwm pulse for the three-level inverter that another embodiment of the application provides puts the flow chart of wave method；
Figure 12 is that the pwm pulse for the three-level inverter that another embodiment of the application provides puts another process of wave method
Figure；
Figure 13 is that the pwm pulse for the three-level inverter that another embodiment of the application provides puts another process of wave method
Figure；
Figure 14 is the structural schematic diagram of the controller for the three-level inverter that another embodiment of the application provides.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
The present invention provides a kind of pwm pulses of three-level inverter to put wave method and controller, to solve the prior art
Middle PWM puts that burst pulse occurs in wave and inner and outer tubes simultaneously turn on equal abnormal operating states, is leading to not guaranteeing inverter just
Often, reliably, stable operation the problem of.
Specifically, the pwm pulse of the three-level inverter puts wave method, it is applied to three-level inverter shown in FIG. 1,
The single-phase bridge arm of the three-level inverter includes: the first switch tube S1, second switch S2, third switching tube being sequentially connected
S3 and the 4th switching tube S4；Wherein, the collector of first switch tube S1 is connected with the anode of power supply, the transmitting of the 4th switching tube S4
Pole is connected with the cathode of the power supply；It is as shown in figure 11 that the pwm pulse of the three-level inverter puts wave method, comprising:
Whether the current single-phase modulating wave of S101, judgement is more than or equal to zero；
If the current single-phase modulating wave of judgement is more than or equal to zero, thens follow the steps S102, forces the single-phase bridge arm
Pwm pulse be that the second switch is connected, make the first switch tube, the third switching tube and the 4th switch
The driving signal that pipe is turned off；
If the PWM that the current single-phase modulating wave of judgement less than zero, thens follow the steps S103, forces the single-phase bridge arm
Pulse is that the third switching tube is connected, and keeps the first switch tube, the second switch and the 4th switching tube equal
The driving signal of shutdown；
S104, judge whether current state meets received put in wave instruction and put wave condition；
If putting wave condition described in judgement satisfaction, thens follow the steps S105, removes the pwm pulse output to the single-phase bridge arm
Pressure.
In specific practical application, all pwm pulses are all forced to by the ePWM module of DSP using error event
High state carries out Feng Bohou by the first variety of priority driven, is judged at current single-phase modulating wave by step S101 first
In positive half cycle or negative half period, then by software enforcement functionalities (step S102 or S103), i.e. the second variety of priority driven is carried out
Put the preparation of wavefront.
Assuming that each switching tube is low level driving, then step S102 can be to force the single-phase bridge arm by software
Pwm pulse be 1011 driving signal；Step S103 can be to force the pwm pulse of the single-phase bridge arm to be by software
1101 driving signal；Wherein, the low level in pwm pulse " 0 " drives corresponding switching tube conducting, the height electricity in pwm pulse
Flat " 1 " drives corresponding switching tube shutdown.
Wave condition of putting in putting wave and instruct is current state to be illustrated for triangular carrier rising edge, if sentencing
The current single-phase modulating wave that breaks is more than or equal to zero, then pwm pulse shown in fig. 5 (can be had circle by step S102
Shown in PWM1 be burst pulse and PWM1 and PWM2 is the feelings that 0 i.e. first switch tube and second switch simultaneously turn on simultaneously
Condition) it is forced to waveform shown in fig. 6；If the single-phase modulating wave of judgement currently less than zero, can be incited somebody to action by step S103
Pwm pulse shown in Fig. 8 (exist PWM2 shown in circle be burst pulse and PWM2 and PWM3 be simultaneously 0 i.e. first switch tube and
The case where second switch simultaneously turns on) it is forced to waveform shown in Fig. 9；Wherein, PWM1 is the signal for driving first switch tube,
PWM2 is the signal for driving second switch, and PWM3 is the signal for driving third switching tube, and PWM4 is the 4th switching tube of driving
Signal.It is available by Fig. 5 to Fig. 8, by software enforcement functionalities, i.e. the second variety of priority driven, pwm pulse is forced to and puts wave
Moment ideal driving signal not only forces inner tube to be constantly on state, while avoiding the appearance of burst pulse, completes
Put the preparation of wavefront.
After the preparation of wavefront is put in completion, it can judge whether current state meets received put by step S104
Wave condition is put in wave instruction, for example judges whether current state is in triangular carrier rising edge；
If current state is that can be removed by step S105 to the single-phase bridge arm in triangular carrier rising edge
The pressure (enforcement functionalities including the first variety of priority driven and the second variety of priority driven) of pwm pulse output.At this point, the single-phase bridge arm
Pwm pulse will control each switching tube according to above-mentioned ideal driving signal, avoid the occurrence of burst pulse and inner and outer tubes are same
When the case where being connected；When next control period, the pwm pulse of the three-level inverter can according to it is normal relatively into
Row output.
The pwm pulse of the three-level inverter provided in this embodiment puts wave method, by the first preferential drive
Dynamic error event enforcement functionalities carry out Feng Bohou, first by the software enforcement functionalities in the second variety of priority driven by PWM arteries and veins
Punching, which is forced to, puts wave moment ideal driving signal；Again judge current state meet it is received put wave instruction in put wave condition
When, remove the enforcement functionalities of the first variety of priority driven and the second variety of priority driven；Make the pwm pulse of the single-phase bridge arm according to above-mentioned reason
The driving signal thought controls each switching tube, and similarly, the pwm pulse of other two single-phase bridge arm also will be according to ideal driving letter
Its corresponding each switching tube number is controlled, avoids the occurrence of burst pulse and the case where inner and outer tubes simultaneously turn on, and then is avoided
Thus bring not can guarantee the problem of inverter normal, reliable, stable operation.
Optionally, step S104 includes:
Judge whether current state is in triangular carrier rising edge；
Alternatively, judging whether current state is in triangular carrier failing edge.
In specific practical application, step S104 can be selected according to its specific application environment, not done herein
It is specific to limit.
The pwm pulse that another specific embodiment of the present invention provides another three-level inverter puts wave method, such as
Shown in Figure 12, comprising:
Whether the current single-phase modulating wave of S201, judgement is more than or equal to zero；
If the current single-phase modulating wave of judgement is more than or equal to zero, thens follow the steps S202, forces the single-phase bridge arm
Pwm pulse be that the second switch is connected, make the first switch tube, the third switching tube and the 4th switch
The driving signal that pipe is turned off；
If the PWM that the current single-phase modulating wave of judgement less than zero, thens follow the steps S203, forces the single-phase bridge arm
Pulse is that the third switching tube is connected, and keeps the first switch tube, the second switch and the 4th switching tube equal
The driving signal of shutdown；
S204, judge whether the fiducial value of presently described single-phase modulating wave is more than or equal to CMPR_En；Wherein, CMPR_En is
It is default to put wave moment corresponding triangular carrier count value；
If the fiducial value of presently described single-phase modulating wave is more than or equal to CMPR_En, S205 is thened follow the steps, will be described single-phase
Modulating wave clipping is in CMPR_Limit.
Wherein, CMPR_En is to preset to put wave moment corresponding triangular carrier count value, and CMPR_Limit is default amplitude；
When putting wave using triangular carrier rising edge, 0 < CMPR_Limit < CMPR_En；When putting wave using triangular carrier failing edge,
Period > CMPR_Limit > CMPR_En, Period are triangular carrier peak value.
S206, judge whether current state meets received put in wave instruction and put wave condition；
If putting wave condition described in judgement satisfaction, thens follow the steps S207, removes the pwm pulse output to the single-phase bridge arm
Pressure.
In specific practical application, it can realize that the pwm pulse of the three-level inverter puts wave method by DSP,
According to the characteristic of DSP, the software enforcement functionalities as the second variety of priority driven be carried out respectively according to each control period it is compulsory；
Within the control period for actually putting wave, after the enforcement functionalities for removing the first variety of priority driven and the second variety of priority driven, if current institute
The fiducial value for stating single-phase modulating wave is more than or equal to CMPR_En, then between the triangular carrier of subsequent generation and single-phase modulating wave just
Often relatively, it will change the step the ideal driving signal that S202 or S203 is obtained；It therefore can be by step S205 to upper
Change is stated to optimize.
Specifically, default wave moment corresponding triangular carrier count value CMPR_En of putting can be put in wave instruction to be received
Be arranged, be also possible to according to specific application environment and preset in advance, be not specifically limited herein；It is in single in current state
When phase modulating wave positive half cycle, by put wave instruction in put wave condition be current state be in triangular carrier rising edge for carry out
Illustrate, since triangular carrier rising edge removes the enforcement functionalities of the error event in the first variety of priority driven and is in second preferentially
The software enforcement functionalities of driving are forced by the software enforcement functionalities in previous control period, force the PWM of the single-phase bridge arm
The driving signal that pulse is 1011, control second switch pipe conducting, if the fiducial value of the control period single-phase modulating wave is small
Wave moment corresponding triangular carrier count value CMPR_En is put in default, then is guaranteed, second switch is clamped down on as on state,
4th switching tube is forced to off state, complementary first switch tube and third switching tube are modulated later, export positive electricity
Pressure or 0 level, such as the single-phase modulating wave positive half cycle of Fig. 6 and when triangular carrier rising edge puts wave, not optimized PWM timing diagram institute
Show；If the fiducial value of the control period single-phase modulating wave, which is more than or equal to preset, puts wave moment corresponding triangular carrier count value
CMPR_En, the driving signal obtained more afterwards can control the conducting of third switching tube, export the 0 level (PWM of the single-phase bridge arm
The driving signal that pulse is 1001), as shown in Figure 6；In order to guarantee initially to put the unification of wave timing, the previous of wave is put in rising edge
The control period passes through step S205 for the single-phase modulating wave clipping in CMPR_Limit, puts so that positive half cycle is optimized
Wave timing is as shown in Figure 7.
Similarly, such as the single-phase modulating wave negative half period of Fig. 9 and when triangular carrier rising edge puts wave, not optimized PWM timing diagram
It is shown, when current state is single-phase modulating wave negative half period, pass through step in the previous control period that triangular carrier rising edge puts wave
S205 in CMPR_Limit, guarantees the single-phase modulating wave clipping in negative half period, and third switching tube is clamped down on as on state,
First switch tube is clamped down on as off state, and complementary second switch and the 4th switching tube are modulated later, exports negative electricity
Pressure or 0 level.It is as shown in Figure 10 that wave timing is put in initial p WM pulse after negative half period optimization；Wherein, PWM1 is that driving first is opened
Close the signal of pipe, PWM2 be the signal for driving second switch, and PWM3 be the signal for driving third switching tube, and PWM4 is drives the
The signal of four switching tubes.
The pwm pulse that another specific embodiment of the present invention provides another three-level inverter puts wave method, such as
Shown in Figure 13, comprising:
S301, judgement initially put whether wave Success Flag is equal to zero；
If whether the wave Success Flag of initially putting equal to zero, thens follow the steps S302, the single-phase modulating wave of judgement currently
More than or equal to zero；
If the current single-phase modulating wave of judgement is more than or equal to zero, thens follow the steps S303, forces the single-phase bridge arm
Pwm pulse be that the second switch is connected, make the first switch tube, the third switching tube and the 4th switch
The driving signal that pipe is turned off；
If the PWM that the current single-phase modulating wave of judgement less than zero, thens follow the steps S304, forces the single-phase bridge arm
Pulse is that the third switching tube is connected, and keeps the first switch tube, the second switch and the 4th switching tube equal
The driving signal of shutdown；
S307, judge whether current state meets received put in wave instruction and put wave condition；
If putting wave condition described in judgement satisfaction, thens follow the steps S308, removes the pwm pulse output to the single-phase bridge arm
Pressure.
S309, it initially puts wave Success Flag by described and sets 1；
Envelope wave success after, it is described initially put wave Success Flag will be by clear 0, the software for being now in the second variety of priority driven is strong
Function processed can be completed to put the preparation of wavefront by step S302 to S308；After putting wave success, then pass through step S309
It initially puts wave Success Flag by described and sets 1；And then completion passes through the wave Success Flag of initially putting and identifies envelope wave or put wave
State.
Optionally, as shown in the dashed box in Figure 13, between step S304 and S307 further include:
S305, judge whether the fiducial value of presently described single-phase modulating wave is more than or equal to CMPR_En；Wherein, CMPR_En is
It is default to put wave moment corresponding triangular carrier count value；
If the fiducial value of presently described single-phase modulating wave is more than or equal to CMPR_En, S306 is thened follow the steps, will be described single-phase
Modulating wave clipping is in CMPR_Limit.
Wherein, CMPR_En is to preset to put wave moment corresponding triangular carrier count value, and CMPR_Limit is default amplitude；
When putting wave using triangular carrier rising edge, 0 < CMPR_Limit < CMPR_En；When putting wave using triangular carrier failing edge,
Period > CMPR_Limit > CMPR_En, Period are triangular carrier peak value.
In addition, in the above-described embodiments, judging whether current state meets received put in wave instruction and put wave described
Before condition (the step S307 in step S206 and Figure 13 in step S104, Figure 12 in Figure 11) further include:
Judge it is described it is received put wave instruction it is whether effective；
If judge it is described it is received put wave instruction effectively, execute and described judge whether current state meets and received put wave
In instruction the step of putting wave condition.
In specific practical application, there may be received the case where putting wave instruction ignore, it is therefore desirable to first to institute
State it is received put wave instruction whether effectively judged, when judge it is described it is received put wave instruction it is effective when, then execution described in sentence
Disconnected current state whether meet it is received put wave instruction in the step of putting wave condition；When judge it is described it is received put wave instruction nothing
When effect, and without the subsequent step in above-described embodiment；So that the present embodiment is more reliable.
Another embodiment of the present invention additionally provides a kind of controller of three-level inverter, applied to as shown in Figure 1 three
Electrical level inverter, the single-phase bridge arm of the three-level inverter include: the first switch tube S1 being sequentially connected, second switch
S2, third switching tube S3 and the 4th switching tube S4；Wherein, the collector of first switch tube S1 is connected with the anode of power supply, and the 4th
The emitter of switching tube S4 is connected with the cathode of the power supply；The controller of the three-level inverter includes: as shown in figure 14
Memory 101, for storing single-phase modulating wave and triangular carrier；
Whether processor 102, the single-phase modulating wave for judging current are more than or equal to zero；If judging currently described
Single-phase modulating wave is more than or equal to zero, then forcing the pwm pulse of the single-phase bridge arm is that the second switch is connected, and makes described
The driving signal that first switch tube, the third switching tube and the 4th switching tube are turned off；If the current list of judgement
For phase modulating wave less than zero, then forcing the pwm pulse of the single-phase bridge arm is that the third switching tube is connected, and makes described first to open
The driving signal that Guan Guan, the second switch and the 4th switching tube are turned off；Judge whether current state meets reception
Put wave instruction in put wave condition；If judgement puts wave condition described in meeting, remove defeated to the pwm pulse of the single-phase bridge arm
Pressure out.
Optionally, processor 102 be used for judge current state whether meet it is received put wave instruction in when putting wave condition,
It is specifically used for:
Judge whether current state is in triangular carrier rising edge；
Alternatively, judging whether current state is in triangular carrier failing edge.
Optionally, processor 102 is also used to:
Judge whether current state is before triangular carrier rising edge, if presently described single-phase modulating wave described
Fiducial value is more than or equal to CMPR_En, then by the single-phase modulating wave clipping in CMPR_Limit；Wherein, CMPR_En is default puts
Wave moment corresponding triangular carrier count value, CMPR_Limit are default amplitude, and 0 < CMPR_Limit < CMPR_En.
Alternatively, judging whether current state is before triangular carrier failing edge, if presently described single-phase tune described
The fiducial value of wave processed is more than or equal to CMPR_En, then by the single-phase modulating wave clipping in CMPR_Limit；Wherein, CMPR_En is
Default to put wave moment corresponding triangular carrier count value, CMPR_Limit is default amplitude, and Period > CMPR_Limit >
CMPR_En, Period are triangular carrier peak value.
Optionally, processor 102 is also used to:
After the pressure for removing the pwm pulse output to the single-phase bridge arm, by initially putting wave Success Flag sets 1；
Before whether the current single-phase modulating wave of judgement is more than or equal to zero, judge described initially whether put wave Success Flag
Equal to zero；
If the wave Success Flag of initially putting judges whether current single-phase modulating wave is more than or equal to zero equal to zero.
Optionally, processor 102 is also used to:
Judge it is described it is received put wave instruction it is whether effective；
If judging, the received wave of putting is instructed effectively, judges whether current state meets received put in wave instruction
Put wave condition.
Specific working principle is same as the previously described embodiments, no longer repeats one by one herein.
Optionally, processor 102 is digital signal processor.
Optionally, memory 101 is the memory being integrated in the digital signal processor.
It is worth noting that realize that the pwm pulse of the three-level inverter puts wave using the digital signal processor,
Not only method is simple, does not influence normal pulsewidth modulation, but also is not necessarily to additional controller (CPLD or FPGA) Collaborative Control,
It is suitble to engineer application.
In specific practical application, realize that the above-mentioned device for putting wave control can be the digital signal processor, when
So or any other single-chip microcontroller with the above function or controller, it is not specifically limited herein, in the application
Protection scope in.
Each embodiment is described in a progressive manner in the present invention, the highlights of each of the examples are with other realities
The difference of example is applied, the same or similar parts in each embodiment may refer to each other.For device disclosed in embodiment
Speech, since it is corresponded to the methods disclosed in the examples, so being described relatively simple, related place is referring to method part illustration
?.
The above is only the preferred embodiment of the present invention, make skilled artisans appreciate that or realizing of the invention.It is right
A variety of modifications of these embodiments will be apparent to one skilled in the art, general original as defined herein
Reason can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, the present invention will not
Be intended to be limited to the embodiments shown herein, and be to fit to it is consistent with the principles and novel features disclosed in this article most
Wide range.
Claims (10)
1. a kind of pwm pulse of three-level inverter puts wave method, which is characterized in that be applied to three-level inverter, described three
The single-phase bridge arm of electrical level inverter includes: the first switch tube being sequentially connected, second switch, third switching tube and the 4th switch
Pipe；Wherein, the collector of the first switch tube is connected with the anode of power supply, the emitter and the electricity of the 4th switching tube
The cathode in source is connected；The pwm pulse of the three-level inverter puts wave method
Whether the current single-phase modulating wave of judgement is more than or equal to zero；
If the single-phase modulating wave of judgement currently is more than or equal to zero, it is described to make to force the pwm pulse of the single-phase bridge arm
Second switch conducting, the driving letter for being turned off the first switch tube, the third switching tube and the 4th switching tube
Number；
If it is to make the third that the current single-phase modulating wave of judgement, which less than zero, forces the pwm pulse of the single-phase bridge arm,
Switching tube conducting, the driving signal for being turned off the first switch tube, the second switch and the 4th switching tube；
Judge whether current state meets received put in wave instruction and put wave condition；
If judgement puts wave condition described in meeting, the pressure of the pwm pulse output to the single-phase bridge arm is removed；
It is described to judge whether current state meets the received wave condition of putting put in wave instruction and include:
Judge whether current state is in triangular carrier rising edge；
Alternatively, judging whether current state is in triangular carrier failing edge.
2. the pwm pulse of three-level inverter according to claim 1 puts wave method, which is characterized in that in the judgement
Whether current state is before triangular carrier rising edge further include:
If the fiducial value of presently described single-phase modulating wave is more than or equal to CMPR_En, by the single-phase modulating wave clipping in CMPR_
Limit；Wherein, CMPR_En be it is default put wave moment corresponding triangular carrier count value, CMPR_Limit is default amplitude, and 0
<CMPR_Limit<CMPR_En；
Alternatively, judging whether current state is before triangular carrier failing edge described further include:
If the fiducial value of presently described single-phase modulating wave is more than or equal to CMPR_En, by the single-phase modulating wave clipping in CMPR_
Limit；Wherein, CMPR_En is to preset to put wave moment corresponding triangular carrier count value, and CMPR_Limit is default amplitude, and
Period > CMPR_Limit > CMPR_En, Period are triangular carrier peak value.
3. the pwm pulse of three-level inverter according to claim 1 or 2 puts wave method, which is characterized in that described clear
After the pressure of the pwm pulse output to the single-phase bridge arm further include:
By initially putting wave Success Flag sets 1；
Before whether the current single-phase modulating wave of the judgement is more than or equal to zero further include:
Judge described initially to put whether wave Success Flag is equal to zero；
If the wave Success Flag of initially putting equal to zero, executes whether the current single-phase modulating wave of the judgement is more than or equal to zero
The step of.
4. the pwm pulse of three-level inverter according to claim 1 or 2 puts wave method, which is characterized in that sentence described
Disconnected current state whether meet it is received put in wave instruction put wave condition before further include:
Judge it is described it is received put wave instruction it is whether effective；
If judge it is described it is received put wave instruction effectively, execute it is described judge current state whether meet it is received put wave instruct
In the step of putting wave condition.
5. a kind of controller of three-level inverter, which is characterized in that be applied to three-level inverter, the three-level inverter
Single-phase bridge arm include: the first switch tube being sequentially connected, second switch, third switching tube and the 4th switching tube；Wherein, institute
The collector for stating first switch tube is connected with the anode of power supply, the cathode phase of the emitter and the power supply of the 4th switching tube
Even；The controller of the three-level inverter includes:
Memory, for storing single-phase modulating wave and triangular carrier；
Whether processor, the single-phase modulating wave for judging current are more than or equal to zero；If the current single-phase tune of judgement
Wave processed is more than or equal to zero, then forcing the pwm pulse of the single-phase bridge arm is that the second switch is connected, and makes described first to open
The driving signal that Guan Guan, the third switching tube and the 4th switching tube are turned off；If the current single-phase modulation of judgement
For wave less than zero, then forcing the pwm pulse of the single-phase bridge arm is that the third switching tube is connected, make the first switch tube,
The driving signal that the second switch and the 4th switching tube are turned off；Judge whether current state meets and received puts wave
Wave condition is put in instruction；If judgement puts wave condition described in meeting, the strong of the pwm pulse output to the single-phase bridge arm is removed
System；
The processor be used for judge current state whether meet it is received put wave instruction in when putting wave condition, be specifically used for:
Judge whether current state is in triangular carrier rising edge；
Alternatively, judging whether current state is in triangular carrier failing edge.
6. the controller of three-level inverter according to claim 5, which is characterized in that the processor is also used to:
Judge whether current state is before triangular carrier rising edge, if the comparison of presently described single-phase modulating wave described
Value is more than or equal to CMPR_En, then by the single-phase modulating wave clipping in CMPR_Limit；Wherein, CMPR_En is when presetting to put wave
Carve corresponding triangular carrier count value, CMPR_Limit is default amplitude, and 0 < CMPR_Limit < CMPR_En；
Alternatively, judging whether current state is before triangular carrier failing edge, if presently described single-phase modulating wave described
Fiducial value be more than or equal to CMPR_En, then by the single-phase modulating wave clipping in CMPR_Limit；Wherein, CMPR_En is default
Put wave moment corresponding triangular carrier count value, CMPR_Limit is default amplitude, and Period > CMPR_Limit > CMPR_
En, Period are triangular carrier peak value.
7. the controller of three-level inverter according to claim 5 or 6, which is characterized in that the processor is also used to:
After the pressure for removing the pwm pulse output to the single-phase bridge arm, by initially putting wave Success Flag sets 1；
Before whether the current single-phase modulating wave of judgement is more than or equal to zero, judge described initially to put whether wave Success Flag is equal to
Zero；
If the wave Success Flag of initially putting judges whether current single-phase modulating wave is more than or equal to zero equal to zero.
8. the controller of three-level inverter according to claim 5 or 6, which is characterized in that the processor is also used to:
Judge it is described it is received put wave instruction it is whether effective；
If judging, the received wave of putting is instructed effectively, judges whether current state meets received put in wave instruction and put wave
Condition.
9. the controller of three-level inverter according to claim 5 or 6, which is characterized in that the processor is number
Signal processor.
10. the controller of three-level inverter according to claim 9, which is characterized in that the memory is to be integrated in
Memory in the digital signal processor.
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| CN113965100B (en) * | 2021-10-29 | 2023-08-29 | 株洲变流技术国家工程研究中心有限公司 | Decoding method, control method and device for three-level pulse modulation control |
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| US9450491B2 (en) * | 2014-10-23 | 2016-09-20 | Qualcomm Incorporated | Circuits and methods providing three-level signals at a synchronous buck converter |
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| CN104377659A (en) * | 2013-08-16 | 2015-02-25 | 力博特公司 | Wave sealing-wave unsealing method and device, wave unsealing method and device and inverter circuit |
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