CN106209034B - A kind of high frequency clock frequency detecting structure for attack resistance chip - Google Patents
A kind of high frequency clock frequency detecting structure for attack resistance chip Download PDFInfo
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- CN106209034B CN106209034B CN201610599416.9A CN201610599416A CN106209034B CN 106209034 B CN106209034 B CN 106209034B CN 201610599416 A CN201610599416 A CN 201610599416A CN 106209034 B CN106209034 B CN 106209034B
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- H—ELECTRICITY
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Abstract
The invention discloses a kind of high frequency clock frequency detecting structural circuits for attack resistance chip, d type flip flop, three two inputs and door, delay unit D or door OR, 10 asynchronous resetting binary addition counter CT, 10 latch LATCH and 10 bit digital comparator DCMP including two concatenated rising edge triggerings；The d type flip flop and three two inputs and door that two rising edges trigger constitute gated clock structure；Delay unit D is connected in series for even number of inverters, controls delay time by adjusting the phase inverter number；The 10 bit digital comparator DCMP includes two 10 bit registers, i.e. upper frequency limit register H and lower-frequency limit register L；Delay unit D with or door OR constitute delay zero clearing structure.Using internal low-frequency clock as gate is counted, to high frequency clock cycles counting number within the set time, to push away to obtain high frequency clock frequency.When gained frequency is more than normal operating frequency range, alarm signal is generated.
Description
Technical field
The present invention relates to chip anti-attack fields more particularly to a kind of using internal low-frequency clock as the outer of count threshold
Portion's high frequency clock frequency detecting structure.
Background technique
In recent years, it is constantly suggested for the attack pattern of various information system and chip, so that information security receives
It seriously threatens.With the progress of microelectric technique, also it is evolving for the attack resistance technology of different attack patterns.The bottom of based on
The safety protection technique of layer hardware circuit has higher security level, has been increasingly becoming information system compared to software protecting
And the preferred option of chip anti-attack.
Some information security chips need to work under the driving of external input clock, the operating rate of internal circuit completely by
The clock determines.Attacker can be unfolded to attack by changing the frequency of input clock.Frequency is excessively high, can make chip work
It gets muddled, into abnormality[1].Underfrequency can make some attack detecting sensor response times in chip increase
Add, so that the sensor guard net that attacker has time enough to crack chip.By changing externally input clock frequency
Rate makes chip operation mistake occur, to obtain abnormal access approach, it is hidden to bring huge safety to information security chip
Suffer from.Therefore, it is necessary to a kind of frequency detecting structures, detect to external input frequency, once exceed operating frequency range, immediately
Alarm signal is generated, and is adopted an effective measure.
By patent retrieval, has Chinese patent and propose the frequency detecting structure for being used for attack resistance chip, patent
CN101968840B only elaborates frequency detecting structure from the angle of methodology, is not directed to specific circuit implementations[2]。
Patent CN103077346B realizes frequency detecting using analog form, is affected by technique, it is not easy to realize high-precision survey
Amount[3]。
[bibliography]
1. easy pine, Dai Zibin；SoC safety chip physical level attack method and security protection analysis [J], state's exoelectron member
Device, 2007 (5): 23-26.
2. summer army tiger, Xu Gongyi, Qian Zhiheng；A kind of chip anti-attack method [P] based on voltage detecting and frequency detecting,
Chinese patent: CN101968840B, 2012-9-26.
3. king new Asia, Wu Xiaoyong；A kind of chip anti-attack system and method [P] based on clock frequency detection, China is specially
Benefit: CN103077346B, 2015-7-22.
Summary of the invention
In view of the defects existing in the prior art, the present invention proposes that a kind of high frequency clock frequency suitable for attack resistance chip is examined
Slowdown monitoring circuit structure, portion is embedded in a low-frequency clock as gate is counted in the chip, carries out to external input high frequency clock frequency
Detection prevents attacker from carrying out frequency attack using external high frequency clock, it is ensured that attack resistance chip can be in suitable frequency model
Enclose interior normal work.
In order to solve the above-mentioned technical problem, a kind of high frequency clock frequency detecting for attack resistance chip proposed by the present invention
Structural circuit, a technical solution being achieved be, d type flip flop including two concatenated rising edges triggerings, three two
Input and door, delay unit D or door OR, 10 asynchronous resetting binary addition counter CT, 10 latch LATCH and 10
Bit digital comparator DCMP；Wherein, the d type flip flop of concatenated two rising edges triggering constitutes synchronous circuit；Two rising edges
The d type flip flop of triggering and three two inputs and door constitute gated clock structure；Delay unit D be even number of inverters connect and
At by adjusting phase inverter number control delay time；The 10 bit digital comparator DCMP includes two 10 bit registers,
That is upper frequency limit register H and lower-frequency limit register L；Delay unit D with or door OR constitute delay zero clearing structure；Outside mentions
The input signal of confession is high frequency clock CLKH, enables En, low-frequency clock CLKL；Internal signal is high-frequency signal CLKT to be measured, door
Control signal Gate, delay reset signal CLRG, gate high-frequency signal CLKG；Output signal is alarm signal A LARM；Above-mentioned each device
Connection relationship between part, between device and signal is as follows:
The d type flip flop of two rising edges triggering is respectively d type flip flop D1 and d type flip flop D2, and three two inputs are distinguished with door
For two inputs and door AND1, two inputs and the input of door AND2 and two and door AND3；The input terminal D phase of enabled En and d type flip flop D1
Even, the input terminal D of the in-phase output end Q and d type flip flop D2 of d type flip flop D1 are connected；Low-frequency clock CLKL and d type flip flop D1 and D
The input end of clock CLK of trigger D2 is connected；The in-phase output end Q of d type flip flop D2 with door AND1 input terminal A2 and with
The input terminal A3 of door AND2 is connected；It is connected with another input terminal A1 of door AND1 with high frequency clock CLKH；It is another with door AND2
One input terminal A4 is connected with low-frequency clock CLKL；It is connected with the output end B1 of door AND1 with the input terminal A5 with door AND3, with
The output end B2 of door AND2 is connected with the input terminal A6 with door AND3, the clock with the output end B3 of door AND3 as counter CT
Input signal is simultaneously connected with the input end of clock CP of 10 asynchronous resetting binary addition counter CT；With the output of door AND2
End B2 be connected with the input terminal A7 of delay unit D, the output end B4 of delay unit D with or door OR input terminal A9 is connected or door OR
Another input terminal A8 is connected with the output end B2 with door AND2；Or door OR output end B5 and 10 asynchronous resetting binary additions
The asynchronous resetting end Clr of counter CT is connected；10 output ports and 10 of 10 asynchronous resetting binary addition counter CT
10 input terminals of position latch LATCH, which correspond, to be connected；With the lock of the output end B2 of door AND2 and 10 latch LATCH
Control terminal G is deposited to be connected；10 output signals of 10 latch LATCH are defeated respectively as 10 of 10 bit digital comparator DCMP
Enter signal, and is connected one by one with the input terminal of 10 bit digital comparator DCMP；With the output end B2 and 10 bit digitals ratio of door AND2
Enabled input terminal E compared with device DCMP is connected, and the in-phase output end Q of d type flip flop D2 and 10 bit digital comparator DCMP are resetted and inputted
Rst is held to be connected；10 bit digital comparator DCMP export alarm signal A LARM.
A kind of high frequency clock frequency detecting structural circuit for attack resistance chip proposed by the present invention, is achieved
Another technical solution is, 10 bit digital comparator DCMP after 10 latch LATCH will be connected in above-mentioned technical proposal
10 bit digital arithmetic unit ALUs are replaced with, 10 bit digital arithmetic unit ALU output is f by measured frequencyH。
In addition, can be in high frequency clock CLKH and input terminal with door AND1 on the basis of above two technical solution
A frequency divider is connected between A1.
Compared with prior art, the beneficial effects of the present invention are:
The present invention is embedded in a low-frequency clock as gate is counted, in the height electricity of internal low-frequency clock by portion in the chip
During flat, counted to by the periodicity of measured frequency, then operating frequency range is seen if fall out by digital comparator, from
And realize digital wide range of frequencies measurement.Meanwhile low-frequency clock can also be used as emergency destruction clock, when frequency detecting to exception
When state, critical data is removed for driving chip.
The present invention uses Clock Gating Technique, reduces system power dissipation.Measurement accuracy and counting gate time length (low frequency
Clock high level width) it is related, measurement range is related with number of counter bits, by adjusting low-frequency clock frequency and counter position
Number, can flexibly change frequency measurement accuracy and measurement range.Pass through the high threshold and Low threshold in modification digital comparator
Register can flexibly modify alarm range.By the way of digitalized measuring frequency, chip area is small, low in energy consumption, to technique
Error is insensitive.
Detailed description of the invention
Fig. 1 is that the present invention realizes fixed range frequency detecting structural circuit figure；
Fig. 2 is the detection waveform figure of the structure of fixed range frequency detecting shown in Fig. 1；
Fig. 3 is that the present invention realizes wide range of frequencies detection structure circuit diagram；
Fig. 4 is the detection waveform figure of wide range of frequencies detection structure shown in Fig. 3.
Specific embodiment
Technical solution of the present invention is described in further detail in the following with reference to the drawings and specific embodiments, it is described specific
Embodiment is only explained the present invention, is not intended to limit the invention.
The present invention proposes a kind of for external input high frequency clock aiming at the problem that attack resistance chip is attacked vulnerable to frequency
Frequency measurement circuit, the circuit efficiently use internal low-frequency clock as count gate, to high frequency clock within the set time
Number of cycles counts, to push away to obtain high frequency clock frequency.When gained frequency is more than normal operating frequency range, alarm signal is generated
Number.
A kind of high frequency clock frequency detecting structural circuit for attack resistance chip proposed by the present invention, is achieved
One technical solution is the frequency detecting for fixed range, as shown in Figure 1, the structural circuit includes two concatenated rising edges
The d type flip flop of triggering, three two inputs and door, delay unit D or door OR, 10 asynchronous resetting binary addition counter CT,
10 latch LATCH and 10 bit digital comparator DCMP；Wherein, the d type flip flop of concatenated two rising edges triggering constitutes
Synchronous circuit；The d type flip flop and three two inputs and door that two rising edges trigger constitute gated clock structure；Delay unit D
It is connected in series for even number of inverters, controls delay time by adjusting the phase inverter number；The 10 bit digital comparator
DCMP includes two 10 bit registers, i.e. upper frequency limit register H and lower-frequency limit register L；Delay unit D and or door OR structure
At delay zero clearing structure.
The input signal provided outside the high frequency clock frequency detecting structural circuit is high frequency clock CLKH, enables En, is low
Frequency clock CLKL；The main signal provided inside the high frequency clock frequency detecting structural circuit is high-frequency signal CLKT to be measured, door
Control signal Gate, delay reset signal CLRG, gate high-frequency signal CLKG；The output of the high frequency clock frequency detecting structural circuit
Signal is alarm signal A LARM；Connection relationship between above-mentioned each device, between device and signal is as follows:
The d type flip flop of two rising edges triggering is respectively d type flip flop D1 and d type flip flop D2, and three two inputs are distinguished with door
For two inputs and door AND1, two inputs and the input of door AND2 and two and door AND3；The input terminal D phase of enabled En and d type flip flop D1
Even, the input terminal D of the in-phase output end Q and d type flip flop D2 of d type flip flop D1 are connected；Low-frequency clock CLKL and d type flip flop D1 and D
The input end of clock CLK of trigger D2 is connected；The in-phase output end Q of d type flip flop D2 with door AND1 input terminal A2 and with
The input terminal A3 of door AND2 is connected；It is connected with another input terminal A1 of door AND1 with high frequency clock CLKH；It is another with door AND2
One input terminal A4 is connected with low-frequency clock CLKL；It is connected with the output end B1 of door AND1 with the input terminal A5 with door AND3, with
The output end B2 of door AND2 is connected with the input terminal A6 with door AND3, the clock with the output end B3 of door AND3 as counter CT
Input signal is simultaneously connected with the input end of clock CP of 10 asynchronous resetting binary addition counter CT.
It is connected with the output end B2 of door AND2 with the input terminal A7 of delay unit D, the output end B4 of delay unit D and or door
OR input terminal A9 is connected or door OR another input terminal A8 is connected with the output end B2 with door AND2；Or door OR output end B5 with
The asynchronous resetting end Clr of 10 asynchronous resetting binary addition counter CT is connected.
10 output port Q of 10 asynchronous resetting binary addition counter CT9、Q8、Q7、Q6、Q5、Q4、Q3、Q2、Q1、
Q0With 10 input terminal C of 10 latch LATCH9、C8、C7、C6、C5、C4、C3、C2、C1、C0It corresponds and is connected；With door AND2
Output end B2 be connected with the latch control terminal G of 10 latch LATCH.10 output signal L of 10 latch LATCH9、
L8、L7、L6、L5、L4、L3、L2、L1、L0Respectively as 10 input signals of 10 bit digital comparator DCMP, and with 10 bit digitals
The input terminal D of comparator DCMP9、D8、D7、D6、D5、D4、D3、D2、D1、D0It is connected one by one；With the output end B2 of door AND2 and 10
The enabled input terminal E of digital comparator DCMP is connected, and the in-phase output end Q of d type flip flop D2 and 10 bit digital comparator DCMP are multiple
Position input terminal Rst is connected；10 bit digital comparator DCMP export alarm signal A LARM.
As shown in Figure 1, suitable low-frequency clock is selected according to measurement accuracy when using, then according to the highest of required measurement
Frequency values select the counter of suitable digit.Secondly, the settling time according to needed for latch input data adjusts delay unit D
Delay so that latch latches count value before counter O reset, while sufficient ratio is reserved for digital comparator again
Compared with the time.Finally, sampling ALARM output signal in low-frequency clock rising edge, effective alarm signal can be obtained.
In the present invention, 10 asynchronous resetting binary addition counter CT, wherein CP is input end of clock, and rising edge has
Effect；Clr is asynchronous resetting end, and low level is effective；Q9、Q8、Q7、Q6、Q5、Q4、Q3、Q2、Q1、Q0For 10 output ports, while
Represent counting output value, Q therein9For highest order.The latch control terminal G of 10 latch LATCH is also to latch control input
End, G failing edge latch data and low level are kept, and G is not latched when being high level, input terminal C9、C8、C7、C6、C5、C4、C3、C2、
C1、C0Input data through latch control output end L9、L8、L7、L6、L5、L4、L3、L2、L1、L0.In 10 bit digital comparator DCMP
Two 10 bit registers contained, i.e. upper frequency limit register H and lower-frequency limit register L.D9、D8、D7、D6、D5、D4、D3、D2、
D1、D0For the data input pin of the digital comparator, En is enabled input terminal, and low level is effective.Rst is the RESET input, low electricity
It is flat effective.
In the present invention, the first d type flip flop D1 and the second trigger D2 and three collectively form with door AND1, AND2, AND3
Gated clock structure.Enabled En is that frequency measurement controls signal, when it is high level, just can be carried out frequency measurement.D1 with
D2 synchronous circuit in series, enabled En is synchronous with low-frequency clock CLKL, obtain synchronous enabled signal Ena.Make En and low frequency
Clock is synchronous, avoid the En between low-frequency clock CLKL high period change and caused by error detection result.Meanwhile working as Ena
When signal is low level, high frequency clock CLKH and low-frequency clock CLKL are closed through the output with door AND1 and AND2, to keep away
Exempted from synchronous enabled Ena it is invalid when, subsequent conditioning circuit still has unnecessary clock to input, and causes power consumption penalty.High frequency clock CLKH
Pass through with synchronous enabled signal Ena and door AND1 phase and obtains high-frequency signal CLKT to be measured.Low-frequency clock CLKL with it is synchronous enabled
Signal Ena passes through and door AND2 phase and obtains gate-control signal Gate.High-frequency signal CLKT to be measured and gate-control signal Gate pass through with
Door AND3 phase and obtain gate high-frequency signal CLKG.Gating high-frequency signal CLKG is the high frequency to be detected letter by gate processing
Number.
In the present invention, delay unit D with or door OR constitute delay zero clearing structure.When gate-control signal Gate is turned by high level
When becoming low level or door OR input terminal A8 is directly low level by high level jump, due to delay unit D delay effect, A9
End does not change immediately or door OR output end does not change equally immediately.It is delayed by certain time, delay unit D
It is just low level by high level jump that output end B4, which is low level or door OR output end by high level jump,.Gate-control signal Gate
Later after a period of time, delay reset signal CLRG just changes, counter CT is just zeroed out operation after certain time-delay.
When gate-control signal Gate is changed into high level by low level or door OR input terminal A8 is directly high level by low level jump,
Or it is high level that door OR output end, which is equally directly jumped by low level,.Reset signal CLRG and gate-control signal Gate be delayed in the same time
Change, counter CT reset signal is invalid immediately.Delay zero clearing structure is avoided due to factors such as cabling delays, so that counter
The case where CT is reset immediately, and latch is not latched immediately due to delay, so that clear operation is relatively reliable.Delay unit D's
Delay time needs to be greater than cabling and is delayed, so that latch LATCH locks counter output valve before counter CT is reset
It deposits.
Frequency detecting architecture signals waveform diagram is as shown in Figure 2.Between the low period in the 1st low-frequency clock CLKL period, make
Energy signal En switchs to high level, and frequency detecting structure is started to work.Since synchronous circuit acts on, until on the 3rd CLKL period
Edge is risen, the synchronous enabled signal Ena synchronous with CLKL is obtained, frequency detecting structure starts to detect frequency.Third low-frequency clock
Between CLKL high period, gate-control signal Gate is high level, exports gate high-frequency signal CLKG to be measured with door AND3, the signal is defeated
Enter counter CT input end of clock CP, when arriving CLKG signal rising edge, counter adds 1.Due to gate-control signal
Gate is high level, i.e. latch LATCH latches control signal G input high level, and latch LATCH keeps pellucidity,
Counter CT output valve Q9、Q8、Q7、Q6、Q5、Q4、Q3、Q2、Q1、Q0Latch output L will directly be reached9、L8、L7、L6、L5、L4、
L3、L2、L1、L0.Since digital comparator enable end E inputs invalid high level, therefore digital comparator does not work, output terminals A LARM
It remains unchanged.Between low-frequency clock CLKL low period, gate-control signal Gate is low level, and CLKG keeps low level, counter
The input of CT input end of clock CP no signal, count value do not change.Gate-control signal Gate is lower the moment by height, latch
LATCH latching accumulator CT output valve, L9、L8、L7、L6、L5、L4、L3、L2、L1、L0It remains unchanged.Digital comparator DCMP is enabled
End E is effective low level, starts to work normally.Digital comparator DCMP reads input terminal D9、D8、D7、D6、D5、D4、D3、D2、D1、
D0Numerical value is compared with numerical value in upper frequency limit register H and lower-frequency limit register L respectively.Due to the 3rd CLKL period
CLKH frequency is normal between high period, so when ALARM signal export low level, alarm free.Postpone by certain time, CLRG
Low level, counter CT are reset.
At 4th CLKL period rising edge, CLRG high level, it is invalid that counter CT is reset, and starts to work normally.Due to
CLKH frequency is excessively high between 4 CLKL period high periods, between the period low period, after digital comparator DCMP is completed relatively,
ALARM signal will export high level, i.e. generation alarm signal.CLKH underfrequency between 5th CLKL period high period,
ALARM signal will also export high level alarm signal.Between 6th CLKL period low period, En is changed into low level, but due to
Synchronous circuit effect, until the 8th CLKL period rising edge, synchronous enabled signal Ena is just changed into low level, frequency detecting electricity
Road stops working.
By selecting suitable low-frequency clock frequency and number of counter bits, the detection of different frequency scope may be implemented.
Detection higher frequency if necessary, can be inserted into frequency divider in high frequency clock and between the input terminal A1 of door AND1, such as Fig. 3 institute
Show.Frequency occurrence is obtained if necessary, digital operation unit ALU can be added after latch, as shown in Figure 4.Assuming that low
Frequency clock frequency is fL, it is f by measured frequencyH, then counter CT count value is N=[fH/(2*fL)], therefore fH=2*fL* N, wherein
[] indicates floor operation.That is ALU needs to realize (2*fL* N) operation.
Protection scope of the present invention is not limited with above embodiment, those of ordinary skill in the art institute according to the present invention
Equivalent modification or variation made by disclosure should all be included in protection scope.
Claims (4)
1. a kind of high frequency clock frequency detecting structural circuit for attack resistance chip, it is characterised in that: concatenated including two
The d type flip flop of rising edge triggering, three two inputs and door, delay unit D or door OR, 10 asynchronous resetting binary addition meters
Number device CT, 10 latch LATCH and 10 bit digital comparator DCMP；Wherein, the d type flip flop of concatenated two rising edges triggering
Constitute synchronous circuit；The d type flip flop and three two inputs and door that two rising edges trigger constitute gated clock structure；Delay
Cells D is connected in series for even number of inverters, controls delay time by adjusting the phase inverter number；10 bit digital compares
Device DCMP includes two 10 bit registers, i.e. upper frequency limit register H and lower-frequency limit register L；Delay unit D and or door OR
Constitute delay zero clearing structure；
Input signal is high frequency clock CLKH, enables En, low-frequency clock CLKL, is all provided by outside；High-frequency signal to be measured
CLKT, gate-control signal Gate, delay reset signal CLRG, the gate all internal signals of high-frequency signal CLKG；Output signal is
Alarm signal A LARM；
Connection relationship between above-mentioned each device, between device and signal is as follows:
The d type flip flop of two rising edges triggering is respectively d type flip flop D1 and d type flip flop D2, and three two inputs and door are respectively two
Input and door AND1, two inputs and the input of door AND2 and two and door AND3；
Enabled En is connected with the input terminal D of d type flip flop D1, the input terminal D of the in-phase output end Q and d type flip flop D2 of d type flip flop D1
It is connected；Low-frequency clock CLKL is connected with the input end of clock CLK of d type flip flop D1 and d type flip flop D2；D type flip flop D2's is same mutually defeated
Outlet Q is connected with the input terminal A2 of door AND1 and with the input terminal A3 of door AND2；With another input terminal A1 of door AND1
It is connected with high frequency clock CLKH；It is connected with another input terminal A4 of door AND2 with low-frequency clock CLKL；With the output of door AND1
End B1 is connected with the input terminal A5 with door AND3, is connected with the output end B2 of door AND2 with the input terminal A6 with door AND3, with door
The output end B3 of AND3 as counter CT clock input signal and with 10 asynchronous resetting binary addition counter CT's
Input end of clock CP is connected；It is connected with the output end B2 of door AND2 with the input terminal A7 of delay unit D, the output of delay unit D
End B4 with or door OR input terminal A9 is connected or door OR another input terminal A8 is connected with the output end B2 with door AND2；Or door OR
Output end B5 is connected with the asynchronous resetting end Clr of 10 asynchronous resetting binary addition counter CT；
10 output ports of 10 asynchronous resetting binary addition counter CT and 10 input terminals of 10 latch LATCH
It corresponds and is connected；It is connected with the output end B2 of door AND2 with the latch control terminal G of 10 latch LATCH；
10 output signals of 10 latch LATCH respectively as 10 bit digital comparator DCMP 10 input signals, and
It is connected one by one with the input terminal of 10 bit digital comparator DCMP；With the output end B2 and 10 bit digital comparator DCMP of door AND2
Enabled input terminal E is connected, and the in-phase output end Q of d type flip flop D2 is connected with 10 bit digital comparator DCMP the RESET input Rst；
10 bit digital comparator DCMP export alarm signal A LARM.
2. being used for the high frequency clock frequency detecting structural circuit of attack resistance chip according to claim 1, which is characterized in that
High frequency clock CLKH and a frequency divider is connected between the input terminal A1 of door AND1.
3. a kind of high frequency clock frequency detecting structural circuit for attack resistance chip, it is characterised in that: concatenated including two
The d type flip flop of rising edge triggering, three two inputs and door, delay unit D or door OR, 10 asynchronous resetting binary addition meters
Number device CT, 10 latch LATCH and 10 bit digital arithmetic unit ALUs；Wherein, the D triggering of concatenated two rising edges triggering
Device constitutes synchronous circuit；The d type flip flop and three two inputs and door that two rising edges trigger constitute gated clock structure；Prolong
Shi DanyuanD is connected in series for even number of inverters, controls delay time by adjusting the phase inverter number；Delay unit D with or
Door OR constitutes delay zero clearing structure；
Input signal is high frequency clock CLKH, enables En, low-frequency clock CLKL, is all provided by outside；High-frequency signal to be measured
CLKT, gate-control signal Gate, delay reset signal CLRG, the gate all internal signals of high-frequency signal CLKG；Output signal is
Alarm signal A LARM；
Connection relationship between above-mentioned each device, between device and signal is as follows:
The d type flip flop of two rising edges triggering is respectively d type flip flop D1 and d type flip flop D2, and three two inputs and door are respectively two
Input and door AND1, two inputs and the input of door AND2 and two and door AND3；
Enabled En is connected with the input terminal D of d type flip flop D1, the input terminal D of the in-phase output end Q and d type flip flop D2 of d type flip flop D1
It is connected；Low-frequency clock CLKL is connected with the input end of clock CLK of d type flip flop D1 and d type flip flop D2；D type flip flop D2's is same mutually defeated
Outlet Q is connected with the input terminal A2 of door AND1 and with the input terminal A3 of door AND2；With another input terminal A1 of door AND1
It is connected with high frequency clock CLKH；It is connected with another input terminal A4 of door AND2 with low-frequency clock CLKL；With the output of door AND1
End B1 is connected with the input terminal A5 with door AND3, is connected with the output end B2 of door AND2 with the input terminal A6 with door AND3, with door
The output end B3 of AND3 as counter CT clock input signal and with 10 asynchronous resetting binary addition counter CT's
Input end of clock CP is connected；It is connected with the output end B2 of door AND2 with the input terminal A7 of delay unit D, the output of delay unit D
End B4 with or door OR input terminal A9 is connected or door OR another input terminal A8 is connected with the output end B2 with door AND2；Or door OR
Output end B5 is connected with the asynchronous resetting end Clr of 10 asynchronous resetting binary addition counter CT；
10 output ports of 10 asynchronous resetting binary addition counter CT and 10 input terminals of 10 latch LATCH
It corresponds and is connected；It is connected with the output end B2 of door AND2 with the latch control terminal G of 10 latch LATCH；
10 output signals of 10 latch LATCH respectively as 10 bit digital arithmetic unit ALUs 10 input signals, and
It is connected one by one with the input terminal of 10 bit digital arithmetic unit ALUs；With the output end B2 and 10 bit digital arithmetic unit ALUs of door AND2
Enabled input terminal E be connected, the in-phase output end Q of d type flip flop D2 and 10 bit digital arithmetic unit ALU the RESET input Rst phases
Even；The output of 10 bit digital arithmetic unit ALUs is f by measured frequencyH。
4. being used for the high frequency clock frequency detecting structural circuit of attack resistance chip according to claim 3, which is characterized in that
High frequency clock CLKH and a frequency divider is connected between the input terminal A1 of door AND1.
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| CN107809285B (en) * | 2017-11-15 | 2019-12-20 | 成都嘉纳海威科技有限责任公司 | Limiting amplifier for burst mode receiver |
| TWI700605B (en) * | 2018-12-28 | 2020-08-01 | 新唐科技股份有限公司 | Clock frequency attack detectiing system of secure chip |
| DE102019211570A1 (en) * | 2019-08-01 | 2021-02-04 | Robert Bosch Gmbh | Method and device for treating an anomaly in a control unit |
| CN113533942B (en) * | 2021-09-15 | 2021-11-30 | 上海矽久微电子有限公司 | Chip testing system and method |
| CN116566362A (en) * | 2023-07-11 | 2023-08-08 | 西安图为电气技术有限公司 | Double pulse generating circuit and double pulse generating method |
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| CN103034804A (en) * | 2012-12-11 | 2013-04-10 | 深圳国微技术有限公司 | Security chip and attack detection circuit thereof |
| CN103077346A (en) * | 2012-12-20 | 2013-05-01 | 深圳国微技术有限公司 | Clock frequency detection based chip anti-attack system and method |
| CN103677082A (en) * | 2013-12-20 | 2014-03-26 | 深圳国微技术有限公司 | Clock frequency monitoring circuit and method |
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