CN106206708A - 半导体装置 - Google Patents
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- CN106206708A CN106206708A CN201510297232.2A CN201510297232A CN106206708A CN 106206708 A CN106206708 A CN 106206708A CN 201510297232 A CN201510297232 A CN 201510297232A CN 106206708 A CN106206708 A CN 106206708A
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Abstract
根据一个实施方式，半导体装置(1)包括：第1半导体层(11)，设置在基板上；第2半导体层(12)，设置在第1半导体层(11)上，包含掺杂有p型杂质的氮化物半导体；第3半导体层(13)，设置在第2半导体层(12)上，包含非掺杂的氮化物半导体；第4半导体层(15)，设置在第3半导体层(13)上，包含氮化物半导体；以及第5半导体层(16)，设置在第4半导体层(15)上，包含带隙比第4半导体层(15)大的氮化物半导体。
Description
相关申请的交叉引用
本申请基于2015年01月21日提出的在先日本专利申请第2015－009588号并要求享受其优先权利益，并且在此通过引用包含其内容的全部。
技术领域
在此说明的实施方式整体上涉及半导体装置。
背景技术
开关电源、转换器等电路中使用开关元件、二极管等功率半导体元件，对于该功率半导体元件，要求高耐压以及低导通电阻。耐压与导通电阻之间存在由元件材料决定的权衡(trade off)关系，但通过将氮化物半导体或碳化硅(SiC)等宽带隙半导体作为元件材料来使用，与硅相比能够改善由材料决定的权衡关系，能够实现高耐压化以及低导通电阻化。
使用了GaN或AlGaN等氮化物半导体的元件具有优异的材料特性，因此能够实现高性能的功率半导体元件。特别在具有AlGaN/GaN的异质构造的HEMT(High Electron Mobility Transistor)中，由于在AlGaN层与GaN层的界面产生由极化带来的高浓度的二维电子气，因此能够实现低导通电阻。
发明内容
实施方式提供能够进一步减小泄露电流的半导体装置。
根据一个实施方式，半导体装置具备：第1半导体层，设置在基板上；第2半导体层，设置在所述第1半导体层上，包含掺杂有p型杂质的氮化物半导体；第3半导体层，设置在所述第2半导体层上，包含非掺杂氮化物半导体；第4半导体层，设置在所述第3半导体层上，包含氮化物半导体；以及第5半导体层，设置在所述第4半导体层上，包含带隙比所述第4半导体层大的氮化物半导体。
根据上述结构的半导体装置，能够提供能够进一步减小泄露电流的半导体装置。
附图说明
图1是实施方式的半导体装置的截面图。
图2是说明半导体装置的动作的示意图。
图3是半导体装置的能带图。
图4是说明漏极电压与泄露电流之间的关系的图表。
具体实施方式
以下，参照附图对实施方式进行说明。其中，附图是示意性的或者是概念性的，各附图的尺寸以及比率等不一定必须与现实的结构相同。以下所示的一些实施方式例示了用于将本发明的技术思想具体化的装置以及方法，本发明的技术思想并不通过构成部件的形状、构造、配置等来确定。另外，以下的说明中，对于具有相同功能以及结构的要素附加相同的附图标记，并仅在必要时进行重复说明。
[1]半导体装置的结构
图1是实施方式的半导体装置1的截面图。半导体装置1是使用作为化合物的氮化物半导体的氮化物半导体装置。此外，半导体装置1是场效应晶体管(FET)，具体而言是高电子迁移率晶体管(HEMT：HighElectron Mobility Transistor)。
基板10由例如以(111)面为主面的硅(Si)基板构成。作为基板10，可以使用碳化硅(SiC)、氮化镓(GaN)、磷化镓(GaP)、磷化铟(InP)、砷化镓(GaAs)或蓝宝石(Al2O3)等。此外，作为基板10，也可以使用包含绝缘层的基板。例如，作为基板10，可以使用SOI(SiliconOn Insulator)基板。
缓冲层(第1缓冲层)(第1半导体层)11设置在基板10上。缓冲层11具有对因形成在缓冲层11上的氮化物半导体层的晶格常数与基板10的晶格常数不同而产生的畸变进行缓和、并且对形成在缓冲层11上的氮化物半导体层的结晶性进行控制的功能。缓冲层11例如由AlXGa1－XN(0≤X≤1)构成。
缓冲层11也可以将组分比不同的多个AlXGa1－XN层叠而构成。在将缓冲层11以层叠构造构成的情况下，对层叠构造的组分比进行调整，以使该层叠构造所包含的多个层的晶格常数从夹着缓冲层11的上下层之中的下层的晶格常数向上层的晶格常数依次变化(增加)。
p型半导体层(第2半导体层)12设置在缓冲层11上。p型半导体层12作为构成具有整流作用的二极管(PN结二极管)Di的一方半导体层而发挥功能。p型半导体层12由掺杂有p型杂质的AlXInYGa1－(X+Y)N(0≤X＜1、0≤Y＜1、0≤X+Y＜1)构成。本实施方式中，p型半导体层12例如由掺杂有p型杂质的GaN构成。作为p型杂质，可以使用镁(Mg)等。
p型半导体层12由于在氮化物半导体中掺杂p型杂质而形成，因此与非掺杂GaN相比，其结晶性恶化。非掺杂是指有意地不掺杂杂质，例如，在制造过程等中进入的程度的杂质量是非掺杂的范畴。因此，从抑制p型半导体层12的结晶性对上层造成影响的观点来看，p型半导体层12的厚度优选较小。p型半导体层12的厚度例如为50nm左右。通过使p型半导体层12的厚度较小，能够抑制由于p型半导体层12的结晶性而p型半导体层12的上层的结晶性恶化。p型半导体层12的厚度被设定为比后述的缓冲层13的厚度小。
p型半导体层12的晶格常数被设定为比缓冲层11的晶格常数大。由此，能够减少缓冲层11向下方向呈凸形的翘曲，进而能够减少半导体装置1的翘曲。
缓冲层(第2缓冲层)(第3半导体层)13设置在p型半导体层12上。缓冲层13由非掺杂AlXInYGa1－(X+Y)N(0≤X＜1、0≤Y＜1、0≤X+Y＜1)构成。非掺杂AlInGaN层是n－型的导电型。本实施方式中，缓冲层13例如由非掺杂GaN构成。非掺杂的GaN也是n－型的导电型。
缓冲层13作为构成二极管Di的另一方半导体层发挥功能，并且具有对形成在缓冲层13上的氮化物半导体层的结晶性进行控制的功能。具体而言，缓冲层13抑制p型半导体层12的结晶缺陷向形成在缓冲层13上的氮化物半导体层转移。缓冲层13的厚度例如为2μm左右。
另外，也可以通过在缓冲层13中掺杂n型杂质而使缓冲层13为n型的导电型。作为n型杂质，可使用硅(Si)或锌(Zn)等。在该情况下，缓冲层13的n型杂质浓度被设定为比p型半导体层12的p型杂质浓度低。
高电阻层(中间层)(第6半导体层)14设置在缓冲层13上。高电阻层14具有提高半导体装置1的耐压的功能。高电阻层14的电阻被设定为比缓冲层13的电阻大。高电阻层14由掺杂有碳(C)的AlXInYGa1－(X+ Y)N(0≤X＜1、0≤Y＜1、0≤X+Y＜1)构成。本实施方式中，高电阻层14例如由掺杂有碳(C)的GaN(C－GaN)构成。高电阻层14的厚度例如为2μm左右。高电阻层14的电阻根据对半导体装置1而言优选的耐压而被适当设定。高电阻层14在本实施方式中不是必须的要件，只要能够允许耐压降低，则也可以不设置高电阻层14。
沟道层(第4半导体层)15设置在高电阻层14上。沟道层15是形成晶体管的沟道(电流路径)的层。沟道层15由AlXInYGa1－(X+Y)N(0≤X＜1、0≤Y＜1、0≤X+Y＜1)构成。沟道层15是非掺杂层，并且由结晶性良好的(高品质的)氮化物半导体构成。关于沟道层15，优选对制造工序进行控制以使杂质进一步变少来形成。本实施方式中，沟道层15例如由非掺杂GaN(也称为本征GaN)构成。沟道层15的厚度例如为1μm左右。
阻挡层(第5半导体层)16设置在沟道层15上。阻挡层16由AlXInYGa1－(X+Y)N(0≤X＜1、0≤Y＜1、0≤X+Y＜1)构成。阻挡层16由带隙比沟道层15的带隙大的氮化物半导体构成。本实施方式中，阻挡层16例如由非掺杂AlGaN构成。作为阻挡层16的AlGaN层中的Al的组分比例如为0.2左右。阻挡层16的厚度例如为30nm左右。
另外，构成半导体装置1的多个半导体层例如通过使用MOCVD(Metal Organic Chemical Vapor Deposition)法的外延生长而被依次形成。即，构成半导体装置1的多个半导体层由外延层构成。
在阻挡层16上相互离开地设有源极电极17以及漏极电极18。进而，在阻挡层16上且在源极电极17以及漏极电极18之间，与源极电极17以及漏极电极18离开地设有栅极电极19。
栅极电极19与阻挡层16进行肖特基接合。即，栅极电极19构成为包含与阻挡层16进行肖特基接合的材料。图1所示的半导体装置1为肖特基势垒型HEMT。作为栅极电极19，例如使用Au/Ni的层叠构造。“/”的左侧表示上层，右侧表示下层。另外，半导体装置1不限定于肖特基势垒型HEMT，也可以是在阻挡层16与栅极电极19之间存在栅极绝缘膜的MIS(Metal Insulator Semiconductor)型HEMT。
源极电极17与阻挡层16进行欧姆接触。同样，漏极电极18与阻挡层16进行欧姆接触。即，源极电极17以及漏极电极18分别构成为包含与阻挡层16进行欧姆接触的材料。作为源极电极17以及漏极电极18，例如使用Al/Ti的层叠构造。
在沟道层15与阻挡层16的异质结构造中，阻挡层16的晶格常数比沟道层15的晶格常数小，因此阻挡层16发生畸变。通过由该畸变带来的压电效应，在阻挡层16内产生压电极化，在沟道层15与阻挡层16的界面附近产生二维电子气(2DEG：two-dimensional electron gas)。该二维电子气成为源极电极17以及漏极电极18间的沟道。并且，通过由栅极电极19与阻挡层16的接合而产生的肖特基势垒，能够实现漏极电流的控制。此外，由于二维电子气具有高的电子迁移率，因此半导体装置1能够实现非常快的开关动作。
在此，上述的p型半导体层12和由n－型半导体层构成的缓冲层13构成二极管Di。二极管Di***在缓冲层11与高电阻层14之间。在对漏极电极18施加高电压、并且对基板10施加了接地电压VSS(0V)的情况下，二极管Di上被施加反向偏压。
p型半导体层12的载流子浓度被设定为比缓冲层13的载流子浓度高。此外，p型半导体层12的p型杂质浓度被设定为比缓冲层13的n型杂质浓度高。一般而言，二极管的耗尽层向PN结之中的载流子浓度低的半导体层侧延伸。本实施方式中，由于p型半导体层12的载流子浓度比缓冲层13的载流子浓度高，因此耗尽层向缓冲层13侧延伸。由此，能够避免耗尽层到达p型半导体层12的下侧的缓冲层11，结果能够抑制泄露电流变大。
p型半导体层12的载流子浓度被设定为1×1016cm－3以上且5×1019cm－3以下。载流子浓度的条件能够替换为杂质浓度的条件。即，p型半导体层12的p型杂质浓度被设定为1×1016cm－3以上且5×1019cm－3以下。
若p型半导体层12的载流子浓度小于1×1016cm－3，则p型半导体层12的载流子浓度有可能变得比缓冲层13的载流子浓度低。例如，在作为缓冲层13而使用了非掺杂GaN的情况下为5×1015以上且1×1016cm－3以下左右。因此，为了使p型半导体层12的载流子浓度比缓冲层13的载流子浓度高，p型半导体层12的载流子浓度优选为1×1016cm－3以上。
若p型半导体层12的载流子浓度比5×1019cm－3大，则在p型半导体层12内有可能产生未被活性化的p型杂质。即，若使p型半导体层12的载流子浓度比5×1019cm－3大，则p型半导体层12中的结晶性会恶化，另一方面载流子浓度不会增加。因此，p型半导体层12的载流子浓度优选为5×1019cm－3以下。
[2]动作
接着，对如上述那样构成的半导体装置1的动作进行说明。图2是说明半导体装置1的动作的示意图。
半导体装置1例如为常通型。半导体装置1例如被用作开关元件，漏极电极18上有时被施加200V～600V左右的高电压。对半导体装置1施加的电压越高，半导体装置1中产生的泄露电流、具体而言从漏极电极18向基板10的泄露电流越大。在半导体装置1动作时，基板10被施加0V。
在半导体装置1导通时，例如被施加栅极电压Vg＝0V、源极电压Vs＝0V、漏极电压Vd＝200V。此时，在漏极电极18以及源极电极17之间，经由在沟道层15形成的沟道而流过漏极电流。
在半导体装置1截止时，例如被施加栅极电压Vg＝－15V、源极电压Vs＝0V、漏极电压Vd＝200V。此时，在栅极电极19的下方延伸的耗尽层的厚度得到控制，漏极电流被切断。
如上所述，p型半导体层12和由n－型半导体层构成的缓冲层13构成二极管Di。构成二极管Di的p型半导体层12以及缓冲层13之中，p型半导体层12为阳极侧，缓冲层13为阴极侧。
在半导体装置1的截止状态中，漏极电极18被施加高电压，基板10被施加0V。此时，二极管Di被施加反向偏压。因此，二极管Di减小流过漏极电极18以及基板10之间的泄露电流。具体而言，若向漏极电极18施加高电压，则与来自漏极电极18的电场的扩展相应地，缓冲层13耗尽。若半导体装置1为截止状态，则由于沟道耗尽而横向(漏极－源极间)的泄漏路径消失，横向的泄露电流减小。此外，通过构成二极管Di的PN结的势垒电位，纵向(漏极－基板间)的泄露电流减小。
另外，在半导体装置1的导通状态下，几乎不产生从漏极电极18向基板10的泄露电流。但是，若漏极电压进一步变大，则有可能产生从漏极电极18向基板10的泄露电流，但在这样的状况中，二极管Di也能够减小从漏极电极18向基板10的泄露电流。
图3是半导体装置1的能带图。图3的横轴对应于从缓冲层11到阻挡层16为止的厚度，纵轴表示能量(eV)。图3的Ev表示价电子带的上端的能级，Ec表示导带的下端的能级。图3是漏极电压Vd＝9V、对基板施加了0V的情况下的实验结果。
从图3可知，在对二极管Di施加了反向偏压的情况下，在p型半导体层12以及缓冲层13所形成的PN结的界面，能量势垒(势垒电位)变高。即，反向偏压越大，二极管Di的耗尽层的厚度变得越大，因此通过二极管Di可减小纵向的泄露电流。
图4是说明漏极电压与泄露电流之间的关系的图表。图4是在对漏极电极18与基板10的2端子间施加了漏极电压的情况下对从漏极电极18向基板10流过的泄露电流进行测定而得到的结果。此时，对基板10施加0V。图4的横轴表示漏极电压(V)，纵轴表示泄露电流(A)。图4的纵轴中的“E”意味着以10为基数(底)的指数标记。此外，图4中示出了具备二极管Di的本实施方式和不具备二极管Di的比较例(即，从图1中删除了p型半导体层12的结构)的图表。
从图4可知，通过将在施加了漏极电压的状态下被施加反向偏压的二极管Di***在缓冲层11与高电阻层14之间，能够减小从漏极电极18向基板10流过的泄露电流。另外，关于二极管Di的反向偏压的阈值(击穿电压)，能够根据使用半导体装置1的环境以及动作条件来任意设定。
[3]效果
如以上详细叙述的那样，在本实施方式中，半导体装置1在缓冲层11与高电阻层14(或沟道层15)之间***p型半导体层12和由n－型半导体层构成的缓冲层13。p型半导体层12以及缓冲层13构成二极管Di。并且，在对漏极电极18施加了高电压的情况下，二极管Di被施加反向偏压。
因而，根据本实施方式，在半导体装置1动作时，能够减小从漏极电极18向基板10流过的泄露电流。由此，能够实现泄露电流较小的半导体装置1，因此能够减小半导体装置1的功耗。
此外，p型半导体层12的载流子浓度被设定为比缓冲层13的载流子浓度高。因此，能够控制为二极管Di的耗尽层向缓冲层13侧延伸，所以能够防止耗尽层到达p型半导体层12之下的缓冲层11。由此，在半导体装置1的动作电压变高的情况下也能够减小泄露电流。
此外，在缓冲层13与沟道层15之间设有电阻比缓冲层13大的高电阻层14。高电阻层14例如构成为包含掺杂有碳(C)的氮化物半导体。由此，能够使半导体装置1更加高耐压化。
本申请说明书中，“层叠”除了相互相接而重叠的情况以外，还包括在中间***其他层而重叠的情况。此外，“设置在…上”，除了直接相接而设置的情况以外，该包括在中间***其他层而设置的情况。
说明了本发明的一些实施方式，但这些实施方式是作为例来提示的，并没有要限定发明的范围。这些新的实施方式能够以其他多种形态实施，在不脱离发明的主旨的范围内能够进行各种省略、替换、变更。这些实施方式及其变形包含于发明的范围及主旨，并且包含于权利要求书所记载的发明及其等价范围。
Claims (8)
1.一种半导体装置，其特征在于，具备：
第1半导体层，设置在基板上；
第2半导体层，设置在所述第1半导体层上，包含掺杂有p型杂质的氮化物半导体；
第3半导体层，设置在所述第2半导体层上，包含非掺杂的氮化物半导体；
第4半导体层，设置在所述第3半导体层上，包含氮化物半导体；以及
第5半导体层，设置在所述第4半导体层上，包含带隙比所述第4半导体层大的氮化物半导体。
2.如权利要求1所述的半导体装置，其特征在于，
所述第2半导体层的载流子浓度比所述第3半导体层的载流子浓度高。
3.如权利要求1或2所述的半导体装置，其特征在于，
所述第2半导体层的载流子浓度为1×1016cm－3以上且5×1019cm－3以下。
4.如权利要求1或2所述的半导体装置，其特征在于，
所述第2半导体层的厚度比所述第3半导体层的厚度小。
5.如权利要求1或2所述的半导体装置，其特征在于，
所述第2半导体层包含由AlXInYGa1－(X+Y)N构成的材料，其中，0≤X＜1，0≤Y＜1，0≤X+Y＜1。
6.如权利要求1或2所述的半导体装置，其特征在于，
所述第3半导体层包含由AlXInYGa1－(X+Y)N构成的材料，其中，0≤X＜1，0≤Y＜1，0≤X+Y＜1。
7.如权利要求1或2所述的半导体装置，其特征在于，
还具备第6半导体层，该第6半导体层设置在所述第3半导体层与所述第4半导体层之间，电阻比所述第3半导体层大。
8.如权利要求7所述的半导体装置，其特征在于，
所述第6半导体层包含含有碳的氮化物半导体。
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| WO2018182633A1 (en) * | 2017-03-30 | 2018-10-04 | Intel Corporation | Interlayers in selective area growth of gallium nitride (gan) based structures |
| US10483354B2 (en) * | 2018-01-30 | 2019-11-19 | Kabushiki Kaisha Toshiba | Nitride semiconductor device |
| WO2020228018A1 (zh) * | 2019-05-16 | 2020-11-19 | 苏州晶湛半导体有限公司 | 一种半导体结构的制备方法 |
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| US20020094002A1 (en) * | 1999-07-16 | 2002-07-18 | Hiroshi Amano | Nitride semiconductor layer structure and a nitride semiconductor laser incorporating a portion of same |
| CN103794608A (zh) * | 2012-10-26 | 2014-05-14 | 三菱电机株式会社 | 单片集成电路 |
| US20140197418A1 (en) * | 2013-01-16 | 2014-07-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure having sets of iii-v compound layers and method of forming the same |
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| US20020094002A1 (en) * | 1999-07-16 | 2002-07-18 | Hiroshi Amano | Nitride semiconductor layer structure and a nitride semiconductor laser incorporating a portion of same |
| CN103794608A (zh) * | 2012-10-26 | 2014-05-14 | 三菱电机株式会社 | 单片集成电路 |
| US20140197418A1 (en) * | 2013-01-16 | 2014-07-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure having sets of iii-v compound layers and method of forming the same |
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| WO2023115701A1 (zh) * | 2021-12-22 | 2023-06-29 | 中国科学院苏州纳米技术与纳米仿生研究所 | 可降低泄露电流的iii族氮化物晶体管结构及其制作方法 |
| US11810910B2 (en) | 2021-12-22 | 2023-11-07 | Suzhou Institute Of Nano-Tech And Nano-Bionics (Sinano) , Chinese Academy Of Sciences | Group III nitride transistor structure capable of reducing leakage current and fabricating method thereof |
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