CN106206620B - Thin-film transistor array base-plate and preparation method thereof and display device - Google Patents
Thin-film transistor array base-plate and preparation method thereof and display device Download PDFInfo
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- CN106206620B CN106206620B CN201610802170.0A CN201610802170A CN106206620B CN 106206620 B CN106206620 B CN 106206620B CN 201610802170 A CN201610802170 A CN 201610802170A CN 106206620 B CN106206620 B CN 106206620B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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Abstract
The invention discloses a kind of thin-film transistor array base-plate and preparation method thereof and display device, method includes: to carry out patterned process to the polycrystalline silicon membrane being formed on substrate using first of optical cover process；Patterned process is carried out to the first metal layer, second insulating layer and the second metal layer on the substrate for being sequentially formed at patterned polysilicon silicon film and not covered by polycrystalline silicon membrane using second optical cover process；Using third road optical cover process to be formed in second insulating layer, the third insulating layer in second metal layer and on the first uncovered insulating layer carries out patterned process；Patterned process is carried out to the third metal layer being formed in contact hole and on third insulating layer using the 4th optical cover process；Pixel confining layer and wall are prepared on third metal layer and uncovered third insulating layer using the 5th optical cover process.It only needs 5 optical cover process that the preparation of array substrate can be completed, and effectively increases the preparation efficiency of array substrate, reduces preparation cost.
Description
Technical field
The present invention relates to field of display technology, more particularly to a kind of thin-film transistor array base-plate and preparation method thereof and
Display device.
Background technique
Currently, in field of display technology, liquid crystal display (Liquid Crystal Display, LCD) and organic light emission
The flat panel displays such as diode display (Organic Light Emitting Diode, OLED) gradually replace CRT
Display.Wherein, OLED have self-luminous, luminous efficiency are high, the response time is short, clarity and contrast are high, nearly 180 ° of visual angles,
Use temperature range is wide, the advantages such as Flexible Displays and large area total colouring can be achieved, it has also become currently used display device.
OLED usually by thin-film transistor array base-plate and is electrically excited photosphere and forms selfluminous element.But it is traditional thin
Film transistor array substrate preparation process complex process, especially in light shield processing step, it usually needs 8 or more light shield
Technique.So many light shield processing step, so that process equipment is also just more, preparation time is also grown, and film has thus been significantly affected
The preparation efficiency and preparation cost of transistor (TFT) array substrate, cause thin-film transistor array base-plate preparation efficiency lower, are prepared into
This is higher.
Summary of the invention
Based on this, it is necessary to be led for light shield processing step is more in traditional thin-film transistor array base-plate preparation process
Cause its preparation efficiency lower, the higher problem of preparation cost, provide a kind of thin-film transistor array base-plate and preparation method thereof and
Display device.
A kind of thin-film transistor array base-plate preparation method that purpose provides to realize the present invention, includes the following steps:
Polycrystalline silicon membrane is prepared on substrate using plated film and crystallization process, and using first of optical cover process to described more
Crystal silicon film layer carries out patterned process, obtains patterned polysilicon silicon film；
In the patterned polysilicon silicon film and first is not sequentially formed absolutely on substrate that the polycrystalline silicon membrane covers
Edge layer, the first metal layer, second insulating layer and second metal layer, and using second optical cover process to the first metal layer,
The second insulating layer and the second metal layer carry out patterned process, form the area TFT and capacitive region of interval pre-determined distance；
In the second insulating layer and the second metal layer after patterned process and uncovered described
Third insulating layer is formed on one insulating layer, and patterned process is carried out to the third insulating layer using third road optical cover process,
Contact hole is formed in the third insulating layer；
In the contact hole on the third insulating layer formed third metal layer, and use the 4th optical cover process pair
The third metal layer carries out patterned process, formed the area TFT source electrode and drain electrode and with the source electrode or drain electrode phase
The anode of the first electrode as Organic Light Emitting Diode even；
Using the third metal layer of the 5th optical cover process after patterned process and not by the third metal layer
Preparation forms patterned pixel confining layer and wall on the third insulating layer of covering, obtains thin film transistor (TFT) array base
Plate.
In one of the embodiments, it is described using second optical cover process to the first metal layer, it is described second absolutely
Edge layer and the second metal layer carry out patterned process, include the following steps:
Yellow light technique is carried out using intermediate tone mask, formed in the second metal layer be spaced the pre-determined distance and
The different photoresist figure layer of thickness；
By multistep etching-ashing-etching technics to the photoresist figure layer, the second metal layer, described second
Insulating layer and the first metal layer perform etching, and remove the photoresist, form the TFT for being spaced the pre-determined distance
Area and the capacitive region；
It wherein, include the first metal layer that is sequentially formed on first insulating layer in the area TFT and described
Second insulating layer；It include the first metal layer being sequentially formed on first insulating layer, described the in the capacitive region
The first metal layer, the second metal layer is completely covered in two insulating layers and the second metal layer, the second insulating layer
Part covers the second insulating layer.
In one of the embodiments, it is described using second optical cover process to the first metal layer, it is described second absolutely
Further include following steps after edge layer and the second metal layer carry out patterned process:
Using the first metal layer as exposure mask, the polycrystalline silicon membrane not covered by the first metal layer is carried out
Impurity ion is injected in autoregistration.
In one of the embodiments, it is described in the contact hole with third metal layer is formed on the third insulating layer
Later, further include the steps that forming metal oxide layer on the third metal layer.
The third metal using the 5th optical cover process after patterned process in one of the embodiments,
Layer and by the third metal layer cover the third insulating layer on preparation form patterned pixel confining layer and interval
Layer, includes the following steps:
It is not covered by the third metal layer using the third metal layer of the coating process after patterned process and
Photosensitive material layers are coated on the third insulating layer；
The photosensitive material layers are exposed using intermediate tone mask, and form different-thickness distribution after development
The pixel confining layer and wall.
Correspondingly, the present invention also provides a kind of thin-film transistor array base-plate, it is brilliant using as above any film
It is prepared by body pipe array substrate preparation method, comprising:
Substrate；
It is formed on the substrate and carries out patterned polycrystalline silicon membrane；
It is formed in first on the patterned polycrystalline silicon membrane and on the substrate not covered by the polycrystalline silicon membrane
Insulating layer；Wherein, first insulating layer includes the area TFT and capacitive region, the area TFT and the capacitive region interval it is default away from
From；
It is sequentially formed on first insulating layer and is located at the grid and second insulating layer in the area TFT, and successively
It is formed on first insulating layer and is located at capacitor bottom crown, second insulating layer and the capacitor top crown of the capacitive region；Its
In, the capacitor top crown is formed in the part of the surface of the second insulating layer；
The third insulation being formed on the second insulating layer, the capacitor top crown and the first uncovered insulating layer
Layer；It wherein, include multiple contact holes in the third insulating layer, multiple contact holes are extended through to the polycrystalline silicon membrane table
Face, capacitor bottom crown surface and capacitor top crown surface；
The sun for forming source electrode in the contact hole, draining and being formed on the uncovered third insulating layer
Pole；Wherein, the surface of third insulating layer described in the anode covering part, and be connected with the source electrode or the drain electrode；
The pixel confining layer and wall being sequentially formed on the uncovered third insulating layer；Wherein, the picture
Plain confining layers cover a part of the anode and expose most of region of the anode.
The grid, the capacitor bottom crown and the capacitor top crown are using identical in one of the embodiments,
Metal or metal alloy material prepares to be formed.
In one of the embodiments, the source electrode, the drain electrode and the anode using identical metal material and/or
Metal oxide materials prepare to be formed simultaneously.
The material of first insulating layer is at least one of silica and silicon nitride in one of the embodiments,；
The material of the second insulating layer and the material of the third insulating layer are silicon nitride, silica and silicon oxynitride
At least one of.
Correspondingly, the present invention also provides a kind of display devices, comprising:
As above any thin-film transistor array base-plate；
The organic luminous layer being formed on the thin-film transistor array base-plate；
The cathode layer as Organic Light Emitting Diode second electrode being formed on the organic luminous layer.
Above-mentioned thin-film transistor array base-plate preparation method, after forming patterned polysilicon silicon film on substrate,
Patterned the first metal layer and second metal layer are formed using one of optical cover process, while also being formed by one of optical cover process
Pixel confining layer and wall, so that traditional 8 or more light shield technique is effectively shortened to 5, it is final only to use 5
The preparation of thin-film transistor array base-plate can be completed in optical cover process, effectively increases the preparation effect of thin-film transistor array base-plate
Rate, while also reducing preparation cost.
Detailed description of the invention
Fig. 1 a is after forming polycrystalline silicon membrane on substrate using thin-film transistor array base-plate preparation method of the invention
The schematic diagram of the section structure；
Fig. 1 b is to be carried out using thin-film transistor array base-plate preparation method of the invention to the polycrystalline silicon membrane on substrate
The schematic diagram of the section structure after patterned process；
Fig. 2 a is the polysilicon film using thin-film transistor array base-plate preparation method of the invention after patterned process
The schematic diagram of the section structure after sequentially forming the first insulating layer, the first metal layer, second insulating layer and second metal layer on layer；
Fig. 2 b is that photoresist is formed in second metal layer using thin-film transistor array base-plate preparation method of the invention
The schematic diagram of the section structure after figure layer；
Fig. 2 c is using thin-film transistor array base-plate preparation method of the invention to the substrate after forming photoresist figure layer
In film layer carry out first step etching after the schematic diagram of the section structure；
Fig. 2 d is using thin-film transistor array base-plate preparation method of the invention to the substrate after completing first step etching
In film layer carry out cineration technics after the schematic diagram of the section structure；
Fig. 2 e is using thin-film transistor array base-plate preparation method of the invention on the substrate after completing cineration technics
Film layer carry out second step etching after the schematic diagram of the section structure；
Fig. 2 f is using thin-film transistor array base-plate preparation method of the invention to the substrate after completing second step etching
In photoresist figure layer removed after the schematic diagram of the section structure；
Fig. 3 a is the substrate using thin-film transistor array base-plate preparation method of the invention after stripping photoresist figure layer
The middle the schematic diagram of the section structure formed after third insulating layer；
Fig. 3 b is to be carried out at patterning using thin-film transistor array base-plate preparation method of the invention to third insulating layer
The schematic diagram of the section structure after reason；
Fig. 4 a is the third insulation using thin-film transistor array base-plate preparation method of the invention after patterned process
The schematic diagram of the section structure after forming third metal layer on layer；
Fig. 4 b is to be carried out at patterning using thin-film transistor array base-plate preparation method of the invention to third metal layer
The schematic diagram of the section structure after reason；
Fig. 5 is the third metal using thin-film transistor array base-plate preparation method of the invention after patterned process
Layer and the section after patterned pixel confining layers and wall is not formed by preparation on third insulating layer that third metal layer covers
Structural schematic diagram.
Specific embodiment
To keep technical solution of the present invention clearer, the present invention is made below in conjunction with drawings and the specific embodiments further detailed
It describes in detail bright.
It is adopted first referring to Fig. 1 a as a specific embodiment of thin-film transistor array base-plate preparation method of the invention
Polycrystalline silicon membrane 103 is formed on the substrate 101 with plated film and crystallization process.Specifically, first using coating process in substrate 101
Upper preparation amorphous silicon film layer, and then amorphous silicon is converted into polysilicon using crystallization processes such as laser crystallizations again.Wherein, substrate
101 can be any one in glass substrate, thin metal matrix plate and flexible plastic substrates.Also, used by this step
Coating process can be any one of physical gas-phase deposition and chemical vapor deposition process.Meanwhile it depositing on the substrate 101
When forming polycrystalline silicon membrane 103, one layer of buffer layer 102 can be also first deposited on the substrate 101, and then is sunk on buffer layer 102 again
Product forms amorphous silicon film layer, finally again by quasi-molecule laser annealing or solid phase annealing or other annealing process to amorphous silicon film layer
It anneals, so that amorphous silicon film layer crystallization conversion is polycrystalline silicon membrane 103.
Herein it should be noted that the buffer layer 102 deposited on the substrate 101 can be silicon nitride (SiNx), silica
(SiOx) and silicon oxynitride (SiNxOy) at least one of material.Also, the amorphous silicon film of formation is deposited on buffer layer 102
The thickness of layer can be 40nm -70nm.
Referring to Fig. 1 b, after deposition forms polycrystalline silicon membrane 103 on the substrate 101, first of light shield system is then used at this time
Journey carries out patterned process to polycrystalline silicon membrane 103, to obtain patterned polysilicon silicon film 103.Wherein, in this step,
Specifically (Strip) technique can be removed by yellow light (Photo) technique, etching (Etch) technique and wet process, obtained patterned more
Crystal silicon film layer 103.Patterned process is carried out to polycrystalline silicon membrane 103 by first of optical cover process, realizes the area TFT and capacitor
The subregion in area.
A referring to fig. 2 is existed after forming patterned polysilicon silicon film 103 on the substrate 101, and then again using coating process
On polycrystalline silicon membrane 103 and the first insulating layer 104, the first gold medal are not sequentially formed on substrate 101 that polycrystalline silicon membrane 103 covers
Belong to layer 105, second insulating layer 106 and second metal layer 107.It should be pointed out that preparation the first insulating layer 104, the first metal
Coating process used by layer 105, second insulating layer 106 and second metal layer 107 equally can for physical gas-phase deposition or
Chemical vapor deposition process.Wherein, the first insulating layer 104 is used as gate insulating layer, can in silica and silicon nitride at least
It is a kind of.E referring to fig. 2, the first metal layer 105 then include the grid 105a for being located at the area TFT in array substrate 101, are located at capacitive region
Capacitor bottom crown 105b and grid wiring (not shown).Also, the first metal layer 105 preferably using Mo, MoW,
At least one of the metal or metal alloy such as Al, Cu material is prepared.Second insulating layer 106 then preferably uses silicon nitride, oxygen
At least one of SiClx and silicon oxynitride.E referring to fig. 2, second metal layer 107, which specifically includes, is located at electricity in array substrate 101
Hold the capacitor top crown 107a and wiring (not shown) in area, material is identical as the first metal layer 105.
When forming the first insulating layer 104, the first metal layer 105, second insulating layer 106 and on polycrystalline silicon membrane 103
After two metal layers 107, that is, second optical cover process can be used and carry out patterned the first metal layer 105 and second metal layer
107 preparation, to realize the grid 105a in the area TFT, the capacitor bottom crown 105b in capacitive region and capacitor top crown 107a
Preparation.
Specifically, b is formed in second metal layer 107 firstly, carrying out yellow light technique using intermediate tone mask referring to fig. 2
It is spaced pre-determined distance and the different photoresist figure layer of thickness.Herein, it should be noted that being formed by photoresist figure layer includes position
In the area TFT and be formed in second metal layer 107 the first photoresist figure layer 108a, positioned at capacitive region and be formed in the second metal
The second relatively thin photoresist figure layer 108b of thickness and it is located at capacitive region on layer 107 and is formed in second metal layer 107
The thicker third photoresist figure layer 108c of thickness.That is, the second photoresist figure layer 108b and third photoresist figure layer 108c are respectively positioned on
Capacitive region is simultaneously formed in second metal layer 107, unlike, the thickness of the second photoresist figure layer 108b is less than third photoresist
The thickness of figure layer 108c.
In turn, c referring to fig. 2, photoresist figure layer and second metal layer 107, second insulating layer 106 and first to formation
Metal layer 105 carries out full etching technique, will not be photo-etched second metal layer 107, the second insulating layer 106 and the of the covering of glue figure layer
The removal of one metal layer 105, forms the area TFT and capacitive region of preset interval.Wherein, the first metal layer 105 positioned at the area TFT is
Grid 105a in thin-film transistor array base-plate 100, the first metal layer 105 positioned at capacitive region are capacitor bottom crown 105b,
Second metal layer 107 positioned at capacitive region is capacitor top crown 107a.
Then, d referring to fig. 2, the whole for being located at the area TFT using cineration technics removal and being covered in second metal layer 107
First photoresist figure layer 108a, positioned at capacitive region and be covered in second metal layer 107 all the second photoresist figure layer 108b,
And the part third photoresist figure layer 108c for being located at capacitive region and being covered in second metal layer 107.Wherein, by grey chemical industry
Remaining part third photoresist figure layer 108c is the 4th photoresist figure layer 108d shown in Fig. 2 d after skill.
E referring to fig. 2, and then continue using etching technics to being deposited in second insulating layer 106, and not by the 4th photoresist
The second metal layer 107 of figure layer 108d covering performs etching, to remove the second gold medal not covered by the 4th photoresist figure layer 108d
Belong to layer 107.
Finally, f, then the 4th photoresist figure that will be covered in second metal layer 107 by wet stripping techniques referring to fig. 2
The photoresist lift off of layer 108d, to obtain 107 graphic structure of final required the first metal layer 105 and second metal layer.
At this point, capacitor plate (including the capacitor of the area TFT grid 105a and capacitive region in thin-film transistor array base-plate 100 can be completed
Bottom crown 105b and capacitor top crown 107a) preparation.Herein, it should be noted that the preset interval formed in this step
The area TFT and capacitive region in, include the first metal layer 105 that is sequentially formed on the first insulating layer 104 in the area TFT (that is, to be thin
Grid 105a in film transistor array substrate 100) and second insulating layer 106；It include being sequentially formed in first absolutely in capacitive region
The first metal layer 105 (that is, for capacitor bottom crown 105b in thin-film transistor array base-plate 100) in edge layer 104, the second insulation
106 (capacitor dielectric layer) of layer and second metal layer 107 (capacitor top crown 107a).Also, second insulating layer 106 is completely covered
One metal layer 105,107 part of second metal layer cover second insulating layer 106.
Further, after preparing the area TFT and capacitive region to form predeterminable area on the substrate 101, in order to improve
The electric conductivity of the corresponding polycrystalline silicon membrane 103 in source electrode and drain electrode region in the area TFT, it is preferred that using patterned first gold medal
Belong to layer 105 be used as exposure mask, to the corresponding polycrystalline silicon membrane in source electrode and drain electrode region 103 carry out autoregistration injection impurity from
Son.Such as: carrying out P doping, generally use borine (B2H6) it is used as unstrpped gas.
Referring to Fig. 3 a, when forming patterned the first metal layer 105 and the second metal on the substrate 101 through the above steps
After layer 107, and then the first insulating layer 104, second insulating layer 106 and the second metal using coating process after patterned process
Preparation forms third insulating layer 109 on layer 107.Wherein, third insulating layer 109 preferably uses silicon nitride, silica and nitrogen oxidation
The preparation of at least one of silicon material.Embodiment shown in Fig. 3 a is to use third insulating layer 109 prepared by two kinds of materials.
In turn, referring to Fig. 3 b, after forming third insulating layer 109 using coating process, then continue using third road light shield
Processing procedure carries out patterned process to third insulating layer 109, to form contact hole 1091 in third insulating layer 109.Wherein,
Yellow light technique, etching technics and wet stripping techniques specifically can be used to prepare to form contact hole 1091.
After forming contact hole 1091 in third insulating layer 109, the system of electrode (source electrode, drain electrode and anode) can be carried out
It is standby.Specifically, a referring to fig. 4, is formed firstly, being deposited in contact hole 1091 and on third insulating layer 109 using coating process
Third metal layer 110.Herein, it should be noted that third metal layer 110 specifically can by Ti, Mo, Al, Cu and Ag at least
A kind of formation.Such as: third metal layer 110 can form Ti/Al/Ti or Mo/Al/Mo multi-layer metal structure.Likewise it is preferred that,
In order to increase surface work function, it can also be deposited on third metal layer 110 and form one layer of metal oxide layer (not shown).
Such as: ITO or IZO.
In turn, b referring to fig. 4, after forming third metal layer 110 in contact hole 1091 and on third insulating layer 109, i.e.,
The 4th optical cover process can be used, patterned process is carried out to third metal layer 110, forms the source electrode 110a positioned at TFT and drain electrode
110b, and the anode 110c as Organic Light Emitting Diode first electrode.Herein, it should be noted that source electrode 110a or leakage
Pole 110b and anode 110c prepares to be formed simultaneously in this step, and source electrode 110a or drain electrode 110b can be used as the sun of capacitive region
Pole 110c.That is, patterning third metal layer 110 required for being formed using yellow light technique, etching technics and wet stripping techniques.
Wherein, anode 110c and source electrode 110a, drain electrode 110b and signal line wiring (not shown) are by same film layer (that is, the
Three metal layers 110) it constitutes.Its by by third metal layer 110 be formed simultaneously source electrode 110a, drain electrode 110b and anode 110c and
Signal line wiring realizes merging for source electrode 110a or drain 110b and anode 110c, thus compared to traditional array substrate
Prepared respectively in 101 preparation process source electrode 110a, drain 110b and anode 110c mode effectively reduce optical cover process, thus
Reach the preparation time for saving thin-film transistor array base-plate 100, improves preparation efficiency, while also reducing and being prepared into
This.
Finally, completing source electrode 110a, drain electrode 110b and sun when preparing simultaneously by using third metal layer 110 referring to Fig. 5
After the 110c of pole, then using third metal layer 110 of the 5th optical cover process after patterned process and not by third metal layer 110
Preparation forms patterned pixel confining layer 111 and wall 112 on the third insulating layer 109 of covering, to finally obtain thin
Film transistor array substrate 100.
Wherein, in a specific embodiment of thin-film transistor array base-plate preparation method of the invention, pixel confining layer
111 and wall 112 can be prepared and be formed by light-sensitive material.Specifically, firstly, using using coating process after patterned process
Third metal layer 110 and do not coated photosensitive material layers on third insulating layer 109 that third metal layer 110 covers.In turn,
It recycles intermediate tone mask to be exposed photosensitive material layers, and forms the pixel restriction of different-thickness distribution after development
Layer 111 and wall 112.
Thin-film transistor array base-plate preparation method of the invention as a result, by utilizing intermediate tone mask technology, using one
Road optical cover process can form patterned the first metal layer 105 and second metal layer in thin-film transistor array base-plate 100
107, while preparing to form pixel confining layer 111 and wall 112 using one of optical cover process, finally realizing only needs 5 light
The preparation of thin-film transistor array base-plate 100 can be realized in cover processing procedure.Its compared to traditional 101 preparation flow of array substrate,
It considerably reduces light shield technique number and improves preparation efficiency to effectively save preparation time.Also, using the present invention
The prepared thin-film transistor array base-plate 100 formed of thin-film transistor array base-plate preparation method can use three-layer metal
(respectively the first metal layer 105, second metal layer 107 and third metal layer 110) is scanned line, signal wire and power supply line
Wiring.
Further, in any of the above-described kind of thin-film transistor array base-plate preparation method, when completion thin film transistor (TFT) battle array
After column substrate, organic luminous layer and cathode layer are directly formed by vapor deposition or printing technology, constitute Organic Light Emitting Diode knot
Structure, and then the preparation of organic light emitting display can be realized by glass cover encapsulation or thin-film package again.
Correspondingly, the principle based on any of the above-described kind of thin-film transistor array base-plate preparation method, the present invention also provides
A kind of thin-film transistor array base-plate.Due to thin-film transistor array base-plate provided by the invention structure with it is provided by the invention
Thin-film transistor array base-plate preparation method is corresponding, therefore overlaps will not be repeated.
A specific embodiment referring to Fig. 5, as thin-film transistor array base-plate 100 of the invention comprising: substrate
101, it is formed on substrate and is carried out patterned polycrystalline silicon membrane 103, is formed on patterned polycrystalline silicon membrane 103 and not
The first insulating layer 104 on the substrate covered by polycrystalline silicon membrane 103.Wherein, the first insulating layer 104 includes interval pre-determined distance
The area TFT and capacitive region.
Meanwhile thin-film transistor array base-plate 100 of the invention further includes being sequentially formed on the first insulating layer 104 simultaneously position
Grid 105a and second insulating layer 106 in the area TFT, and be sequentially formed on the first insulating layer 104 and be located at capacitive region
Capacitor bottom crown 105b, second insulating layer 106 and capacitor top crown 107a.Wherein, capacitor top crown 107a is formed in second absolutely
In the part of the surface of edge layer 106.
Further, thin-film transistor array base-plate 100 of the invention further includes being formed in second insulating layer 106, capacitor
Third insulating layer 109 on top crown 107a and the first uncovered insulating layer 104.Wherein, include in third insulating layer 109
Multiple contact holes, multiple contact holes are extended through to pole on 103 surface of polycrystalline silicon membrane, the capacitor surface bottom crown 105b and capacitor
The surface plate 107a.
Also, thin-film transistor array base-plate of the invention further includes forming source electrode 110a in the contact hole, drain electrode
The 110b and anode 110c being formed on uncovered third insulating layer 109.Wherein, anode 110c covering part third insulate
The surface of layer 109, and be connected with source electrode 110a or drain electrode 110b, to realize source electrode 110a or drain 110b's and anode 110c
Merge.
Meanwhile thin-film transistor array base-plate 100 of the invention further include be sequentially formed in third metal layer and not by
Pixel confining layer 111 and wall 112 on the third insulating layer 109 of third metal layer covering.Wherein, pixel confining layer 111
It covers a part of anode 110c and exposes most of region of anode 110c.Further, it is also necessary to explanation, at this
In one specific embodiment of the thin-film transistor array base-plate 100 of invention, substrate 101 is glass substrate, thin metal matrix plate or soft
Property plastic base.Formed amorphous silicon film layer 103 on the substrate 101 with a thickness of 40nm -70nm.
Also, grid 105a, capacitor bottom crown 105b and capacitor top crown 107a use identical metal material or metal
Alloy material prepares to be formed.Source electrode 110a, drain electrode 110b and anode 110c are then aoxidized using identical metal material and/or metal
Object material prepares to be formed simultaneously.Preferably, source electrode 110a, drain electrode 110b and anode 110c use metal material and metal oxide
Material prepares to be formed simultaneously, wherein metal oxide materials are located on metal material, are formed by one-pass film-forming processing procedure.Tool
Body, source electrode 110a, drain electrode 110b and anode 110c bottom use metal or metal alloy, and top layer then uses metal oxide material
Material preparation is formed.Wherein, metal oxide can be at least one of tin indium oxide (ITO) and indium zinc oxide (IZO).
In addition, it should also be noted that, in a specific embodiment of thin-film transistor array base-plate 100 of the invention,
The material of first insulating layer 104 is at least one of silica and silicon nitride.The material and third of second insulating layer 106 insulate
The material of layer 109 is at least one of silicon nitride, silica and silicon oxynitride.
Correspondingly, the present invention also provides a kind of display device, including as above any thin film transistor (TFT) array base
Plate 100, the organic luminous layer being formed on thin-film transistor array base-plate and the conduct being formed on organic luminous layer are organic
The cathode layer of light emitting diode second electrode.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneously
Limitations on the scope of the patent of the present invention therefore cannot be interpreted as.It should be pointed out that for those of ordinary skill in the art
For, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to guarantor of the invention
Protect range.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.
Claims (10)
1. a kind of thin-film transistor array base-plate preparation method, which comprises the steps of:
Polycrystalline silicon membrane is prepared on substrate using plated film and crystallization process, and using first of optical cover process to the polysilicon
Film layer carries out patterned process, obtains patterned polysilicon silicon film；
Do not sequentially formed on substrate that the polycrystalline silicon membrane covers in the patterned polysilicon silicon film and the first insulating layer,
The first metal layer, second insulating layer and second metal layer, and using second optical cover process to the first metal layer, described the
Two insulating layers and the second metal layer carry out patterned process, form the area TFT and capacitive region of interval pre-determined distance；
In the second insulating layer and the second metal layer after patterned process and uncovered described first is exhausted
Third insulating layer is formed in edge layer, and patterned process is carried out to the third insulating layer using third road optical cover process, in institute
It states in third insulating layer and forms contact hole；
In the contact hole on the third insulating layer formed third metal layer, and using the 4th optical cover process to described
Third metal layer carries out patterned process, forms the source electrode and drain electrode in the area TFT and is connected with the source electrode or drain electrode
The anode of first electrode as Organic Light Emitting Diode；
It is not covered using the third metal layer of the 5th optical cover process after patterned process and by the third metal layer
The third insulating layer on preparation form patterned pixel confining layer and wall, obtain thin-film transistor array base-plate.
2. the method according to claim 1, wherein described use second optical cover process to first metal
Layer, the second insulating layer and the second metal layer carry out patterned process, include the following steps:
Yellow light technique is carried out using intermediate tone mask, forms be spaced the pre-determined distance and thickness in the second metal layer
Different photoresist figure layers；
By multistep etching-ashing-etching technics to the photoresist figure layer, the second metal layer, second insulation
Layer and the first metal layer perform etching, and remove the photoresist, formed the area TFT for being spaced the pre-determined distance and
The capacitive region；
It wherein, include the first metal layer and described second being sequentially formed on first insulating layer in the area TFT
Insulating layer；In the capacitive region include be sequentially formed on first insulating layer the first metal layer, it is described second absolutely
The first metal layer, the second metal layer part is completely covered in edge layer and the second metal layer, the second insulating layer
Cover the second insulating layer.
3. method according to claim 1 or 2, which is characterized in that using the second optical cover process to described first
Further include following steps after metal layer, the second insulating layer and the second metal layer carry out patterned process:
Using the first metal layer as exposure mask, the polycrystalline silicon membrane not covered by the first metal layer is carried out from right
Quasi- injection impurity ion.
4. thin-film transistor array base-plate preparation method according to claim 1, which is characterized in that described in the contact
Hole neutralizes and is formed after third metal layer on the third insulating layer, further includes that metal oxidation is formed on the third metal layer
The step of nitride layer.
5. thin-film transistor array base-plate preparation method according to claim 1, which is characterized in that described to use the 5th
The third metal layer of the optical cover process after patterned process and the third not covered by the third metal layer insulate
Preparation forms patterned pixel confining layer and wall on layer, includes the following steps:
Using the third metal layer of the coating process after patterned process and not described in third metal layer covering
Photosensitive material layers are coated on third insulating layer；
The photosensitive material layers are exposed using intermediate tone mask, and form the institute of different-thickness distribution after development
State pixel confining layer and wall.
6. a kind of thin-film transistor array base-plate, which is characterized in that use film crystal described in any one of claim 1 to 5
It is prepared by pipe array substrate preparation method, comprising:
Substrate；
It is formed on the substrate and patterned polycrystalline silicon membrane；
It is formed in the first insulation on the patterned polycrystalline silicon membrane and on the substrate not covered by the polycrystalline silicon membrane
Layer；Wherein, first insulating layer includes the area TFT and capacitive region, the area TFT and capacitive region interval pre-determined distance；
It is sequentially formed on first insulating layer and is located at the grid and second insulating layer in the area TFT, and is sequentially formed
In capacitor bottom crown, second insulating layer and capacitor top crown on first insulating layer and positioned at the capacitive region；Wherein, institute
Capacitor top crown is stated to be formed in the part of the surface of the second insulating layer；
The third insulating layer being formed on the second insulating layer, the capacitor top crown and the first uncovered insulating layer；
It wherein, include multiple contact holes in the third insulating layer, multiple contact holes are extended through to the polysilicon film layer surface, institute
State capacitor bottom crown surface and capacitor top crown surface；
The anode for forming source electrode in the contact hole, draining and being formed on the uncovered third insulating layer；Its
In, the surface of third insulating layer described in the anode covering part, and be connected with the source electrode or the drain electrode；
The pixel confining layer and wall being sequentially formed on the uncovered third insulating layer；Wherein, the pixel limit
Given layer covers described anode a part and exposes most of region of the anode.
7. thin-film transistor array base-plate according to claim 6, which is characterized in that pole under the grid, the capacitor
Plate and the capacitor top crown prepare to be formed using identical metal or metal alloy material.
8. thin-film transistor array base-plate according to claim 6, which is characterized in that the source electrode, the drain electrode and institute
Anode is stated using identical metal material and/or metal oxide materials while preparing to be formed.
9. thin-film transistor array base-plate according to claim 6, which is characterized in that the material of first insulating layer is
At least one of silica and silicon nitride；
The material of the second insulating layer and the material of the third insulating layer are in silicon nitride, silica and silicon oxynitride
It is at least one.
10. a kind of display device characterized by comprising
The described in any item thin-film transistor array base-plates of claim 6 to 9；
The organic luminous layer being formed on the thin-film transistor array base-plate；
The cathode layer as Organic Light Emitting Diode second electrode being formed on the organic luminous layer.
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| CN108666354A (en) * | 2018-05-14 | 2018-10-16 | 昆山国显光电有限公司 | Display panel and display device |
| US10651250B2 (en) | 2018-06-25 | 2020-05-12 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Display panel and method for manufacturing same |
| CN108922867A (en) * | 2018-06-25 | 2018-11-30 | 武汉华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
| CN109885214A (en) * | 2019-03-07 | 2019-06-14 | 南京中电熊猫液晶显示科技有限公司 | A kind of embedded touch array substrate and its manufacturing method |
| CN111129324A (en) * | 2019-12-16 | 2020-05-08 | 武汉华星光电半导体显示技术有限公司 | OLED display and manufacturing method thereof |
| WO2022050984A1 (en) * | 2020-09-04 | 2022-03-10 | Applied Materials, Inc. | Methods of fabricating oled panel with inorganic pixel encapsulating barrier |
| CN113628974B (en) * | 2021-07-27 | 2023-10-31 | 深圳市华星光电半导体显示技术有限公司 | Array substrate preparation method and array substrate |
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