CN106206449B - The high yield RRAM unit of film scheme with optimization - Google Patents
The high yield RRAM unit of film scheme with optimization Download PDFInfo
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- CN106206449B CN106206449B CN201510310463.2A CN201510310463A CN106206449B CN 106206449 B CN106206449 B CN 106206449B CN 201510310463 A CN201510310463 A CN 201510310463A CN 106206449 B CN106206449 B CN 106206449B
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Abstract
The method with resistive random access memory (RRAM) unit of good yield and relevant device are formed the present invention relates to a kind of.In some embodiments, by forming hearth electrode above lower metal interconnection layer, and being formed on hearth electrode, there is the dielectric data accumulation layer of the variable resistance of first thickness to implement this method.Coating is formed in dielectric data accumulation layer.Coating has second thickness, in the range of about 2 times to about 3 times thicker than first thickness of second thickness.It is rectangular at top electrode on the cover layer, and upper metal interconnection layer is formed above top electrode.The present invention relates to the high yield RRAM units of the film scheme with optimization.
Description
Cross reference to related applications
The application is U. S. application the 14/242nd, the 983 part continuation application submitted on April 2nd, 2014.
Technical field
The present invention relates to the high yield RRAM units of the film scheme with optimization.
Background technique
Many modern electronic devices contain the electronic memory for being configured to storing data.Electronic memory can be volatibility
Memory or nonvolatile memory.Volatile memory storing data when its energization, and nonvolatile memory is disconnected when it
It being capable of storing data when electric.Resistive random access memory (RRAM) is manufactured due to its simple structure and with CMOS logic
The compatibility of technique and a promising candidate for becoming next-generation non-volatile memory technologies.RRAM unit includes vertical
Ground is located at the resistance-type data storage layer between two electrodes, wherein two electrode settings are metallized at back-end process (BEOL)
In layer.
Summary of the invention
In order to solve the problems in the existing technology, according to an aspect of the invention, there is provided a kind of formation resistance
The method of formula random access memory (RRAM) unit, comprising: hearth electrode is formed above lower metal interconnection layer；At the bottom
The dielectric data accumulation layer with the variable resistance of first thickness is formed on electrode；It is formed and is covered in the dielectric data accumulation layer
Cap rock, wherein the coating has second thickness, the second thickness about 2 times to about 3 times of model thicker than the first thickness
In enclosing；Top electrode is formed above the coating；And upper metal interconnection layer is formed above the top electrode.
In the above-mentioned methods, the first thickness of the dielectric data accumulation layer is in about 40 angstroms and about 60 angstroms of range
It is interior.
In the above-mentioned methods, the second thickness of the coating is in the range of about 75 angstroms and about 150 angstroms.
In the above-mentioned methods, further includes: implement to retain baking after forming the dielectric data accumulation layer, wherein
Implement the reservation baking at a temperature of in the range of about 150 DEG C and about 250 DEG C, and the duration was in about 24 hours peace treaties
In the range of 100 hours.
In the above-mentioned methods, the dielectric data accumulation layer includes one of following or a variety of: hafnium oxide tantalum
(HfTaO), tantalum aluminum oxide (TaAlO), hafnium silicon oxide (HfSiO) and tantalum oxide silicon (TaSiO).
In the above-mentioned methods, the dielectric data accumulation layer includes hafnium oxide aluminium (HfAlO).
In the above-mentioned methods, forming the dielectric data accumulation layer includes: that implementation is respectively formed the more of hafnium oxide (HfO) layer
A first atomic layer deposition (ALD) deposition cycle；And implement to form aluminium oxide on following hafnium oxide (HfO) layer respectively
(AlO) multiple second ALD deposition periods of layer.
In the above-mentioned methods, it is formed HfO layers described, comprising: when implementing the first precursor gas pulses and continuing the first pulse
Between with by water (H2O it) introduces in process chamber；The H is discharged from the process chamber2O；Implement the second precursor gas pulses and continues
Two burst lengths are with by hafnium tetrachloride (HfCl4) introduce in the process chamber, wherein first burst length is greater than described the
Two burst lengths；And the HfCl is discharged from the process chamber4。
In the above-mentioned methods, first burst length continues in the range of about 1000 milliseconds and about 2000 milliseconds.
According to another aspect of the present invention, it additionally provides and a kind of forms resistive random access memory (RRAM) unit
Method, comprising: form hearth electrode；The dielectric data accumulation layer with first thickness is formed above the hearth electrode；It is being formed
Implement to retain baking after the dielectric data accumulation layer；Coating is formed in the dielectric data accumulation layer, wherein described
Coating has second thickness, in the range of about 2 times to about 3 times thicker than the first thickness of the second thickness；And institute
It states and forms top electrode above coating.
In the above-mentioned methods, the dielectric data accumulation layer includes the hafnium oxide aluminium formed using atom layer deposition process
(HfAlO), forming the dielectric data accumulation layer includes: multiple first atomic layers that implementation is respectively formed hafnium oxide (HfO) layer
Deposit (ALD) deposition cycle；And implement to form the multiple of aluminium oxide (AlO) layer on following hafnium oxide (HfO) layer respectively
Second ALD deposition period.
In the above-mentioned methods, the hafnium oxide (HfO) layer is deposited, comprising: by water (H2O) precursor is introduced in process chamber and is held
Continued for the first burst length to form the H2The single layer of O；The H is discharged from the process chamber2O precursor；By hafnium tetrachloride
(HfCl4) the precursor introducing process chamber is interior and continues for the second burst length, second burst length is than first pulse
Short twice of time or more, wherein the HfCl4Precursor and the H2The single-layer back of O should be to form the hafnium oxide (HfO) layer；With
And the HfCl is discharged from the process chamber4Precursor.
In the above-mentioned methods, first burst length continues in the range of about 1000 milliseconds and about 2000 milliseconds.
In the above-mentioned methods, the first thickness of the dielectric data accumulation layer is in about 40 angstroms and about 60 angstroms of range
It is interior.
In the above-mentioned methods, the second thickness of the coating is in the range of about 75 angstroms and about 150 angstroms.
In the above-mentioned methods, further includes: in lower metal interconnection layer disposed thereon bottom electrode layer；On the bottom electrode layer
Deposit the dielectric data accumulation layer；The coating is deposited in the dielectric data accumulation layer；It sinks on the coating
Product top electrode layer；Pattern the top electrode layer and the coating selectively to form the top electricity with the first width
Pole；And pattern the dielectric data accumulation layer and the bottom electrode layer selectively to be formed with wide greater than described first
The hearth electrode of second width of degree.
In the above-mentioned methods, the time between the dielectric data accumulation layer and the deposition coating is being deposited, about
Implement the reservation baking at a temperature of in the range of 150 DEG C and about 250 DEG C, and the duration was at about 24 hours and about 100
In the range of hour.
According to another aspect of the invention, a kind of resistive random access memory (RRAM) unit is additionally provided, comprising:
Hearth electrode is arranged above lower metal interconnection layer；The dielectric data accumulation layer of variable resistance has first thickness and is located at
Above the hearth electrode；Coating is located in the dielectric data accumulation layer, wherein the coating has second thickness, institute
It states in the range of about 2 times to about 3 times thicker than the first thickness of second thickness；Top electrode is arranged above the coating；With
And upper metal interconnection layer, it is arranged on the top electrode.
In above-mentioned RRAM unit, the first thickness of the dielectric data accumulation layer is in about 40 angstroms and about 60 angstroms of model
In enclosing；And wherein, the second thickness of the coating is in the range of about 75 angstroms and about 150 angstroms.
In above-mentioned RRAM unit, the dielectric data accumulation layer includes hafnium oxide aluminium (HfAlO).
Detailed description of the invention
When reading in conjunction with the accompanying drawings, from it is described in detail below can best understanding each aspect of the present invention.It should be noted that
According to the standard practices in industry, all parts are not drawn on scale.In fact, in order to clearly discuss, the ruler of all parts
It is very little to arbitrarily increase or reduce.
Fig. 1 is shown using atomic layer deposition (ALD) technique to form hearth electrode and in-situ deposition technique to be formed above
Dielectric data accumulation layer form the processes of some embodiments of the method for resistive random access memory (RRAM) unit
Figure.
Fig. 2 shows be configured to the first ALD technique in situ of implementing to form hearth electrode and the 2nd ALD technique to be formed above
Dielectric data accumulation layer handling implement some embodiments block diagram.
Fig. 3 A shows the RRAM with hearth electrode and dielectric data accumulation layer in situ above by ALD process deposits
The sectional view of some embodiments of unit.
Fig. 3 B shows the one of the hearth electrode of RRAM unit and the exemplary XPS depth distribution of dielectric data accumulation layer in situ
The figure of a little embodiments.
Fig. 4, which is shown, to be deposited using ALD technique with forming hearth electrode and in-situ deposition technique with the dielectric data for being formed above
Reservoir forms the flow charts of some additional embodiments of the method for RRAM unit.
Fig. 5 to Figure 12, which is shown, forms high k Jie above using ALD technique to form hearth electrode and original position ALD technique
Electric material forms some embodiments of the sectional view of the method for RRAM unit.
Figure 13 shows the sectional view of some embodiments of the RRAM unit with improved yield.
Figure 14 shows the sectional view of some additional embodiments of RRAM unit.
Figure 15 shows some additional embodiments for the method to form RRAM unit.
Figure 16 shows some implementations for the atom layer deposition process for being used to form the data storage layer including hafnium oxide aluminium
The exemplary timing chart of example.
Figure 17 shows some implementations of the figure of tube core yield good known to the integrated chip with multiple RRAM units
Example.
Figure 18 shows the figure of the reservation yield (retention yield) of the integrated chip with multiple RRAM units
Some embodiments.
Specific embodiment
Following disclosure provides the different embodiments or example of many different characteristics for realizing provided theme.
The specific example of component and arrangement is described below to simplify the present invention.Certainly, these are only example, are not intended to limit this
Invention.For example, in the following description, above second component or the upper formation first component may include the first component and second
Component is formed as the embodiment directly contacted, and also may include that can be formed between the first component and second component additionally
Component so that the embodiment that the first component and second component can be not directly contacted with.In addition, the present invention can be in each reality
Repeat reference numerals and/or letter in example.The repetition is for purposes of simplicity and clarity, and itself not indicate to be discussed
Each embodiment and/or configuration between relationship.
Moreover, for ease of description, can be used herein such as " ... under ", " in ... lower section ", " lower part ", " ... it
On ", the spatially relative term on " top " etc., it is (or another with another in order to describe an element or component as shown in the figure
The relationship of element or component a bit).Other than orientation shown in figure, spatially relative term is intended to include device and is using or operating
In different direction.Device can otherwise orient (be rotated by 90 ° or in other directions), and space as used herein
Relative descriptors can be explained similarly accordingly.
Resistive random access memory (RRAM) unit have hearth electrode, hearth electrode by dielectric data accumulation layer with it is upper
The top electrode in face separates.In general, using physical vapor deposition (PVD) technology square depositions of bottom electrode on substrate.Then, the bottom of at
Ex situ forms dielectric data accumulation layer above electrode.It will be appreciated, however, that using PVD process formed hearth electrode (for example,
TiN the oxygen spread from high k dielectric layer towards hearth electrode) is removed.Oxygen moves back the interface between hearth electrode and dielectric data accumulation layer
Change, low yield of devices (for example, since the leakage current near crystal round fringes increases) can be led to by having RRAM unit
High leakage current.
Therefore, the present invention relates to form resistive random access memory (RRAM) unit with reduced leakage current
Method and relevant apparatus.In some embodiments, this method includes the atomic layer deposition using at least top for forming hearth electrode
Product (ALD) technique forms hearth electrode above lower metal interconnection layer.After forming the top of hearth electrode, at the top of hearth electrode
On dielectric data accumulation layer is formed in situ.Then, top electrode is formed above dielectric data accumulation layer, and above top electrode
Form upper metal interconnection layer.It is deposited by using the dielectric data that ALD technique is formed in situ the top of hearth electrode and is formed above
Reservoir improves the interface performance between hearth electrode and dielectric data accumulation layer, leakage current is caused to reduce, and improves leakage electricity
The yield of devices of flow distribution and RRAM unit.
Fig. 1, which is shown, forms dielectric data storage above using ALD technique to form hearth electrode and original position ALD technique
Layer come formed resistive random access memory (RRAM) unit with low current leakage method 100 some embodiments.
In a step 102, using atomic layer deposition (ALD) technique to form at least top of hearth electrode and in lower metal
Upperside interconnection layer forms hearth electrode.ALD technique may include any kind of atom layer deposition process, including but not limited to ALD
Or the ALD (PEALD) of plasma enhancing.It can inhibit oxygen in hearth electrode using ALD technique to form the top of hearth electrode
To external diffusion, to improve the integrality at the interface between hearth electrode and dielectric data accumulation layer above.
At step 104, with the formation of hearth electrode, Jie with variable resistance is formed in situ on the top of hearth electrode
Electric data storage layer.Oxide interface is prevented by dielectric data accumulation layer shown in frame 103 and being formed in situ for hearth electrode
Formation of the layer (electrical property that RRAM unit can be reduced) on bottom electrode layer.In some embodiments, ALD technique can be passed through
Form dielectric data accumulation layer.In other embodiments, dielectric data accumulation layer can be formed by other deposition techniques.
In step 106, top electrode is formed above dielectric data accumulation layer.
In step 108, upper metal interconnection layer is formed above top electrode.In some embodiments, upper metal is mutual
Even layer may include the upper metal via layer being formed on top electrode.In other embodiments, upper metal interconnection layer may be used also
To include the upper metal trace layer being arranged in upper metal via layer.
Fig. 2 shows be configured to implementation ALD technique in situ to be formed to form hearth electrode and ALD technique and be used for RRAM unit
The upper surface of dielectric data accumulation layer handling implement 200 some embodiments block diagram.
Handling implement 200 includes the first process chamber 202 that second processing room 218 is connected to by wafer transfer chamber 212.The
One process chamber 202, second processing room 218 and wafer transfer chamber 212 are connected to one or more vacuum units 224 (for example, vacuum
Pump), vacuum unit 224 is configured to generate low-voltage ring in the first process chamber 202, second processing room 218 and wafer transfer chamber 212
Border.In some embodiments, environment under low pressure can have for example about 10-3Support and about 10-5Pressure in the range of support.
First process chamber 202 includes being configured to keep the first wafer support element 204 of semiconductor substrate 206 (for example, brilliant
Circle electrostatic chuck), wherein RRAM unit will be formed in semiconductor substrate 206.First process chamber 202 further includes ALD deposition member
Part 208, ALD deposition element 208 are configured at least top of the hearth electrode by ALD process deposits RRAM unit.In some realities
It applies in example, ALD deposition element 208 is configurable to deposit entire hearth electrode.ALD deposition element 208 may be configured to
Vapor precursor is disposably introduced in first process chamber 202 (for example, TiCl4And NH3Or N2/H2Precursor is to form TiN) gas
Entrance and the expulsion element for being configured to discharge vapor precursor.During each growth cycle, the precursor molecule of vapor precursor and half
Molecule on conductor substrate 206 reacts to form atomic layer.In some embodiments, ALD deposition element 208 may include plasma
The ALD element of body enhancing, the ALD element of plasma enhancing further comprise being configured to generate to improve in the first process chamber 202
Deposition rate plasma RF plasma generating element.
In some embodiments, the first process chamber 202 may further include PVD deposition element 210, PVD deposition element
210 are configured to the bottom of the hearth electrode by physical vapor deposition (PVD) process deposits RRAM unit.In such embodiment
In, PVD deposition element 210 is configured to form the bottom of hearth electrode, and ALD deposition element 208 is configured in the bottom of hearth electrode
The upper top for forming hearth electrode.
Wafer transfer chamber 212 is connected to and including wafer transmission element 214 (for example, wafer is transmitted with the first process chamber 202
Robot).Wafer transmission element 214 is configured to semiconductor substrate 206 being moved to second processing room from the first process chamber 202
218.Since wafer transfer chamber 212 is kept under vacuum, wafer transmits element 214 can be by the transmission in situ of semiconductor substrate 206
To second processing room 218 (that is, not breaking environment under low pressure).
Second processing room 218 includes the second wafer support element 220 for being configured to keep semiconductor substrate 206.At second
Managing room also includes ALD deposition element 222, and ALD deposition element 222 is configured to the deposited on portions by ALD technique in hearth electrode
Dielectric data accumulation layer is (for example, use HfCl4And H2O precursor is to form including HfOxDielectric data accumulation layer)
Fig. 3 A shows the sectional view of the RRAM unit 300 with the hearth electrode 310 formed by ALD technique.
RRAM unit 300 includes the diffusion barrier layer being arranged in bottom dielectric layer 306 and lower metal interconnection layer 302
308, lower metal interconnection layer 302 is enclosed by interlayer dielectric (ILD) layer 304 being located in BEOL (back-end process) metallization stack part
Around.In some embodiments, lower metal interconnection layer 302 may include that diffusion barrier layer 308 and following semiconductor is arranged in
One in multiple metal interconnecting layers between substrate (not shown).Hearth electrode 310 is arranged on diffusion barrier layer 308.Diffusion
Barrier layer 308 is configured to prevent material from diffusing to hearth electrode 310 from lower metal interconnection layer 302.
Hearth electrode 310 has the top surface 311 formed by ALD technique.For example, in some embodiments, can pass through
Continuous ALD technique forms hearth electrode 310.In other embodiments, hearth electrode can be formed by two stages depositing operation
310, in two stages depositing operation, the bottom 310a of hearth electrode is formed by PVD process, and bottom electricity is formed by ALD technique
The top 310b of pole.In some embodiments, the bottom 310a of hearth electrode can have bigger than the top 310b of hearth electrode
Thickness.
Dielectric data accumulation layer in situ 312 using the dielectric data that following bottom electrode layer 310 has been formed in situ (that is, deposited
Reservoir) it is arranged on the top surface 311 of hearth electrode 310, so that the dielectric data accumulation layer 312 is formed with by ALD technique
The top surface 311 of hearth electrode 310 directly contact.Dielectric data accumulation layer 312 in situ include be configured to storing data state can
Power transformation hinders metal oxide layer.For example, induced synthesis is crossed over dielectric number by the voltage for being applied to dielectric data accumulation layer 312 in situ
According to the conductive path (for example, Lacking oxygen) of accumulation layer 312, to reduce the resistance of dielectric data accumulation layer 312 in situ.It depends on
The voltage applied, dielectric data accumulation layer 312 in situ will undergo reversible change between high resistance state and low resistance state.
Because dielectric data accumulation layer 312 is formed in situ using hearth electrode 310, dielectric data accumulation layer 312 in situ is directly
Adjacent hearth electrode 310 and in situ no intervention oxide interface layer between dielectric data accumulation layer 312 and hearth electrode 310,
And oxide interface layer will be formed when forming dielectric data accumulation layer 312 in situ using 310 ex situ of hearth electrode.In addition, answering
Work as understanding, causes hearth electrode 310 than being formed using physical vapor deposition (PVD) technique to form hearth electrode 310 using ALD technique
Hearth electrode 310 have lower O2Concentration.
For example, Fig. 3 B shows some implementations of Figure 32 2 of exemplary X-ray photoelectron spectroscopy (XPS) depth distribution 324
Example, exemplary X-ray photoelectron spectroscopy (XPS) depth distribution 324 show the oxygen content of hearth electrode 310 (along section line A-
A').Figure 32 2 further illustrates the XPS depth distribution 326 of the oxygen content of the hearth electrode formed using PVD process.
As shown in XPS depth distribution 324, the oxygen content of hearth electrode 310 is in dielectric data close to hearth electrode 310 and above
With the increase of relatively small slope before the position at the interface 328 between accumulation layer 312.XPS depth distribution 324 is at interface 328
Place reaches about 2.5% maximum oxygen content.XPS depth distribution 326 shows the oxygen content of the hearth electrode formed using PVD process
Increase and reach at interface 328 about 10% maximum oxygen content with significantly greater slope.
Referring again to Fig. 3 A, in some embodiments, coating 314 be can be set above dielectric data accumulation layer 312.
Coating 314 is configured to storage oxygen, this can promote the resistance variations in dielectric data accumulation layer 312.In some embodiments,
Coating 314 may include the relatively low metal or metal oxide of oxygen concentration.Top electrode 316 is arranged on coating 314
Side, and upper metal interconnection layer 319 is arranged above top electrode 316.In some embodiments, upper metal interconnection layer 319
It may include upper metal via layer 320 and upper metal trace layer 322 comprising conductive material (for example, copper, aluminium etc.).
Fig. 4, which is shown, forms dielectric data storage above using ALD technique to form hearth electrode and original position ALD technique
Layer come formed RRAM unit method 400 some additional embodiments.
Although disclosed method (for example, method 100,400 and 1500) be shown and described as a series of behavior or
Event, but it is to be understood that the sequence of shown these behaviors or event should not be construed as limited significance.For example, some rows
For can occur in a different order and/or in addition to it is shown herein and/or description behavior or event other behaviors or
Event occurs simultaneously.In addition, and the not all behavior shown is all to implement one or more aspects of the present invention or of the invention
Necessary to embodiment.Furthermore, it is possible to execute shown herein one with one or more individually behaviors and/or stage
Or multiple behaviors.
In step 402, bottom dielectric layer is formed above lower metal interconnection layer.Bottom dielectric layer is under exposing
The opening of portion's metal interconnecting layer.
In step 404, in some embodiments, expansion can be formed above lower metal interconnection layer and bottom dielectric layer
Dissipate barrier layer.Diffusion barrier layer can deposit in the opening in the bottom dielectric layer for exposing following metal interconnecting layer, from
And make the adjacent following metal layer of diffusion barrier layer.
In a step 406, rectangular at bottom electrode layer on the diffusion barrier using ALD technique.In some embodiments, exist
In step 408, PVD process can be used and deposit the first bottom electrode layer on the diffusion barrier to form bottom electrode layer.Then, exist
In step 410, ALD technique can be used and form the second bottom electricity directly contacted with the first bottom electrode layer on the first bottom electrode layer
Pole layer.
In step 412, with the formation of bottom electrode layer, dielectric data accumulation layer is formed in situ above bottom electrode layer.
Dielectric data accumulation layer, which has, to be configured to depending on being applied to the voltage of hearth electrode or top electrode and in high resistance state and low electricity
The variable resistance of reversible change is undergone between resistance state.In some embodiments, dielectric data accumulation layer may include high k dielectric
Layer.
In step 414, implement to retain baking.Retain baking and improves the switch window of RRAM unit (that is, improving
Difference between the data mode of RRAM unit).In some embodiments, raising in the range of about 150 DEG C and about 250 DEG C
At a temperature of implement to retain baking, and the duration is in the range of about 24 hours and about 100 hours.
In step 416, in some embodiments, coating can be formed above dielectric data accumulation layer.
In step 418, rectangular at top electrode layer on the cover layer.
At step 420, top electrode layer and coating are selectively patterned according to masking layer.The selectivity of top electrode layer
Patterning forms the top electrode of RRAM unit.
In step 422, sidewall spacer is formed in the opposite sides of top electrode and coating.
In step 424, according to masking layer and sidewall spacer selectively patterned dielectric data storage layer, hearth electrode
Layer and diffusion barrier layer.Selectively patterning bottom electrode layer forms the hearth electrode of RRAM unit.
In step 426, upper metal interconnection layer is formed above top electrode.In some embodiments, upper metal is mutual
Even layer may include the upper metal via layer being formed on top electrode and the upper metal being formed in upper metal via layer
Trace layer.
Fig. 5 to Figure 13 is shown using ALD technique to form hearth electrode and original position ALD technique to form dielectric number above
Some embodiments of the sectional view of the method for RRAM unit are formed according to accumulation layer.Although describing Fig. 5 to figure in conjunction with method 400
13, but it is to be understood that the structure disclosed in Fig. 5 to Figure 13 is not limited to this method, on the contrary, can represent independently of method
Individual structure.
Fig. 5 shows some embodiments of the sectional view 500 corresponding to step 402 to 404.
As shown in sectional view 500, bottom dielectric layer 306 is formed at the position above lower metal interconnection layer 302,
In, lower metal interconnection layer 302 is arranged in interlayer dielectric (ILD) layer 304.Bottom dielectric layer 306 includes exposure lower metal
The opening 504 of interconnection layer 302.Deposition technique can be used (for example, chemical vapor deposition, physical vapor are heavy in diffusion barrier layer 502
Product etc.) it is deposited in opening 504 and is deposited on 306 top of bottom dielectric layer.
In some embodiments, lower metal interconnection layer 302 may include the conductive metal of such as copper or aluminium.In some realities
It applies in example, ILD layer 304 may include oxide, low K dielectrics or Ultra low k dielectric.In some embodiments, for example, bottom
Dielectric layer 306 may include silicon carbide (SiC) or silicon nitride (SiN).In some embodiments, diffusion barrier layer 502 can wrap
Include leading for the metal of (Al), manganese (Mn), cobalt (Co), titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), tin (Sn), magnesium (Mg) etc.
Electroxidation object, nitride or nitrogen oxides.
Fig. 6 A to Fig. 6 B shows some embodiments of the sectional view 600 and 604 corresponding to step 406.
Fig. 6 A shows sectional view 600, wherein forms bottom electrode layer 602 using continuous ALD deposition technique.Hearth electrode
Layer 602 can be formed on diffusion barrier layer 502.In some embodiments, ALD technique may include plasma enhancing
ALD (PEALD) technique, using RF plasma with realize compared with traditional ALD technique higher deposition rate (that is,
Higher output) and low temperature under improved film electrical property.In various embodiments, bottom electrode layer 602 may include metal
Nitride or metal.For example, in some embodiments, bottom electrode layer 602 may include titanium nitride (TiN) or tantalum nitride (TaN).
In other embodiments, bottom electrode layer 602 may include tungsten (W) or copper (Cu).
Fig. 6 B shows sectional view 604, wherein forms bottom electrode layer 602, two stages deposition using two stages depositing operation
Technique forms second using physical vapor deposition (PVD) process deposits the first bottom electrode layer 602a and using subsequent ALD technique
Bottom electrode layer 602b.In some embodiments, the first bottom electrode layer 602a can be used PVD process and be formed to have the first thickness
Degree.Second bottom electrode layer 602b can be then formed in the first bottom electrode layer 602a using ALD technique up to second thickness, and
Two thickness are less than first thickness.
Using two stages depositing operation to form the output that bottom electrode layer 602 improves method 400, while still providing
The top surface of improved electrical property can be provided to RRAM.This is because PVD process provides high deposition rate, and ALD technique mentions
Supply to inhibit the oxygen in bottom electrode layer 602 to the top surface of external diffusion.In some embodiments, the first bottom electrode layer 602a can be with shape
As the first thickness having in the range of about 50 angstroms and about 100 angstroms, and the second bottom electrode layer 602b can be formed to have
Second thickness in the range of about 15 angstroms and about 30 angstroms.Second thickness be enough to allow to inhibit the oxygen in bottom electrode layer 602 to
External diffusion.
Fig. 7 shows some embodiments of the sectional view 700 corresponding to step 412.
It is in situ (for example, not from vacuum above bottom electrode layer 602 by bottom electrode layer 602 as shown in sectional view 700
Take out substrate) form the dielectric data accumulation layer 702 with variable resistance.On the bottom electrode layer 602 by ALD process deposits
The rectangular electrical property (for example, reducing leakage current) that RRAM device is improved at dielectric data accumulation layer 702.For example, passing through ALD
Titanium nitride (TiN) bottom electrode layer of process deposits has oxygen concentration ladder more smaller than the TiN bottom electrode layer deposited by PVD process
Degree.Therefore, can be inhibited by the TiN bottom electrode layer of ALD process deposits the oxygen in TiN bottom electrode layer to external diffusion, thus
Interface between TiN bottom electrode layer and dielectric data accumulation layer provides better interface integrity.In addition, being formed in situ
Bottom electrode layer 602 and dielectric data accumulation layer 702 prevent the formation of oxide interface layer, and the formation of oxide interface layer can
To reduce the electrical property (for example, the leakage current for increasing RRAM unit) of RRAM unit.
In some embodiments, ALD process deposits dielectric data accumulation layer 702 can be passed through.ALD technique provides improvement
The good stepcoverage at the interface between bottom electrode layer 602 and dielectric data accumulation layer 702.In some embodiments, dielectric
Data storage layer 702 may include high-k dielectric material.For example, in various embodiments, dielectric data accumulation layer 702 can wrap
Include hafnium oxide (HfOX), zirconium oxide (ZrOX), aluminium oxide (AlOX), nickel oxide (NiOX), tantalum oxide (TaOx) or titanium oxide
(TiOx)。
Fig. 8 shows some embodiments of the sectional view 800 corresponding to step 414 to 416.
As shown in sectional view 800, coating 802 can be formed in dielectric data accumulation layer 702.In some embodiments
In, coating 802 may include the metal of such as titanium (Ti), hafnium (Hf), platinum (Pt), and/or aluminium (Al).In other embodiments
In, coating 802 may include such as titanium oxide (TiOx), hafnium oxide (HfOX), zirconium oxide (ZrOX), germanium oxide (GeOX), oxygen
Change caesium (CeOX) metal oxide.
Top electrode layer 804 is formed above coating 802.It can be by vapor deposition technique (for example, physical vapor is heavy
Product, chemical vapor deposition etc.) deposition top electrode layer 804.In various embodiments, top electrode layer 804 may include nitride metal
Object or metal.For example, in some embodiments, top electrode layer 804 may include titanium nitride (TiN) or tantalum nitride (TaN).At it
In his embodiment, top electrode layer 804 may include tungsten (W) or copper (Cu).
Fig. 9 shows some embodiments of the sectional view 900 corresponding to step 418.
As shown in sectional view 900, masking layer 902 is formed selectively above top electrode layer 804.Masking layer 902 configures
For the top electrode for limiting RRAM unit.In some embodiments, masking layer 902 may include hard mask layer.For example, masking layer
902 may include hard mask material, such as silica (SiO2), silicon nitride (SiN), silicon oxynitride (SiON) or silicon carbide
(SiC)。
Figure 10 shows some embodiments of the sectional view corresponding to step 418 to 420.
As shown in sectional view 1000, implement the first Patternized technique to pattern top electrode layer 804 and coating 802.The
One Patternized technique selectively by region that not masked layer 902 covers top electrode layer 804 and coating 802 be exposed to
Etchant 1002, to generate top electrode 316 and patterned coating 314.Top electrode has the first width.Then in top electricity
Sidewall spacer 1004 is formed in the opposite sides of pole 316 and patterned coating 314.In some embodiments, Ke Yitong
Crossing on nitride deposition to dielectric data accumulation layer 702 and will be etched selectively to nitride to form sidewall spacer 1004
Mode form sidewall spacer 1004.
Figure 11 shows the sectional view 1100 of some embodiments corresponding to step 422.
As shown in sectional view 1100, implement the second Patternized technique with patterned dielectric data storage layer 702, bottom electrode layer
602 and diffusion barrier layer 308.Second Patternized technique selectively covers not masked layer 902 or sidewall spacer 1004
Region in dielectric data accumulation layer 702, bottom electrode layer 602 and diffusion barrier layer 308 be exposed to etchant 1102, thus raw
At patterned dielectric data accumulation layer 312, hearth electrode 310 and patterned diffusion barrier layer 308.Hearth electrode, which has, is greater than top
Second width of the first width of electrode is (since bottom electrode layer 602 is patterned by masking layer 902 and sidewall spacer 1004
).
Figure 12 shows the sectional view 1200 of some embodiments corresponding to step 424.
As shown in sectional view 1200, upper metal interconnection layer 319 is formed above top electrode 316.In some embodiments,
Upper metal interconnection layer 319 may include upper metal via layer 320 and upper metal trace layer 322.In some embodiments,
Can by RRAM memory cell dielectric layer 318 form upper metal interconnection layer 319.Then, implement etching
Technique is to form the opening for extending through dielectric layer 318 and hard mask layer 1202 to expose top electrode 316.Then, with metal (example
Such as, copper, aluminium etc.) opening is filled to form upper metal via layer 320 and upper metal trace layer 322.
Figure 13 shows the sectional view of some embodiments of the RRAM unit 1300 with improved yield.
RRAM unit 1300 includes the dielectric data accumulation layer 312 being arranged between hearth electrode 310 and top electrode 316.It is situated between
Electric data storage layer 312 may include high k dielectric layer (for example, the dielectric layer with the dielectric constant greater than 3.9).Coating
314 be arranged between hearth electrode 310 and top electrode 316 and be located at dielectric data accumulation layer 312 above and adjacent dielectric data
At the position of accumulation layer 312.In some embodiments, coating 314 may include metal (for example, Ti, Hf, Pt and/or Al)
Or metal oxide is (for example, TiOX、HfOX、ZrOX、GeOXAnd/or CeOX)。
It should be appreciated that although hearth electrode 310 and dielectric data accumulation layer 312, which is formed in situ, can improve RRAM unit
Can, the yield of the integrated chip including RRAM unit depends on the thickness ratio between dielectric data accumulation layer 312 and coating 314
Rate.Therefore, in some embodiments, by making coating 314 that there is the thickness t in dielectric data accumulation layer 3121About 2
Again to the thickness t in the range of 3 times2, yield can be improved.For example, in some embodiments, dielectric data accumulation layer 312 can
To have thickness t in the range of about 40 angstroms and about 60 angstroms1, and coating 314 can have at about 75 angstroms and about 150 angstroms
Thickness t in range2。
In various embodiments, dielectric data accumulation layer 312 may include hafnium oxide aluminium (HfAlO), hafnium oxide tantalum
(HfTaO), tantalum aluminum oxide (TaAlO), hafnium silicon oxide (HfSiO) and/or tantalum oxide silicon (TaSiO).In general, including in formation
During the dielectric data accumulation layer 312 of HfAlO, the precursor substance as used in the formation at HfAlO layers, chlorine (Cl) atom sinks
Product is in HfAlO.Chlorine atom generates the hole trap that can reduce the performance of RRAM unit 1300.It has further realized that,
The quantity for reducing the chlorine atom in dielectric data accumulation layer 312 can be further improved the yield of RRAM unit 1300.Therefore, exist
In some embodiments, dielectric data accumulation layer 312 can have about 0.9% chlorine impurity content.
Therefore, by adjusting the thickness ratio between dielectric data accumulation layer 312 and coating 314 (for example, C/D ratio
Value between about 2 to about 3) and be used in combination have low chlorine impurity content data storage layer, RRAM unit 1300 provide tool
There is the integrated chip (IC) of improved yield.
Figure 14 shows the sectional view of some additional embodiments of RRAM unit 1400.
RRAM unit 1400 includes the insulating layer 1402 being arranged between RRAM stack and dielectric layer 318.Insulating layer
1402 adjacent diffusion barrier layers 308, hearth electrode, dielectric data accumulation layer and sidewall spacer side wall.Insulating layer 1402 can be with
Further abut the top of hard mask layer 1202.Insulating layer 1402 protects RRAM stack during manufacture, to prevent to heap
The damage of overlapping piece and improvement yield.In some embodiments, for example, insulating layer 1402 may include silicon carbide (SiC) or nitridation
Silicon (SiN).
Figure 15 shows some additional embodiments for the method 1500 to form RRAM unit.Method 1500 is generated with improving
The mode of yield of RRAM unit form data storage layer and coating.
In step 1502, bottom electrode layer is formed.In some embodiments, atomic layer deposition (ALD) technique can be used
It is rectangular at bottom electrode layer on substrate.
In step 1504, dielectric data accumulation layer is formed above bottom electrode layer.In some embodiments, dielectric data
Accumulation layer can use the bottom electrode layer to be formed and be formed in situ.Dielectric data accumulation layer is applied to hearth electrode with basis is configured to
Or top electrode voltage and between high resistance state and low resistance state undergo reversible change variable resistance.
In some embodiments, dielectric data accumulation layer may include the high k dielectric layer formed by ALD technique.For example,
Dielectric data accumulation layer may include hafnium oxide aluminium (HfAlO) layer formed using ALD technique, and ALD technique is being respectively formed oxygen
Change multiple period 1 of hafnium (HfO) layer (step 1506) and is respectively formed multiple the of aluminium oxide (AlO) layer (step 1508)
Between two cycles alternately.The quantity of multiple period 1 and multiple second rounds will depend on the thickness of dielectric data accumulation layer.
In step 1510, in some embodiments, it is possible to implement retain baking.In some embodiments, at about 150 DEG C
Implement to retain baking at raised temperature in the range of about 250 DEG C, and the duration was about 24 hours and about 100 hours
In the range of.
In step 1512, coating is formed above dielectric data accumulation layer.Can by depositing operation (for example,
CVD, PE-CVD, PVD etc.) by coating be formed to have dielectric data accumulation layer thickness about 2 again to about 3 times of range
Interior thickness.
It is rectangular at top electrode layer on the cover layer in step 1514.
In step 1516, top electrode layer and coating are selectively patterned according to masking layer.Selectively pattern
The top electrode of top electrode layer formation RRAM unit.
In step 1518, in some embodiments, side wall can be formed in the opposite sides of top electrode and coating
Spacer.
In step 1520, according to masking layer and sidewall spacer, selectively patterned dielectric data storage layer and bottom are electric
Pole layer.Selectively patterning bottom electrode layer forms the hearth electrode of RRAM unit.
In step 1522, insulating layer and dielectric layer are formed above patterned RRAM stack.In some embodiments
In, dielectric layer may include interlayer dielectric (ILD) layer, and interlayer dielectric (ILD) layer includes low k dielectric, ultra low k dielectric materials
Or pole low k dielectric.
In step 1524, upper metal interconnection layer is formed above top electrode.In some embodiments, upper metal is mutual
Even layer may include the upper metal via layer being formed on top electrode and the upper metal being formed in upper metal via layer
Trace layer.
Figure 16 shows the atomic layer deposition for being used to form the dielectric data accumulation layer including hafnium oxide aluminium (HfAlO)
(ALD) exemplary timing chart 1600 of some embodiments of technique.ALD technique is using deposit hafnium oxides (HfO) respectively and aoxidizes
The alternate deposition cycle c1 and c2 of the layer of aluminium (AlO) form HfAlO.Although showing the ALD period in a particular order, should manage
Solution, can invert the sequence (for example, H in some embodiments2O pulse can be in HfCl4Implement before pulse).
It, can be in time t during the first deposition cycle c1 as shown in timing diagram 16001Implement the first precursor gases arteries and veins
Punching 1602 is with by water (H2O it) introduces in process chamber.H is formed on the substrate in first precursor gas pulses 16022The single layer of O molecule.So
Afterwards in time t2-t3Between from process chamber be discharged H2O.It can be in time t3Implement the second precursor gas pulses 1604 with by tetrachloro
Change hafnium (HfCl4) introduce in process chamber.HfCl4With H2The single-layer back of O molecule should be to generate the single layer of HfO on substrate.Then,
It can be in time t4-t5Between from process chamber be discharged HfCl4。
It, can be in time t during the second deposition cycle c25Implement third precursor gas pulses 1606 with by water (H2O) draw
Enter in process chamber.Third precursor gas pulses 1606 form H on the single layer of HfO2The single layer of O molecule.Then in time t6-t7
Between from process chamber be discharged H2O.It can be in time t7Implement the 4th precursor gas pulses 1608 with by trimethyl aluminium (Al2(CH3)6
Or TMA) introduce in process chamber.TMA and H2The single-layer back of O molecule should be with the single layer of the generation AlO on the single layer of HfO.Then, may be used
In time t8-t9Between from process chamber be discharged TMA.
The first and second deposition cycle c1 and c2 can be iteratively repeated, to control HfAlO layers of thickness.This is because each
Deposition cycle c1 and/or c2 is by the atomic layer of forming material.Therefore, the ALD deposition period of implementation is more, the storage of HfAlO data
The thickness of layer is bigger.
Under normal conditions, during the single layer for forming HfO, due to HfCl4Preceding intracorporal chlorine, chlorine (Cl) atomic deposition exist
In the single layer of HfO.Chlorine atom generates the hole trap that can reduce the performance of RRAM unit in the single layer of HfO.It should be appreciated that
By increasing H2O burst length pt1The chlorine impurity in HfO can be reduced.Therefore, by increasing relative to HfCl4Burst length
pt2H2The burst length pt of O1, form the single layer with the HfO of reduced chlorine impurity.For example, the first burst length pt1It can be with
Than the second burst length pt2Long 2 times or more.Increase H2O burst length pt1Further increase O (- OH) content.Increased OH content
Improve devices switch and performance uniformity.In some embodiments, the H during the first deposition cycle c12O burst length pt1
It can have duration in the range of about 1000 milliseconds (ms) and about 2000ms and during the second deposition cycle c2
H2O burst length pt1' it can have duration in the range of about 500ms and about 1500ms.
Figure 17 shows Figure 170's 0 of tube core (KGD) yield good known to the integrated chip with multiple RRAM units
Some embodiments.Figure 170 0 shows the ratio (C/D ratio) of overburden cover and dielectric data accumulation layer thickness along x-axis
With the KGD yield (that is, yield of unencapsulated IC tube core) in y-axis.
As shown in Figure 170 0, in first area 1702, as the thickness of coating increases, overburden cover and dielectric number
Also increase according to the ratio (C/D ratio) of accumulation layer thickness.The increase of C/D ratio improves the KGD yield of RRAM unit to first
Value V1。
In second area 1704, the thickness of coating and dielectric data accumulation layer is kept constant, but is used to form Jie
H in the ALD technique of electric data storage layer2The O burst length increases.H2The increase in O burst length reduces generated dielectric number
According to the chlorine impurity content in accumulation layer and hydrogen molecule content is increased, to improving the KGD yield of RRAM unit to second value
V2。
In third region 1706, the thickness of coating is further increased.The increase of the thickness of coating increases C/D ratio
Rate.However, the KGD yield that the increase of the thickness of coating corresponds to RRAM unit reaches third value V in third region3's
Relatively small raising.
In the fourth region 1708, the thickness of dielectric data accumulation layer increases.The thickness for increasing dielectric data accumulation layer is (same
The thickness of Shi Zengjia coating) reduce C/D ratio.However, KGD yield can by the thickness for increasing dielectric data accumulation layer
To be further increased to the 4th value V4。
Therefore, as shown in Figure 170 0, by adjusting the ratio of coating and the thickness of dielectric data accumulation layer (for example, being situated between
Between 2 and 3) the dielectric data accumulation layer with high hydrogen molecule content and low chlorine impurity content is used in combination, have RRAM mono-
The yield of the integrated chip of member can increase between about 1.2 times and about 1.5 times (that is, 1.5 >=V4/V1≥1.2)。
Figure 18 shows some embodiments of Figure 180 0 of the reservation yield of the integrated chip with multiple RRAM units.Figure
1800 show along the reservation in the overburden cover of x-axis and the ratio (C/D ratio) and y-axis of dielectric data accumulation layer thickness
Yield (that is, retaining the IC yield after baking).
As shown in Figure 180 0, in first area 1802, as the thickness of coating increases, overburden cover and dielectric number
Also increase according to the ratio (C/D ratio) of accumulation layer thickness.The increase of C/D ratio improves the yield of RRAM unit to the first value
V1’。
In second area 1804, the thickness of coating and dielectric data accumulation layer is kept constant, but is used to form Jie
H in the ALD technique of electric data storage layer2The O burst length increases.H2The increase in O burst length reduces generated dielectric number
According to the chlorine impurity content in accumulation layer and hydrogen molecule content is increased, to improving the yield of RRAM unit to second value V2’。
In third region 1806, the thickness of coating is further increased.The increase of the thickness of coating increases C/D ratio
Rate.However, the yield that the increase of the thickness of coating corresponds to RRAM unit reaches third value V in third region3' phase
To lesser reduction.
In the fourth region 1808, the thickness of dielectric data accumulation layer increases.The thickness for increasing dielectric data accumulation layer is (same
The thickness of Shi Zengjia coating) reduce C/D ratio.However, by the thickness for increasing dielectric data accumulation layer, yield can be into
One step increases to the 4th value V4’。
Therefore, as shown in Figure 180 0, by adjusting the ratio of coating and the thickness of dielectric data accumulation layer (for example, being situated between
Between 2 and 3), the dielectric data accumulation layer with high hydrogen molecule content and low chlorine impurity content is used in combination, has RRAM mono-
The yield of the integrated chip of member can increase between about 2.5 times and about 3 times (that is, 3 >=V4’/V1’≥2)。
Therefore, the present invention relates to a kind of resistive random access memory (RRAM) units for being formed and having improved yield
Method and relevant device.
In some embodiments, the present invention relates to a kind of sides for forming resistive random access memory (RRAM) unit
Method.Implement this method by forming hearth electrode above lower metal interconnection layer.Being formed on hearth electrode has first thickness
Variable resistance dielectric data accumulation layer, and form coating in dielectric data accumulation layer.Coating has second thickness,
In the range of about 2 times to about 3 times thicker than first thickness of second thickness.It is rectangular at top electrode on the cover layer, and on top electrode
It is rectangular at upper metal interconnection layer.
In other embodiments, the present invention relates to a kind of sides for forming resistive random access memory (RRAM) unit
Method.This method includes forming hearth electrode, and the dielectric data accumulation layer with first thickness is formed above hearth electrode.This method
It further include implementing to retain baking after forming dielectric data accumulation layer.This method further includes being formed in dielectric data accumulation layer
Coating, wherein coating has second thickness, in the range of about 2 times to about 3 times thicker than first thickness of second thickness.The party
Method further includes rectangular at top electrode on the cover layer.
In yet other embodiment, the present invention relates to a kind of resistive random access memory (RRAM) units.It should
RRAM unit has is arranged in hearth electrode above lower metal interconnection layer, and above hearth electrode with first thickness
The dielectric data accumulation layer of variable resistance.The RRAM unit further includes the coating in dielectric data accumulation layer.Coating
With second thickness, in the range of about 2 times to about 3 times thicker than first thickness of second thickness.RRAM unit further includes that setting is being covered
Top electrode above cap rock and the upper metal interconnection layer being arranged on top electrode.
Foregoing has outlined the features of several embodiments, so that side of the invention may be better understood in those skilled in the art
Face.It should be appreciated by those skilled in the art that they can be easily using designing or modifying based on the present invention for real
Now with other process and structures in the identical purpose of this introduced embodiment and/or the identical advantage of realization.Those skilled in the art
Member it should also be appreciated that this equivalent constructions without departing from the spirit and scope of the present invention, and without departing substantially from essence of the invention
In the case where mind and range, they can make a variety of variations, replace and change herein.
Claims (20)
1. a kind of method for forming resistive random access memory (RRAM) unit, comprising:
Hearth electrode is formed above lower metal interconnection layer；
The dielectric data accumulation layer of the variable resistance with first thickness is formed in situ on the hearth electrode；
Coating is formed in the dielectric data accumulation layer, wherein the coating has second thickness, the second thickness
In the range of 2 times to 3 times thicker than the first thickness；
Top electrode is formed above the coating；And
Upper metal interconnection layer is formed above the top electrode,
Wherein, the lower bottom electrode layer of the hearth electrode is formed using physical vapor deposition (PVD) technique, then uses atomic layer
Deposit the top bottom electrode layer that (ALD) forms the hearth electrode.
2. according to the method described in claim 1, wherein, the first thickness of the dielectric data accumulation layer is at 40 angstroms and 60
In the range of angstrom.
3. according to the method described in claim 1, wherein, the second thickness of the coating is in 75 angstroms and 150 angstroms of model
In enclosing.
4. according to the method described in claim 1, further include:
Implement to retain baking after forming the dielectric data accumulation layer, wherein temperature in the range of 150 DEG C and 250 DEG C
Degree is lower to implement the reservation baking, and the duration is in the range of 24 hours and 100 hours.
5. according to the method described in claim 1, wherein, the dielectric data accumulation layer includes one of following or a variety of:
Hafnium oxide tantalum (HfTaO), tantalum aluminum oxide (TaAlO), hafnium silicon oxide (HfSiO) and tantalum oxide silicon (TaSiO).
6. according to the method described in claim 1, wherein, the dielectric data accumulation layer includes hafnium oxide aluminium (HfAlO).
7. according to the method described in claim 6, wherein, forming the dielectric data accumulation layer includes:
Implement multiple first atomic layer deposition (ALD) deposition cycles for being respectively formed hafnium oxide (HfO) layer；And
Implement multiple second atomic layer depositions (ALD) for forming aluminium oxide (AlO) layer on following hafnium oxide (HfO) layer respectively
Deposition cycle.
8. according to the method described in claim 7, wherein, forming the hafnium oxide (HfO) layer, comprising:
Implement the first precursor gas pulses and continued for the first burst length with by water (H2O it) introduces in process chamber；
Water (the H is discharged from the process chamber2O)；
Implement the second precursor gas pulses and continued for the second burst length with by hafnium tetrachloride (HfCl4) introduce in the process chamber,
Wherein, first burst length is greater than second burst length；And
Hafnium tetrachloride (the HfCl is discharged from the process chamber4)。
9. according to the method described in claim 8, wherein, first burst length continues at 1000 milliseconds and 2000 milliseconds
In range.
10. a kind of method for forming resistive random access memory (RRAM) unit, comprising:
Form hearth electrode；
The dielectric data accumulation layer with first thickness is formed in situ above the hearth electrode；
Implement to retain baking after forming the dielectric data accumulation layer；
Coating is formed in the dielectric data accumulation layer, wherein the coating has second thickness, the second thickness
In the range of 2 times to 3 times thicker than the first thickness；And
Top electrode is formed above the coating,
Wherein, the lower bottom electrode of the hearth electrode is formed using physical vapor deposition (PVD) technique, then uses atomic layer deposition
Product (ALD) forms the top hearth electrode of the hearth electrode.
11. according to the method described in claim 10, wherein, the dielectric data accumulation layer includes using atom layer deposition process
The hafnium oxide aluminium (HfAlO) of formation, forming the dielectric data accumulation layer includes:
Implement multiple first atomic layer deposition (ALD) deposition cycles for being respectively formed hafnium oxide (HfO) layer；And
Implement multiple second atomic layer depositions (ALD) for forming aluminium oxide (AlO) layer on following hafnium oxide (HfO) layer respectively
Deposition cycle.
12. according to the method for claim 11, wherein deposit the hafnium oxide (HfO) layer, comprising:
By water (H2O) precursor introduces in process chamber and continued for the first burst length to form the water (H2O single layer)；
Water (the H is discharged from the process chamber2O) precursor；
By hafnium tetrachloride (HfCl4) the precursor introducing process chamber is interior and continues for the second burst length, the second burst length ratio
Described short twice of first burst length or more, wherein the hafnium tetrachloride (HfCl4) precursor and the water (H2O single-layer back) is answered
To form the hafnium oxide (HfO) layer；And
Hafnium tetrachloride (the HfCl is discharged from the process chamber4) precursor.
13. according to the method for claim 12, wherein first burst length continues in 1000 milliseconds and 2000 milliseconds
In the range of.
14. according to the method described in claim 10, wherein, the first thickness of the dielectric data accumulation layer at 40 angstroms and
In the range of 60 angstroms.
15. according to the method described in claim 10, wherein, the second thickness of the coating is at 75 angstroms and 150 angstroms
In range.
16. according to the method described in claim 10, further include:
In lower metal interconnection layer disposed thereon bottom electrode layer；
The dielectric data accumulation layer is deposited on the bottom electrode layer；
The coating is deposited in the dielectric data accumulation layer；
Top electrode layer is deposited on the coating；
Pattern the top electrode layer and the coating selectively to form the top electrode with the first width；And
Pattern the dielectric data accumulation layer and the bottom electrode layer selectively to be formed to have and be greater than first width
The second width the hearth electrode.
17. according to the method for claim 16, wherein depositing the dielectric data accumulation layer and depositing the coating
Between time, in the range of 150 DEG C and 250 DEG C at a temperature of implement reservation baking, and the duration is small 24
When and in the range of 100 hours.
18. a kind of resistive random access memory (RRAM) unit, comprising:
Hearth electrode is arranged above lower metal interconnection layer；
The dielectric data accumulation layer of variable resistance has first thickness and is located above the hearth electrode；
Coating is located in the dielectric data accumulation layer, wherein the coating has second thickness, the second thickness
In the range of 2 times to 3 times thicker than the first thickness；
Top electrode is arranged above the coating；And
Upper metal interconnection layer is arranged on the top electrode,
The hearth electrode includes the first hearth electrode and the second hearth electrode above first hearth electrode, wherein described
One hearth electrode has first thickness, and second hearth electrode has less than the second thickness of the first thickness and described the
Two thickness are enough to inhibit the oxygen in the hearth electrode to external diffusion.
19. resistor random access memory cell according to claim 18,
Wherein, the first thickness of the dielectric data accumulation layer is in the range of 40 angstroms and 60 angstroms；And
Wherein, the second thickness of the coating is in the range of 75 angstroms and 150 angstroms.
20. resistor random access memory cell according to claim 18, wherein the dielectric data accumulation layer packet
Include hafnium oxide aluminium (HfAlO).
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