CN106205530B

CN106205530B - GOA circuits

Info

Publication number: CN106205530B
Application number: CN201610596186.0A
Authority: CN
Inventors: 龚强
Original assignee: Wuhan China Star Optoelectronics Technology Co Ltd
Current assignee: Wuhan China Star Optoelectronics Technology Co Ltd
Priority date: 2016-07-26
Filing date: 2016-07-26
Publication date: 2018-10-16
Anticipated expiration: 2036-07-26
Also published as: CN106205530A

Abstract

The invention discloses a kind of GOA circuits comprising：Signal generator module, for generating the first clock signal and second clock signal；The waveform of the waveform of first clock signal and the second clock signal all has there are two failing edge；Control module is pulled up, for the output of controlled stage communication number, the current potential of the pull-up drop-down point and when first output is in charged state, pulls down the current potential at the control point；Pull-up module, for charging to first output end；Pull-down module, for when first output is in non-charged state, pulling down the current potential of the drop-down point；Pull-down control module, for when first output is in non-charged state, pulling down the current potential of first output end；Wherein N is positive integer.The present invention can promote the display homogeneity of liquid crystal display panel.

Description

GOA circuits

【Technical field】

The present invention relates to actuation techniques field, more particularly to a kind of GOA circuits.

【Background technology】

Traditional GOA (Gate driver On Array) technical solution, usually in existing thin film transistor (TFT) array In the processing procedure of substrate, scan drive circuit is formed in array substrate, to realize on the thin-film transistor array base-plate Pel array progressively scans.

With the development of low temperature polycrystalline silicon (LTPS) semiconductor thin-film transistor, due to LTPS semiconductors superhigh current carrying itself The characteristic of transport factor, corresponding panel periphery integrated circuit also become everybody focus of attention, and System on Panel (SOP) relation technological researching becomes hot spot.

It, the gate off moment of thin film transistor (TFT), can be because of the capacitance coupling between grid and drain electrode after charging to pixel It closes and feedthrough (Feedthrough) phenomenon occurs, cause the voltage on the practical voltage and data line being filled with of pixel variant.Although This difference can be compensated by adjusting common voltage, but when deviation occurs in processing procedure, since feed-trough voltage is bigger, processing procedure The unevenness of common voltage caused by deviation will be more apparent.

Feed-trough voltage when therefore reducing pixel charging has great significance to promoting Display panel homogeneity.Currently, part External integrated circuit (Gate IC) for gate driving can export tool, and there are two the output signals of failing edge, to reduce feedback Be powered pressure, but for GOA circuits and is not suitable for.GOA circuits can only export tool, and there are one the output signal of failing edge, the grid of TFT Pole turn-off transient is directly reduced to constant pressure low potential VGL by constant pressure high potential VGH, cannot reduce feedthrough electricity when pixel charging Pressure is unfavorable for promoting the display homogeneity of liquid crystal display panel.

Therefore, it is necessary to propose a kind of GOA circuits, to solve the above technical problems.

【Invention content】

The purpose of the present invention is to provide a kind of GOA circuits, with solve the output ends of existing GOA circuits in the prior art without Method output tool is there are two the waveform signal of failing edge, the technical problem for causing the homogeneity of panel poor.

To solve the above problems, technical scheme is as follows：

A kind of GOA circuits comprising：

At least two mutual cascade GOA units, wherein N grades of GOA units include：

First common signal input terminal, the second common signal input terminal, high level input terminal, low-level input, first Clock signal output terminal, third common signal input terminal, the 4th common signal input terminal, second clock signal output end；N-1 Grade signal input part, N+1 grades of signal input parts, the first control terminal, the second control terminal, drop-down point, the first clock signal input End, second clock signal input part, the first output end, control point；

The N grades of GOA units further include：

Signal generator module, respectively with the first common signal input terminal, the second common signal input terminal, described High level input terminal, the low-level input, first clock signal output terminal, the third common signal input terminal, The 4th common signal input terminal and the second clock signal output end connection, for generate the first clock signal and Second clock signal；The waveform of the waveform of first clock signal and the second clock signal all has there are two failing edge；

Pull up control module, respectively with the N-1 grades of signal input parts, the N+1 grades of signal input parts, described the One control terminal, second control terminal and first clock signal input terminal connection, for the defeated of controlled stage communication number Go out, pull up the current potential of the drop-down point and when first output is in charged state, pulls down the electricity at the control point Position；

Pull-up module is connect with the second clock signal input part, first output end, the drop-down point respectively, For charging to first output end；

Pull-down module controls mould with the high level input terminal, the second clock signal input part, the pull-up respectively Block connects, and is commonly connected to the drop-down point with the pull-up module, is used in first output in non-charging shape When state, the current potential of the drop-down point is pulled down；

Pull-down control module is connect with the high level input terminal, the low level output end respectively, and with the pull-up Control module, pull-up module connection；And it is commonly connected to the control point with the pull-down module, for described first Output pulls down the current potential of first output end when non-charged state；Wherein N is positive integer.

The GOA circuits of the present invention, due to increasing signal generator module on the basis of existing GOA circuits, by this Signal generator module generates the clock signal having there are two failing edge, further such that failing edge there are two output signal tools, from And feed-trough voltage is reduced, improve the homogeneity of panel.

【Description of the drawings】

Fig. 1 is the circuit diagram of existing GOA circuits；

Fig. 2 is the sequence diagram of existing GOA circuits；

Fig. 3 is the circuit diagram of the first the first signal generator module of the invention；

Fig. 4 is the circuit diagram of the first second signal generation module of the invention；

Fig. 5 be the present invention GOA circuits in each clock signal sequence diagram；

Fig. 6 is the circuit diagram of second of first signal generator modules of the invention；

Fig. 7 is the circuit diagram of second of second signal generation module of the invention；

Fig. 8 is the sequence diagram of the GOA circuits of the present invention.

【Specific implementation mode】

The explanation of following embodiment is to refer to additional schema, to illustrate the particular implementation that the present invention can be used to implement Example.The direction term that the present invention is previously mentioned, such as "upper", "lower", "front", "rear", "left", "right", "inner", "outside", " side " Deng being only the direction with reference to annexed drawings.Therefore, the direction term used be illustrate and understand the present invention, rather than to The limitation present invention.The similar unit of structure is to be given the same reference numerals in the figure.

The GOA driving circuits of the present invention are suitable for display panel, such as TFT-LCD (Thin Film Transistor Liquid Crystal Display, liquid crystal display panel of thin film transistor), OLED (Organic Light Emitting Diode, organic LED display panel) etc., GOA driving circuits of the invention are used to provide drive signal to display panel (scanning signal).

With reference to figure 1, Fig. 1 is the circuit diagram of existing GOA circuits.

The GOA circuits of the present embodiment include at least two mutual cascade GOA units, if N is positive integer, wherein N grades GOA unit includes：

High level input terminal, low-level input；N-1 grades of signal input parts, N+1 grades of signal input parts, the first control End processed, the second control terminal, drop-down point Q, the first clock signal input terminal, second clock signal input part, the first output end, control Point P；

The voltage of high level input terminal input is VGH, the voltage of low-level input input is VGL, N-1 grades of signals are defeated The signal for entering end input is G (N-1), the signal of N+1 grades of signal input part inputs is G (N+1), the letter of the first control terminal input Number be U2D, the signal of the second control terminal input is D2U, the signal of drop-down point Q, the first clock signal input terminal input be CK1 or The signal that person CK2, second clock signal input part input is CK2 or the signal of CK1, the first output end are G (N), control point P；

Wherein, the N-1 grades of signal input parts are connected with the first output end of N-1 grades of GOA unit；The N+ 1 grade of signal input part is connected with the first output end of N+1 grades of GOA unit；

By taking the GOA unit other than the first order and afterbody GOA unit as an example, as shown in Figure 1, the N grades of GOA units Further include：Pull up control module 100, pull-up module 200, pull-down module 300, pull-down control module 400；

Control module 200 is pulled up, is controlled respectively with the N-1 grades of signal input parts, N+1 grades of signal input parts, first End processed, the second control terminal, the connection of the first clock signal input terminal, pull-up control module 200 are used for the output of controlled stage communication number, It pulls up the current potential of the drop-down point and when first output is in charged state, pulls down the current potential at the control point； This grade of communication number is G (N+1) or G (N-1)；

Pull-up module 200 is connect with the second clock signal input part, the first output end, the drop-down point respectively, on Drawing-die block 200 is for charging to first output end；

Pull-down module 300 is controlled with the high level input terminal, the second clock signal input part, the pull-up respectively Molding block 100 connects, and is commonly connected to the drop-down point with the pull-up module 200, and pull-down module 300 is used for described the One output pulls down the current potential of the drop-down point when non-charging shape；

Pull-down control module 400 is connect with the high level input terminal, the low level output end respectively, and with it is described Pull up control module 100, pull-up module 200 connects；And it is commonly connected to the control point with the pull-down module 300, it is used for When first output is in non-charged state, the current potential of first output end is pulled down.

When forward scan, it is high level that forward scan, which controls signal U2D, and it is low level that reverse scan, which controls signal D2U, When scanning 1 row, the signal of N-1 grades of signal input parts input is STV.When reverse scan, forward scan control letter Number U2D is low level, and it is high level that reverse scan, which controls signal D2U, and when scan last column, which inputs The signal of end input is STV.

As shown in Fig. 2, CK1, CK2 indicate the first clock signal and second clock signal, by taking 4 grades of GOA units as an example, G (1) The signal of the first output end output per level-one GOA unit is indicated to G (4)；

First clock signal input terminal of the pull-up control module 100 of wherein the 1st grade GOA unit accesses CK1, pull-up module 200, the second clock signal input part of pull-down module 300 meets CK2；The of the pull-up control module 100 of 2nd grade of GOA unit One clock signal input terminal access CK2, pull-up module 200, pull-down module 300 second clock signal input part meet CK1；3rd First clock signal input terminal of the pull-up control module 100 of grade GOA unit accesses CK1, pull-up module 200, pull-down module 300 Second clock signal input part meet CK2；First clock signal input terminal 100 of the pull-up control module of the 4th grade of GOA unit Access CK2, pull-up module 200, pull-down module 300 second clock signal input part meet CK1.

With the 1st behavior example, when as U2D and D2U, one of them is high level, and when CK1 is high level, Q points are high potential； When CK1 is low level, CK2 is high level, G (1) outputs are high level；When CK1 is high level and CK2 is low level, G (1) output is low level, namely is equal to VGL, remaining row is similar.

It is not difficult to find out by Fig. 2, GOA circuits can only export tool, and there are one the output signal of failing edge, the gate off winks of TFT Between, the voltage of G (n) is directly reduced to constant pressure low potential VGL by constant pressure high potential VGH, cannot reduce feedthrough when pixel charging Voltage, it is poor so as to cause the display homogeneity of liquid crystal display panel.

The GOA circuits of the present invention, including：At least two mutual cascade GOA units, on the basis of existing GOA unit, The N grades of GOA units of the present invention further include the first common signal input terminal, the second common signal input terminal；First clock signal Output end, third common signal input terminal, the 4th common signal input terminal, second clock signal output end；

The signal of the first common signal input terminal input is CKA, the signal of the second common signal input terminal input is The signal that CKB, the first clock signal output terminal export is CK1, the signal of third common signal input terminal input is CKC, the 4th The signal of common signal input terminal input is CKD, the signal of second clock signal output end output is CK2；

When N is odd number, first clock signal input terminal connects first clock signal output terminal；Described second Clock signal input terminal connects the second clock signal output end；When N is even number, first clock signal input terminal connects Connect the second clock signal output end；The second clock signal input part connects first clock signal output terminal；

The N grades of GOA units further include：

Signal generator module, respectively with the first common signal input terminal, the second common signal input terminal, described High level input terminal, the low-level input, first clock signal output terminal, the third common signal input terminal, 4th common signal input terminal and second clock signal output end connection, for generating the first clock signal and second Clock signal；The waveform of the waveform of first clock signal and the second clock signal all has there are two failing edge；

The signal generator module includes the first signal generator module and second signal generation module；

First signal generator module, it is defeated with the first common signal input terminal, second common signal respectively Enter end, the connection of the high level input terminal, the low-level input, first clock signal output terminal；First letter Number generation module is for generating the first clock signal CK1；

The second signal generation module, respectively with the third common signal input terminal, the 4th common signal input terminal, The high level input terminal, the low-level input and second clock signal output end connection；For generating second Clock signal CK2；

With reference to figure 3, Fig. 3 is the circuit diagram of the first the first signal generator module of the invention.

As shown in figure 3, the first first signal generator module 10 of the present invention includes：

First film transistor T1 comprising first grid, the first source electrode and first drain electrode, the first grid with it is described First common signal input terminal 11 connects, and first source electrode connect with the high level input terminal 12, described first drain and First clock signal output terminal 13 connects；

First capacitance C1, one end of the first capacitance C1 are connect with the first grid, and the first capacitance C1's is another One end is connected with first drain electrode；

Second thin film transistor (TFT) T2 comprising second grid, the second source electrode and second drain electrode, the second grid with it is described Second common signal input terminal 14 connects, and second source electrode connect with the low-level input 15, described second drain and The first drain electrode connection.

With reference to figure 4, Fig. 4 is the circuit diagram of the first second signal generation module of the invention

As shown in figure 4, the first described second signal generation module 20 of the present invention includes：

Third thin film transistor (TFT) T3 comprising third grid, third source electrode and third drain electrode, the third grid with it is described Third common signal input terminal 21 connects, and the third source electrode connect with the high level input terminal 22, the third drain and The second clock signal output end 23 connects；

Second capacitance C2, one end of the second capacitance C2 are connect with the third grid, and the second capacitance C2's is another One end is connected with third drain electrode；

4th thin film transistor (TFT) T4 comprising the 4th grid, the 4th source electrode and the 4th drain electrode, the 4th grid with it is described 4th common signal input terminal 24 connects, and the 4th source electrode connect with the low-level input 25, the described 4th drain and The third drain electrode connection.

As shown in figure 5, in conjunction with Fig. 3,4, when CKA is high level, CKB is low level, first film transistor T1 is closed, Second thin film transistor (TFT) T2 is disconnected so that CK1 outputs are high level, namely the CK1 waveforms institute equal to VGH, such as t1-t2 periods Show；When CKA is low level, CKB is low level, first film transistor T1 and the second thin film transistor (TFT) T2 are disconnected, due to The effect of the coupling of capacitance C1 so that CK1 can be pulled down to the voltage between VGH and VGL；Namely CK1 occurs under the 1st time Drop, such as shown in the CK1 waveforms of t2-t3 periods；When CKA is low level, and CKB is high level, first film transistor T1 is disconnected It opening, the second thin film transistor (TFT) T2 is closed, and CK1 is low level, namely is equal to VGL, such as shown in the CK1 waveforms of t3-t5 periods, CK1 signals occur second and decline, it can be seen that there are two failing edges for CK1 tools.

It is understood that when CKC is high level, CKD is low level so that CK2 outputs are high level, namely are equal to VGH, such as shown in the CK2 waveforms of t3-t4 periods；When CKC is low level, CKD is low level, due to the coupling of capacitance C2 Effect so that CK2 can be pulled down to the voltage between VGH and VGL；Namely there is the 1st decline in CK2, such as when t4-t5 Shown in the CK2 waveforms of section；When CKC is low level, and CKD is high level, CK2 is low level, namely is equal to VGL, such as t5-t6 Shown in the CK2 waveforms of period, CK2 signals occur second and decline, it can be seen that there are two failing edges for CK2 tools.

With reference to figure 6, Fig. 6 is the circuit diagram of second of first signal generator modules of the invention.

As shown in fig. 6, second of first signal generator modules 30 of the invention include：

5th thin film transistor (TFT) T5 comprising the 5th grid, the 5th source electrode and the 5th drain electrode, the 5th grid with it is described First common signal input terminal 31 connects, and the 5th source electrode connect with the high level input terminal 32, the described 5th drain and First clock signal output terminal 33 connects；

6th thin film transistor (TFT) T6 comprising the 6th grid, the 6th source electrode and the 6th drain electrode, the 6th grid with it is described Second common signal input terminal 34 connects, and the 6th source electrode is connect by first resistor R1 with the low-level input 35, 6th drain electrode is connected with the 5th drain electrode.

With reference to figure 7, Fig. 7 is the circuit diagram of second of second signal generation module of the invention.

As shown in fig. 7, second of second signal generation module 40 of the present invention includes：

7th thin film transistor (TFT) T7 comprising the 7th grid, the 7th source electrode and the 7th drain electrode, the 7th grid with it is described Third common signal input terminal 41 connects, and the 7th source electrode connect with the high level input terminal 42, the described 7th drain and The second clock signal output end 43 connects；

8th thin film transistor (TFT) T8 comprising the 8th grid, the 8th source electrode and the 8th drain electrode, the 8th grid with it is described 4th common signal input terminal 44 connects, and the 8th source electrode is connect by second resistance R2 with the low-level input 45, 8th drain electrode is connected with the 7th drain electrode.

In conjunction with Fig. 6 and 7 and Fig. 5, when CKA is high level, CKB is low level, first film transistor T1 is closed, the Two thin film transistor (TFT) T2 are disconnected so that CK1 outputs are high level, namely the waveform institute equal to VGH, such as the CK1 of t1-t2 periods Show；When CKA is low level, CKB is low level, first film transistor T1 and the second thin film transistor (TFT) T2 are disconnected, due to The partial pressure of resistance R1 acts on so that CK1 can be pulled down to the voltage between VGH and VGL；Namely CK1 occurs under the 1st time Drop, such as shown in the waveform of the CK1 of t2-t3 periods；When CKA is low level, and CKB is high level, first film transistor T1 It disconnects, the second thin film transistor (TFT) T2 is closed, and CK1 is low level, namely the waveform institute equal to VGL, such as the CK1 of t3-t5 periods Show, CK1 signals occur second and decline, it can be seen that there are two failing edges for CK1 tools.The principle of second signal generation module and this Similar, details are not described herein.

That is, the GOA unit of the present invention may include the first signal generator module of any one of the above and second signal production Raw module；Include additionally pull-up control module, pull-up module, pull-down module, pull-down control module；

Fig. 1 is returned to, the pull-up control module 100 includes with control output end, the pull-up control module 100：The Nine thin film transistor (TFT) T9, the tenth thin film transistor (TFT) T10, the 11st thin film transistor (TFT) T11；

9th thin film transistor (TFT) T9 comprising the 9th grid, the 9th source electrode and the 9th drain electrode, the 9th grid with it is described First control terminal connects, and the 9th source electrode is connect with the N-1 grades of signal input parts；The letter of the first control terminal input Number be U2D；The signal of the second control terminal input is D2U；

Tenth thin film transistor (TFT) T10 comprising the tenth grid, the tenth source electrode and the tenth drain electrode, the tenth grid and institute The connection of the second control terminal is stated, the tenth source electrode connect with the N+1 grade signal input parts, and the described tenth drains and described the Nine drain electrode connections；

11st thin film transistor (TFT) T11 comprising the 11st grid, the 11st source electrode and the 11st drain electrode, the described tenth One grid is connect with first clock signal input terminal, and the 11st source electrode is connected with the 9th drain electrode；

When N is odd number, first clock signal input terminal connects first clock signal output terminal, namely with the One signal generator module connects；When N is even number, first clock signal input terminal connects the second clock signal output End, namely connect with second signal generation module.

The pull-up module 200 includes：12nd thin film transistor (TFT) T12 and third capacitance；

12nd thin film transistor (TFT) T12 comprising the 12nd grid, the 12nd source electrode and the 12nd drain electrode, the described tenth Two grids are connect with the drop-down point Q, and the 12nd source electrode is connect with the second clock signal input part, and the described 12nd Drain electrode is connect with first output end, and when N is odd number, the second clock signal input part connects the second clock letter Number output end, namely connect with second signal generation module；When N is even number, the second clock signal input part connects institute The first clock signal output terminal is stated, namely is connect with the first signal generator module.

Third capacitance C3, one end of the third capacitance C3 are connect with the drop-down point, and the third capacitance C3's is another End is connected with the 12nd drain electrode.

The pull-down control module 400 includes：13rd thin film transistor (TFT) T13, the 14th thin film transistor (TFT) T14, the tenth Five thin film transistor (TFT) T15, the 4th capacitance C4；

13rd thin film transistor (TFT) T13 comprising the 13rd grid, the 13rd source electrode and the 13rd drain electrode, the described tenth Three grids are connected with the 11st drain electrode, and the 13rd source electrode connect with first clock signal input terminal, and described the 13 drain electrodes are connect with the control point P；

14th thin film transistor (TFT) T14 comprising the 14th grid, the 14th source electrode and the 14th drain electrode, the described tenth Four grids are connect with the 13rd source electrode, and the 14th source electrode is connect with the high level input terminal, the 14th leakage Pole is connect with the control point P；

15th thin film transistor (TFT) T15 comprising the 15th grid, the 15th source electrode and the 15th drain electrode, the described tenth Five grids are connect with the control point P, and the 15th source electrode is connect with the low-level input, it is described 15th drain electrode with The first output end connection；

One end of 4th capacitance C4, the 4th capacitance C4 are connect with the control point P, and the C4 of the 4th capacitance is another End is connected with the 15th drain electrode.

The pull-down module 300 includes：

16th thin film transistor (TFT) T16 comprising the 16th grid, the 16th source electrode and the 16th drain electrode, the described tenth Six grids are connect with the high level input terminal, and the 16th source electrode is connected with 11 drain electrode, the 16th drain electrode It is connect with the drop-down point Q；

17th thin film transistor (TFT) T17 comprising the 17th grid, the 17th source electrode and the 17th drain electrode, the described tenth Seven grids are connect with the second clock signal input part, and the 17th source electrode is connect with 16 source electrode；

18th thin film transistor (TFT) T18 comprising the 18th grid, the 18th source electrode and the 18th drain electrode, the described tenth Eight grids are connect with the control point, and the 18th source electrode is connected with 17 drain electrode；It is described 18th drain electrode with it is described Low-level input connects.

As shown in figure 8, by forward scan and by taking the 1st grade of GOA unit as an example, when STV outputs are high level and CK1 is also When high level, pull-up control module 100 works.CK1 draws high the current potential of P points, and STV draws high the current potential of Q points；When next Sequence (t1-t3 moment), CK1 are low level, and CK2 is high level, since Q points are high level, the current potential of P points are dragged down, together When Q points be maintained at high potential.

When Q points are in high potential, pull-up module 200 works, and the current potential that CK2 is output to G (1) namely G (1) is equal to CK2 Current potential, also there are two failing edges in G (1).When the current potential of P points is high level, and CK2 is also high level, pass through pull-down module 300 move Q points to low potential.When CK1 is high level, the current potential of P points is drawn high, since thin film transistor (TFT) T15 is closed, by G (1) current potential drags down, namely is equal to VGL.The output waveform of remaining grade of GOA unit is similar with the 1st grade.

The GOA circuits of the present invention, it is only necessary to adjust the sequential of CKA, CKB, CKC, CKD, so that it may under having twice with acquisition CK1 the and CK2 signals for dropping edge, so as to so that Gate outputs have the waveform of failing edge twice.

Since feed-trough voltage is that moments for closing of Gate (thin film transistor (TFT) of pixel), (namely G (n) became low level wink Between), caused by the coupling of grid G and drain D interpolar, feed-trough voltage is specifically as shown in formula 1：

V_f=C_gd×(V_g1-V_g2)/(C_gs+C_lc+C_st)；Formula 1

Wherein V_fFor feed-trough voltage, C_gdIt is the capacitance in pixel (Pixel) between the grid and drain electrode of TFT devices, C_lcIt is The liquid crystal capacitance of Pixel, C_stIt is the storage capacitance of Pixel；V_g1It is the Gate voltages in Pixel before TFT closings, V_g2It is Gate voltages after TFT is closed in Pixel, i.e. VGL.Since only there are one failing edge, existing electricity for existing G (n) The V on road_g1Equal to VGH, and the present invention is since the Gate voltage drops before can closing Pixel are as low as between VGH and VGL A certain voltage value so that V_g1Less than VGH, to reduce V_g1With V_g2Between difference, so as to reduce Pixel close When caused by feed-trough voltage.

The GOA driving circuits of the present invention lead to due to increasing signal generator module on the basis of existing GOA circuits It crosses the signal generator module and generates the clock signal having there are two failing edge, further such that there are two decline for output signal tool Edge improves the homogeneity of panel to reduce feed-trough voltage.

In conclusion although the present invention is disclosed above with preferred embodiment, above preferred embodiment is not to limit The system present invention, those skilled in the art can make various changes and profit without departing from the spirit and scope of the present invention Decorations, therefore protection scope of the present invention is subject to the range that claim defines.

Claims

1. a kind of GOA circuits, which is characterized in that including：

At least two mutual cascade GOA units, wherein N grades of GOA units include：

First common signal input terminal, the second common signal input terminal, high level input terminal, low-level input, the first clock Signal output end, third common signal input terminal, the 4th common signal input terminal, second clock signal output end；N-1 grades of letters Number input terminal, N+1 grades of signal input parts, the first control terminal, the second control terminal, drop-down point, the first clock signal input terminal, Two clock signal input terminals, the first output end, control point；

The N grades of GOA units further include：

Signal generator module, it is electric with the first common signal input terminal, the second common signal input terminal, the height respectively It is flat input terminal, the low-level input, first clock signal output terminal, the third common signal input terminal, described 4th common signal input terminal and second clock signal output end connection, for generating the first clock signal and second Clock signal；The waveform of the waveform of first clock signal and the second clock signal all has there are two failing edge；

Control module is pulled up, is controlled respectively with the N-1 grades of signal input parts, the N+1 grades of signal input parts, described first End processed, second control terminal and first clock signal input terminal connection, for controlled stage communication number output, It draws the current potential of the drop-down point and when first output is in charged state, pulls down the current potential at the control point；

Pull-up module connect with the second clock signal input part, first output end, the drop-down point, is used for respectively It charges to first output end；

Pull-down module connects with the high level input terminal, the second clock signal input part, the pull-up control module respectively It connects, and the drop-down point is commonly connected to the pull-up module, be used for when first output is in non-charged state, Pull down the current potential of the drop-down point；

Pull-down control module is connect with the high level input terminal, the low level output end respectively, and is controlled with the pull-up Module, pull-up module connection；And it is commonly connected to the control point with the pull-down module, in first output When end is in non-charged state, the current potential of first output end is pulled down；Wherein N is positive integer；

The signal generator module includes the first signal generator module, and first signal generator module is for generating the first clock Signal；First signal generator module respectively with the first common signal input terminal, the second common signal input terminal, The high level input terminal, the low-level input, first clock signal output terminal connection；

Wherein described first signal generator module includes：

First film transistor comprising first grid, the first source electrode and the first drain electrode, the first grid are public with described first Signal input part connection, first source electrode are connect with the high level input terminal altogether, when first drain electrode is with described first Clock signal output end connects；

One end of first capacitance, first capacitance is connect with the first grid, the other end of first capacitance with it is described First drain electrode connection；

Second thin film transistor (TFT) comprising second grid, the second source electrode and the second drain electrode, the second grid are public with described second Signal input part connection, second source electrode are connect with the low-level input altogether, and second drain electrode is leaked with described first Pole connects；

Alternatively, first signal generator module includes：

5th thin film transistor (TFT) comprising the 5th grid, the 5th source electrode and the 5th drain electrode, the 5th grid are public with described first Signal input part connection, the 5th source electrode are connect with the high level input terminal altogether, when the 5th drain electrode is with described first Clock signal output end connects；

6th thin film transistor (TFT) comprising the 6th grid, the 6th source electrode and the 6th drain electrode, the 6th grid are public with described second Signal input part connection, the 6th source electrode are connect by first resistor with the low-level input altogether, the 6th drain electrode It is connected with the 5th drain electrode.

2. GOA circuits according to claim 1, which is characterized in that

The signal generator module further includes second signal generation module；

The second signal generation module is for generating second clock signal；The second signal generation module is respectively with described Three common signal input terminals, the 4th common signal input terminal, the high level input terminal, the low-level input, Yi Jisuo State the connection of second clock signal output end.

3. GOA circuits according to claim 2, which is characterized in that

The second signal generation module includes：

Third thin film transistor (TFT) comprising third grid, third source electrode and third drain electrode, the third grid are public with the third Signal input part connection, the third source electrode are connect with the high level input terminal altogether, when the third drain electrode is with described second Clock signal output end connects；

Second capacitance, one end of second capacitance are connect with the third grid, the other end of second capacitance with it is described Third drain electrode connection；

4th thin film transistor (TFT) comprising the 4th grid, the 4th source electrode and the 4th drain electrode, the 4th grid are public with the described 4th Signal input part connection, the 4th source electrode are connect with the low-level input altogether, and the 4th drain electrode is leaked with the third Pole connects.

4. GOA circuits according to claim 2, which is characterized in that

The second signal generation module includes：

7th thin film transistor (TFT) comprising the 7th grid, the 7th source electrode and the 7th drain electrode, the 7th grid are public with the third Signal input part connection, the 7th source electrode are connect with the high level input terminal altogether, when the 7th drain electrode is with described second Clock signal output end connects；

8th thin film transistor (TFT) comprising the 8th grid, the 8th source electrode and the 8th drain electrode, the 8th grid are public with the described 4th Signal input part connection, the 8th source electrode are connect by second resistance with the low-level input altogether, the 8th drain electrode It is connected with the 7th drain electrode.

5. GOA circuits according to claim 2, which is characterized in that

The pull-up control module includes：

9th thin film transistor (TFT) comprising the 9th grid, the 9th source electrode and the 9th drain electrode, the 9th grid are controlled with described first End connection processed, the 9th source electrode are connect with the N-1 grades of signal input parts；

Tenth thin film transistor (TFT) comprising the tenth grid, the tenth source electrode and the tenth drain electrode, the tenth grid are controlled with described second End connection processed, the tenth source electrode are connect with the N+1 grades of signal input parts, and the tenth drain electrode connects with the 9th drain electrode It connects；

11st thin film transistor (TFT) comprising the 11st grid, the 11st source electrode and the 11st drain electrode, the 11st grid with The first clock signal input terminal connection, the 11st source electrode are connected with the 9th drain electrode；

When N is odd number, first clock signal input terminal connects first clock signal output terminal；When N is even number, First clock signal input terminal connects the second clock signal output end.

6. GOA circuits according to claim 5, which is characterized in that

The pull-up module includes：

12nd thin film transistor (TFT) comprising the 12nd grid, the 12nd source electrode and the 12nd drain electrode, the 12nd grid with The drop-down point connection, the 12nd source electrode are connect with the second clock signal input part, the 12nd drain electrode and institute State the connection of the first output end；

One end of third capacitance, the third capacitance is connect with the drop-down point, the other end of the third capacitance and described the 12 drain electrode connections；

When N is odd number, the second clock signal input part connects the second clock signal output end；When N is even number, The second clock signal input part connects first clock signal output terminal.

7. GOA circuits according to claim 6, which is characterized in that

The pull-down control module includes：

13rd thin film transistor (TFT) comprising the 13rd grid, the 13rd source electrode and the 13rd drain electrode, the 13rd grid with The 11st drain electrode connection, the 13rd source electrode are connect with first clock signal input terminal, the 13rd drain electrode It is connect with the control point；

14th thin film transistor (TFT) comprising the 14th grid, the 14th source electrode and the 14th drain electrode, the 14th grid with 13rd source electrode connection, the 14th source electrode are connect with the high level input terminal, the described 14th drain with it is described Control point connects；

15th thin film transistor (TFT) comprising the 15th grid, the 15th source electrode and the 15th drain electrode, the 15th grid with The control point connection, the 15th source electrode are connect with the low-level input, the 15th drain electrode and described first Output end connects；

One end of 4th capacitance, the 4th capacitance is connect with the control point, the other end of the 4th capacitance and described the 15 drain electrode connections.

8. GOA circuits according to claim 7, which is characterized in that

The pull-down module includes：

16th thin film transistor (TFT) comprising the 16th grid, the 16th source electrode and the 16th drain electrode, the 16th grid with The high level input terminal connects, and the 16th source electrode is connected with 11 drain electrode, under the described 16th drains and is described Draw point connection；

17th thin film transistor (TFT) comprising the 17th grid, the 17th source electrode and the 17th drain electrode, the 17th grid with The second clock signal input part connection, the 17th source electrode are connect with 16 source electrode；

18th thin film transistor (TFT) comprising the 18th grid, the 18th source electrode and the 18th drain electrode, the 18th grid with The control point connection, the 18th source electrode are connected with 17 drain electrode；18th drain electrode is defeated with the low level Enter end connection.