CN106203577B - Vector adder for carrier leakage elimination system - Google Patents
Vector adder for carrier leakage elimination system Download PDFInfo
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- CN106203577B CN106203577B CN201610710293.1A CN201610710293A CN106203577B CN 106203577 B CN106203577 B CN 106203577B CN 201610710293 A CN201610710293 A CN 201610710293A CN 106203577 B CN106203577 B CN 106203577B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/0723—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Amplifiers (AREA)
Abstract
The application relates to a vector adder for a carrier leakage elimination system, and belongs to the technical field of adders. The circuit comprises three circuits of a transconductance stage, a load stage and an output buffer stage, wherein the transconductance stage comprises two adjustable transconductance stages and a constant transconductance stage, the transconductance stage is connected in series with the load stage after being connected in parallel, the load stage is connected in series with the output buffer stage, the load stage consists of a differential inductor L, a blocking capacitor C0 and a capacitor C1, the output of the adjustable transconductance stage is a point A and a point B, the differential inductor L is respectively connected with a point A, B, is connected in parallel with the blocking capacitor C0 after being connected in series with the capacitor C1, and is respectively connected to the output buffer stage by a point C and a point D. The application optimizes the inductance and capacitance values so as to realize that the vector adder reaches the maximum gain.
Description
Technical Field
The application relates to the field of adders, in particular to a vector adder for a carrier leakage cancellation system.
Background
In electronics, a vector adder is a digital circuit that performs addition calculations of digital or vector signals. For a passive UHF RFID system, because the isolation between a reader-writer receiver and a transmitter is limited, a carrier signal at the transmitting end can leak to the receiving end, a new carrier leakage elimination technology utilizes a directional coupler to obtain a reference signal source for carrier elimination at the output end of the reader-writer transmitter, the signal source generates I/Q two paths of carrier elimination reference signals through a quadrature signal generator, and the I/Q two paths of carrier elimination reference signals and a radio frequency tag signal containing carrier leakage are processed together through a vector adder to obtain better amplitude characteristic and phase characteristic, so that carrier leakage elimination is realized. However, the inductance and capacitance of the conventional adder are large, one of them is not suitable for monolithic implementation, and the other one cannot achieve the maximum gain.
Disclosure of Invention
Aiming at the defects and the shortcomings in the prior art, the application provides a vector adder for a carrier leakage elimination system, which optimizes inductance and capacitance values so as to realize that the vector adder achieves maximum gain.
The technical scheme adopted for solving the technical problems is as follows:
the vector adder for carrier leakage eliminating system includes three circuits including transconductance stage, load stage and output buffering stage, the transconductance stage includes two adjustable transconductance stages and one constant transconductance stage, the transconductance stage is connected parallelly to the load stage, the load stage is connected serially to the output buffering stage, the load stage consists of differential inductor L, blocking capacitor C0 and capacitor C1, the output of the adjustable transconductance stage is point A and point B, the differential inductor L is connected to A, B, the differential inductor L is connected serially to the capacitor C1, the capacitor C0 is connected parallelly, and the C and D points are connected to the output buffering stage.
Furthermore, the transconductance stage adopts a differential source stage negative feedback structure.
Further, the load stage circuit is connected with a power supply VDD.
Further, the output buffer stage is provided with two ends V OUTP 、V OUTN Output to the lower circuit.
The application has the following beneficial effects: the inductance and capacitance values are optimized to achieve the maximum gain of the vector adder.
Drawings
FIG. 1 is a schematic circuit diagram of the present application.
Detailed Description
The application will be further illustrated with reference to specific examples. It is to be understood that these examples are illustrative of the present application and are not intended to limit the scope of the present application. Furthermore, it should be understood that various changes and modifications can be made by one skilled in the art after reading the teachings of the present application, and such equivalents are intended to fall within the scope of the application as defined in the appended claims.
As shown in the figure, the vector adder for the carrier leakage elimination system comprises three circuits of a transconductance stage, a load stage and an output buffer stage, wherein the transconductance stage comprises two adjustable transconductance stages and a constant transconductance stage, the transconductance stage circuits are connected in parallel and then connected with the load stage in series, the load stage is connected with the output buffer stage in series, the load stage consists of a differential inductor L, a blocking capacitor C0 and a capacitor C1, the output of the adjustable transconductance stage is a point A and a point B, the differential inductor L is respectively connected with a A, B point, is connected with the capacitor C1 in series and then is connected with the blocking capacitor C0 in parallel, and is respectively connected with the output buffer stage through a point C and a point D.
The transconductance stages adopt a differential source negative feedback structure, wherein the equivalent transconductance of the two transconductance stages can be adjusted by adjusting the negative feedback resistance of the two transconductance stages, and the signals are subjected to vector addition through the transconductance stages.
The load stage circuit is connected with a power supply VDD.
The output buffer stage is provided with two ends V OUTP 、V OUTN Output to the lower circuit.
Specifically, I, Q two paths of orthogonal carrier cancellation reference signals generated by the orthogonal signal generator are respectively input into the adjustable transconductance stage through an I path signal channel and a Q path signal channel, useful tag signals containing carrier leakage are input into the constant transconductance stage, and the useful signals are sent to a lower-stage circuit through the load stage and the output buffer stage. The application optimizes the inductance and capacitance values to achieve the maximum gain of the vector adder.
Claims (2)
1. A vector adder for a carrier leakage cancellation system, characterized by: the load stage is formed by connecting a differential inductor L, a blocking capacitor C0 and a capacitor C1 in series, the output of the adjustable transconductance stage is A point and B point, the differential inductor L is respectively connected with A, B point and is connected with the blocking capacitor C0 in parallel after being connected with the capacitor C1 in series, the transconductance stage is connected to the output buffer stage by C point and D point respectively, the transconductance stage adopts a differential source stage negative feedback structure, and the load stage circuit is connected with a power supply VDD.
2. A vector adder for a carrier leakage cancellation system according to claim 1, characterized in that: the output buffer stage is provided with two ends VOUTP and VOUTN to be output to a lower-stage circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610710293.1A CN106203577B (en) | 2016-08-23 | 2016-08-23 | Vector adder for carrier leakage elimination system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610710293.1A CN106203577B (en) | 2016-08-23 | 2016-08-23 | Vector adder for carrier leakage elimination system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106203577A CN106203577A (en) | 2016-12-07 |
| CN106203577B true CN106203577B (en) | 2023-10-20 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610710293.1A Active CN106203577B (en) | 2016-08-23 | 2016-08-23 | Vector adder for carrier leakage elimination system |
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| Country | Link |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101807883A (en) * | 2010-04-08 | 2010-08-18 | 复旦大学 | Single-ended input and differential output low-noise amplifier applied in UWB system |
| CN102386859A (en) * | 2010-08-27 | 2012-03-21 | 杭州中科微电子有限公司 | Wide band amplifier with frequency compensation |
| CN103314527A (en) * | 2011-01-05 | 2013-09-18 | 德克萨斯仪器股份有限公司 | Circuit and method for reducing input leakage in chopped amplifier during overload conditions |
| CN104484690A (en) * | 2014-12-23 | 2015-04-01 | 苏州宽温电子科技有限公司 | Carrier cancelling circuit system for removing carrier jamming of receiving loop |
| CN104539373A (en) * | 2014-12-30 | 2015-04-22 | 天津大学 | High-speed CMOS monolithic integration light receiver front end of cross coupling structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| PT2456068E (en) * | 2010-11-22 | 2013-08-22 | Ericsson Telefon Ab L M | Low-noise amplifier with impedance boosting circuit |
-
2016
- 2016-08-23 CN CN201610710293.1A patent/CN106203577B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101807883A (en) * | 2010-04-08 | 2010-08-18 | 复旦大学 | Single-ended input and differential output low-noise amplifier applied in UWB system |
| CN102386859A (en) * | 2010-08-27 | 2012-03-21 | 杭州中科微电子有限公司 | Wide band amplifier with frequency compensation |
| CN103314527A (en) * | 2011-01-05 | 2013-09-18 | 德克萨斯仪器股份有限公司 | Circuit and method for reducing input leakage in chopped amplifier during overload conditions |
| CN104484690A (en) * | 2014-12-23 | 2015-04-01 | 苏州宽温电子科技有限公司 | Carrier cancelling circuit system for removing carrier jamming of receiving loop |
| CN104539373A (en) * | 2014-12-30 | 2015-04-22 | 天津大学 | High-speed CMOS monolithic integration light receiver front end of cross coupling structure |
Non-Patent Citations (1)
| Title |
|---|
| 一种多输出压控电流差分跨导放大器的设计;刘晨光等;《电子器件》;第350-355页 * |
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| CN106203577A (en) | 2016-12-07 |
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