CN106201802B - The measurement method of the CPU internal interrupt response time and recovery time of logic-based analyzer - Google Patents
The measurement method of the CPU internal interrupt response time and recovery time of logic-based analyzer Download PDFInfo
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- CN106201802B CN106201802B CN201610576805.XA CN201610576805A CN106201802B CN 106201802 B CN106201802 B CN 106201802B CN 201610576805 A CN201610576805 A CN 201610576805A CN 106201802 B CN106201802 B CN 106201802B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2268—Logging of test results
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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Abstract
The present invention relates to the measurement methods of the CPU internal interrupt response time and recovery time of logic-based analyzer a kind of comprising following steps: S1, CPU match connection by GPIO1 mouthfuls, GPIO2 mouthfuls with logic analyser respectively；Step S2, before software can trigger down trigger, the level of GPIO1 mouthfuls of overturning；Step S3, triggering selected software can trigger interruption, and continuous n times overturn GPIO1 mouthfuls of level signal；Step S4, after above-mentioned software can trigger and interrupt recovery and after GPIO1 level change, logic analyser stops the acquisition to GPIO1 mouthfuls, GPIO2 mouthfuls corresponding level signals, and GPIO1 mouthfuls of record, GPIO2 mouthfuls of corresponding level signals are analyzed, to determine interrupt response time T1 and recovery time T2.Operation of the present invention is convenient, is able to achieve the precise measurement to CPU internal interrupt response time and recovery time, avoids the deviation of system operation time and Time-Series analysis.
Description
Technical field
The present invention relates to a kind of measurement method, the CPU internal interrupt response time of especially a kind of logic-based analyzer
With the measurement method of recovery time.
Background technique
Currently, domestic engine control software, either using the software of multiple-interrupt frame still using behaviour in real time
Make the software of system, it is all unavoidable to use CPU internal interrupt, such as the included timer interruption of CPU or pass through instruction touching
Other traps of hair, and these internal interrupts usually play important role, such as in the timeticks of Real-Time Scheduling
It is disconnected.
Interrupt response time and recovery time are real time operating system or the most important performance indicator of multiple interrupt system
One of, interrupt response time refers to that interrupt requests generation starts to process the time between user program to processor (CPU), interrupts
Recovery time is finger processor time back to needed for being interrupted code.Interrupt response time and recovery time reflect system pair
In the speed of external event response, the real-time performance for analyzing real-time system is of great significance, and cuts especially for interruption
The system for changing frequency, the system operation time that the two times occupy are bigger.The accurate survey of interrupt response time and recovery time
Amount, architecture design early period of only control software provides important reference frame, and is directly related to and guarantees later period control
The performance of device product processed.
Although also mentioning operating system in the limited technical data of external engine control software to use in the inside CPU
It is disconnected, but the specific guidance and implementation method for interrupting measurement are not found.Domestic engine control software is before this in
Disconnected response time and the two performances of recovery time lack always enough concerns, also do not have explicitly to their measurement
Guidance method, and interrupt requests event is for the difficult point of the measurement of CPU internal interrupt the two indexs and is interrupted when returning
The capture of punctum, unlike external interrupt has the hardware signal of interrupt requests that can observe.Other industry relevant procedures runing times
Measurement method, be to carry timer with CPU to measure, it can reach essence for the time measurement that plain sequence executes
True effect, but the measurement for the two time index of internal interrupt will cause very big in default of the capture to measurement point
Loss of accuracy.
Summary of the invention
The purpose of the present invention is overcoming the deficiencies in the prior art, in the CPU that a kind of logic-based analyzer is provided
The measurement method of portion's interrupt response time and recovery time, it is easy to operate, be able to achieve to the CPU internal interrupt response time and
The precise measurement of recovery time reduces the deviation of system operation time and Time-Series analysis, securely and reliably.
According to technical solution provided by the invention, CPU internal interrupt response time of a kind of logic-based analyzer and extensive
The measurement method of multiple time, the measurement method include the following steps:
S1, two GPIO mouthful of CPU are chosen, and is configured to general output interface and initially for selected two GPIO mouthfuls
Low level output is turned to, described two GPIO mouthfuls are individually identified as GPIO1 mouthfuls and GPIO2 mouthfuls；CPU by GPIO1 mouthfuls,
GPIO2 mouthfuls match connection with logic analyser respectively, and when GPIO1 mouthfuls of level are in rising edge, logic analyser is acquired simultaneously
Save GPIO1 mouthfuls, GPIO2 mouthfuls of corresponding level signals；
Step S2, the software of selected CPU, which can trigger, to interrupt, and before software can trigger down trigger, GPIO1 mouthfuls of overturning
Level, so that logic analyser is acquired and saves to GPIO1 mouthfuls, GPIO2 mouthfuls of corresponding level signals；
Step S3, triggering selected software can trigger interruption, and continuously GPIO1 mouthfuls of n times overturning of level signal, and
Pitching pile is carried out during interrupt processing, so that GPIO1 mouthfuls of level is overturn in the traps processing function starting position of response,
And GPIO2 mouthfuls of level is set into height in interrupt processing function end position；
Step S4, after above-mentioned software can trigger and interrupt recovery and after GPIO1 level change, logic analyser stopping pair
The acquisition of GPIO1 mouthfuls, GPIO2 mouthfuls corresponding level signals, and GPIO1 mouthfuls of record, GPIO2 mouthfuls of corresponding level signals are divided
Analysis, to determine interrupt response time T1 and recovery time T2.
In step S3, after software can trigger down trigger, when continuous n times overturn GPIO1 mouthfuls of level signal, (N-2) *
The interval time of adjacent GPIO1 mouthfuls of level of two side to overturn is greater than the triggerable CPU suspension execution that is triggered to interrupted of software and works as future
The time of sequence instruction, N are more than or equal to 3.
In step S2, after the triggerable interruption of software for selecting CPU, remaining interruption of CPU is shielded.
Advantages of the present invention: the GPIO1 mouth of CPU, GPIO2 mouthfuls are connect with logic analyser, are adopted by logic analyser
Collect and record GPIO1 mouthfuls, GPIO2 mouthfuls of corresponding level signals, is become by the overturning of GPIO1 mouthfuls, GPIO2 mouthfuls corresponding level signals
Change, the interrupt response time and Interrupting Time that obtain CPU internal interrupt can be measured, it is easy to operate, reduce system fortune
The deviation of row time and Time-Series analysis, securely and reliably.
Detailed description of the invention
Fig. 1 is flow chart of the invention.
Fig. 2 is the schematic diagram that logic analyser of the present invention acquires GPIO1 mouthfuls, GPIO2 mouthfuls corresponding level signals.
Specific embodiment
Below with reference to specific drawings and examples, the invention will be further described.
It is able to achieve the precise measurement to CPU internal interrupt response time and recovery time as shown in Figure 1:, avoids system
The deviation of runing time and Time-Series analysis, measurement method of the invention include the following steps:
S1, two GPIO mouthful of CPU are chosen, and is configured to general output interface and initially for selected two GPIO mouthfuls
Low level output is turned to, described two GPIO mouthfuls are individually identified as GPIO1 mouthfuls and GPIO2 mouthfuls；CPU by GPIO1 mouthfuls,
GPIO2 mouthfuls match connection with logic analyser respectively, and when GPIO1 mouthfuls of level are in rising edge, logic analyser is acquired simultaneously
Save GPIO1 mouthfuls, GPIO2 mouthfuls of corresponding level signals；
Specifically, for the CPU of selection, two GPIO mouthfuls are chosen, and configures general output for selected GPIO mouth
Interface, and be known to those skilled in the art, herein not by the detailed process that described GPIO mouthfuls is initialized as low level output
It repeats again.When logic analyser is connect with CPU, the GPIO1 mouth of CPU, GPIO2 mouthfuls are connect with two of logic analyser respectively
Input channel connection, the ground wire of logic analyser and the ground wire of CPU connect, and logic analyser specifically connect to match and be combined into CPU
Known to those skilled in the art, details are not described herein again.Generally, the sampling precision with higher of logic analyser, logic
The running parameter of analyzer can be dominant frequency 100M, sampling precision 2ns.Since GPIO1 mouthfuls, GPIO2 mouthfuls are initialized to
Low level output, after logic analyser is connect with CPU, when GPIO1 mouthfuls of level are in rising edge, logic analysis
Instrument just can acquire and save GPIO1 mouthfuls, GPIO2 mouthfuls of corresponding level signals.
Step S2, the software of selected CPU, which can trigger, to interrupt, and before software can trigger down trigger, GPIO1 mouthfuls of overturning
Level, so that logic analyser is acquired and saves to GPIO1 mouthfuls, GPIO2 mouthfuls of corresponding level signals；
In the embodiment of the present invention, choosing the software inside CPU can trigger interruption, i.e., runs corresponding software on CPU, lead to
It crosses software and triggers corresponding internal interrupt, so as to realize the measurement of interrupt response time and recovery time.Selected CPU's is soft
Part can trigger interrupt after, shield remaining interruption of CPU, seized or nested situation to avoid multiple interrupt is generated.It can by step 1
Know, be initialized as low level output due to GPIO1 mouthfuls, after GPIO1 mouthful of overturning of level, so that GPIO1 mouthfuls with upper
Edge is risen, at this point, logic analyser can be realized the acquisition and storage to GPIO1 mouthfuls, GPIO2 mouthfuls corresponding level signals.
Step S3, triggering selected software can trigger interruption, and continuously GPIO1 mouthfuls of n times overturning of level signal, and
Pitching pile is carried out during interrupt processing, so that GPIO1 mouthfuls of level is overturn in the traps processing function starting position of response,
And GPIO2 mouthfuls of level is set into height in interrupt processing function end position；
In the embodiment of the present invention, after software can trigger down trigger, when continuous n times overturn GPIO1 mouthfuls of level signal,
(N-2) interval time of the adjacent GPIO1 mouthfuls of level of two side to overturn of * is greater than the triggerable CPU that is triggered to interrupted of software and stops to execute
The time of current procedure instruction, N are more than or equal to 3.The software can trigger the CPU suspension execution present procedure that is triggered to interrupted and refer to
The time of order can inquire from CPU handbook and obtain；When it is implemented, can realize GPIO1 mouthfuls of level by software instruction
Signal overturning.
Software, which can trigger to interrupt, realizes triggering by software instruction, and specific trigger process is ripe for those skilled in the art
Know.During interrupt processing, the level that function starting position overturns GPIO1 mouthfuls is handled by the traps in response, it can
Realize capture CPU start to process interrupt user program at the time of point, by interrupt processing function end position by GPIO2 mouthfuls
Level sets height, can be realized capture and interrupts user program and is finished at the time of point, can use the common skill of the art
Art means realize pitching pile during interrupt processing, and specific implementation process is known to those skilled in the art, herein no longer
It repeats.
After it can trigger interruption to software and trigger, when continuous n times overturn GPIO1 mouthfuls of level signal, turned over using n times
Turning the M times in GPIO1 mouthfuls of level signal overturning, ((traps are triggered to CPU and stop to execute current procedure instruction M=rounding
Time/twice overturns the interval time+1 between CPIO1), M is more than or equal to 1) can analog capture CPU internal interrupt request
It generates, after the level signal that the M times overturns GPIO1 mouthfuls, CPU enters interrupt processing process, it is arranged by the above-mentioned time, after
The level signal of GPIO1 mouthfuls continuous of overturning can be realized capture CPU back to the time point of original program and interrupt for observing
Software after recovery executes state.
Step S4, after above-mentioned software can trigger and interrupt recovery and after GPIO1 level change, logic analyser stopping pair
The acquisition of GPIO1 mouthfuls, GPIO2 mouthfuls corresponding level signals, and GPIO1 mouthfuls of record, GPIO2 mouthfuls of corresponding level signals are divided
Analysis, to determine interrupt response time T1 and recovery time T2.
In the embodiment of the present invention, logic analyser is limited to patrol to the sampling of GPIO1 mouthfuls, GPIO2 mouthfuls corresponding level signals
The limitation such as storage capacity of analyzer is collected, but at least needs to guarantee the sampling to GPIO1 mouthfuls, GPIO2 mouthfuls corresponding level signals
It can trigger to software after interrupting recovery, when it is implemented, the sampling stop condition of logic analyser can be set, the sampling stops
Only condition, which can according to need, is determined, and details are not described herein again.After stopping sampling, to the GPIO1 mouth of record, GPIO2 mouthfuls
Corresponding level signal is analyzed.
As shown in Fig. 2, according to the definition of interrupt response time and Interrupting Time, T1 is interrupt response time, from figure
Show the starting position T1: the failing edge of GPIO1 mouthfuls of level represents interrupt requests generation, arrives T1 end position: GPIO1 mouthfuls of level it is upper
Liter edge represents CPU and starts to process interruption user program, and the time of T1 end position and starting position is read from logic analyser
Difference, to obtain interrupt response time T1.
To Interrupting Time T2, in figure, the starting position T2: GPIO2 mouthfuls of corresponding rising edges, which represent, interrupts user programs
It is finished, T2 end position: the failing edge of GPIO1 mouthfuls of level represents CPU back to original program moment point, from logic analysis
The time difference that T2 end position and starting position are read on instrument, Interrupting Time T2 can be obtained.
Processor TMS320F2812, CPU is used to run engine control software with CPU, the internal interrupt of measurement is
For RTOSINT interrupts corresponding interrupt response time T1 and Interrupting Time T2, to specific implementation process of the invention
It is illustrated.Specifically,
After the starting section of control software, two pins of GP configuring IOA10 and GPIOD6 are general output function, initially
Turn to output low level, it is ensured that the two pins do not use in this other unrelated measurement pitching pile code, shield other interruptions.
It connects two GPIOA10 and GPIOD6 signals and ground line arrives two channels ch1, ch2 and ground wire ch_Gnd of logic analyser,
The acquisition precision that logic analyser is arranged is 2ns, and trigger condition is that the rising edge of GPIOA10 triggers and saves data.
Before setting RTOSINT interrupt flag bit, it is high that the 10th for setting the data register value of GPIOA, which is 1, GPIOA10,
Level, after setting RTOSINT interrupt flag bit, setting the 10th of the data register value of GPIOA repeatedly is 1 or 0, is then reached
To GPIOA10 level five times effects of overturning.
Value in the corresponding data register position traps processing function starting position overturning GPIOA10 of response, in
The data register location of GPIOD6 is that 1, GPIOD6 exports high level by disconnected processing function end position.
Logic analyser acquires and analyzes the data of above-mentioned record, so as to obtain interrupt response time T1 and interrupt extensive
Multiple time T2.Specifically, it (is needed in the GPIO trigging signal of TMS320F2812 using the quick output hardware characteristic of GPIO
Time is 40ns, and the instruction of overturning GPIO is 1-3 cpu instruction, and holding time is up to 25ns), the level of GPIO becomes
Change the generation of moment approximate expression interrupt requests, CPU starts to process interruption user program, interruption user program is finished and CPU
Back to four moment points of code are interrupted, the error that interrupt response and recovery time measure is preferably at most 25ns, this compares timer
It obtains error caused by the function (time and function processing time that go out stacking including function) of count value and wants small, pass through logic point
The level change of the high-precision capture GPIO signal of analyzer obtains interrupt response time T1 and interruption then by analysis data
The precision of recovery time T2, measurement result can reach tens ns or so on the processor of 100M or so.
By the above process, the RTOSINT interrupt response time T1 of engine control software more can be accurately measured in
Disconnected recovery time T2, meets with theory analysis, this provides basis for the timing of system and time analysis and verifying, is properties of product
Assessment and verifying provide the foundation guarantee.
The GPIO1 mouth of CPU, GPIO2 mouthfuls are connect by the present invention with logic analyser, are collected and recorded by logic analyser
GPIO1 mouthfuls, GPIO2 mouthfuls of corresponding level signals are changed by the overturning of GPIO1 mouthfuls, GPIO2 mouthfuls corresponding level signals, can
Measurement obtain the interrupt response time and Interrupting Time of CPU internal interrupt, it is easy to operate, reduce system operation time and
The deviation of Time-Series analysis, securely and reliably.
Claims (2)
1. the measurement method of the CPU internal interrupt response time and recovery time of logic-based analyzer a kind of, characterized in that institute
Measurement method is stated to include the following steps:
S1, two GPIO mouthfuls for choosing CPU, and be configured to general output interface for selected two GPIO mouthfuls and be initialized as
Low level output, described two GPIO mouthfuls are individually identified as GPIO1 mouthfuls and GPIO2 mouthfuls；CPU passes through GPIO1 mouthfuls, GPIO2 mouthfuls
Connection is matched with logic analyser respectively, when GPIO1 mouthfuls of level are in rising edge, logic analyser is acquired and saved
GPIO1 mouthfuls, GPIO2 mouthfuls of corresponding level signals；
Step S2, the software of selected CPU, which can trigger, to interrupt, and before software can trigger down trigger, the electricity of GPIO1 mouthfuls of overturning
It is flat, so that logic analyser is acquired and saves to GPIO1 mouthfuls, GPIO2 mouthfuls of corresponding level signals；
Step S3, triggering selected software can trigger interruption, and continuous n times overturn GPIO1 mouthfuls of level signal, and are interrupting
Pitching pile is carried out in treatment process, so that overturning GPIO1 mouthfuls of level in the interrupt processing function starting position of response, and in
GPIO2 mouthfuls of level is set height by disconnected processing function end position；After software can trigger down trigger, continuous n times overturn GPIO1
When the level signal of mouth, the interval time of the adjacent GPIO1 mouthfuls of level of two side to overturn of (N-2) *, which is greater than software, can trigger the touching interrupted
It is dealt into CPU to stop to execute the time of current procedure instruction, N is more than or equal to 3；
Step S4, after above-mentioned software can trigger and interrupt recovery and after GPIO1 level change, logic analyser stops to GPIO1
Mouthful, the acquisitions of GPIO2 mouthful corresponding level signals, and to record GPIO1 mouthfuls, GPIO2 mouthfuls of corresponding level signals analyze, with
Determine interrupt response time T1 and recovery time T2.
2. the measurement of the CPU internal interrupt response time and recovery time of logic-based analyzer according to claim 1
Method, characterized in that in step S2, after the triggerable interruption of software for selecting CPU, shield remaining interruption of CPU.
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107463494B (en) * | 2017-06-30 | 2020-11-03 | 百富计算机技术（深圳）有限公司 | Interrupt service program debugging method, device, storage medium and computer equipment thereof |
| CN111831521B (en) * | 2019-04-18 | 2023-04-11 | 深圳市汇顶科技股份有限公司 | Test method of interrupt response time, processor and electronic equipment |
| CN111008100B (en) * | 2019-10-16 | 2021-09-21 | 格力电器（杭州）有限公司 | Linux real-time operating system interrupt response time test system and method |
| CN112650616B (en) * | 2021-01-05 | 2024-07-05 | 上海擎昆信息科技有限公司 | Interrupt detection method, device and system |
| CN113220532B (en) * | 2021-05-20 | 2022-11-25 | 复旦大学 | Method and device for testing feedback time of interrupt event of embedded operating system |
| CN115309618B (en) * | 2022-06-30 | 2023-04-11 | 广州创龙电子科技有限公司 | Input and output delay detection method and system based on RT-Linux system |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6745321B1 (en) * | 1999-11-08 | 2004-06-01 | International Business Machines Corporation | Method and apparatus for harvesting problematic code sections aggravating hardware design flaws in a microprocessor |
| CN1774700A (en) * | 2003-04-08 | 2006-05-17 | 孕龙科技股份有限公司 | Data pickup processing method for logic analyzer and apparatus thereof |
| CN201387606Y (en) * | 2009-04-21 | 2010-01-20 | 北京星网锐捷网络技术有限公司 | Interrupt processing device and physical connection state rollover event processing device |
| CN102215139A (en) * | 2010-04-02 | 2011-10-12 | 华为技术有限公司 | Interruption measuring method, device and system |
| CN103198002A (en) * | 2012-01-09 | 2013-07-10 | 上海海尔集成电路有限公司 | Measurement method and simulator for program running time |
-
2016
- 2016-07-20 CN CN201610576805.XA patent/CN106201802B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6745321B1 (en) * | 1999-11-08 | 2004-06-01 | International Business Machines Corporation | Method and apparatus for harvesting problematic code sections aggravating hardware design flaws in a microprocessor |
| CN1774700A (en) * | 2003-04-08 | 2006-05-17 | 孕龙科技股份有限公司 | Data pickup processing method for logic analyzer and apparatus thereof |
| CN201387606Y (en) * | 2009-04-21 | 2010-01-20 | 北京星网锐捷网络技术有限公司 | Interrupt processing device and physical connection state rollover event processing device |
| CN102215139A (en) * | 2010-04-02 | 2011-10-12 | 华为技术有限公司 | Interruption measuring method, device and system |
| CN103198002A (en) * | 2012-01-09 | 2013-07-10 | 上海海尔集成电路有限公司 | Measurement method and simulator for program running time |
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