CN106158775A - Semiconductor package and manufacture method thereof - Google Patents
Semiconductor package and manufacture method thereof Download PDFInfo
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- CN106158775A CN106158775A CN201510147264.4A CN201510147264A CN106158775A CN 106158775 A CN106158775 A CN 106158775A CN 201510147264 A CN201510147264 A CN 201510147264A CN 106158775 A CN106158775 A CN 106158775A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73217—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a kind of semiconductor package and manufacture method thereof.Semiconductor package includes a substrate, one first chip, one first dielectric layer, a dielectric enclosure layer and at least one first guide hole.First chip is arranged on substrate.First chip has one first touch-down zone.First dielectric layer is arranged on the first chip.First chip and the first dielectric layer are packaged in wherein by dielectric enclosure layer.First guide hole runs through dielectric enclosure layer and the first dielectric layer.First guide hole is connected to the first touch-down zone of the first chip.
Description
Technical field
The present invention is about a kind of semiconductor structure and manufacture method thereof, is particularly partly to lead about one
Body encapsulating structure and manufacture method thereof.
Background technology
Routing connects the offer semiconductor package interconnection that (wire bonding) is a kind of usual use
The method of structure (interconnection).But, owing to wire is a kind of relatively long conductive path,
The consumption and the electric capacity that make electric power throw into question.Additionally, wire, soldered ball and connection pad all take up space
Existence, the number of wire and density therefore suffer from limit.Furthermore, cost can be along with the number of wire
Increase and increase.
Development in recent years goes out straight-through silicon perforation (Through Silicon Via, TSV), and this is another kind of offer
The method of semiconductor package interconnection structure.Straight-through silicon perforation be by have multiple perforation through
Silicon substrate therein provides interconnection structure.Such conductive path is shorter, and the density of conductive path
Can be the highest.But, its complex process, with high costs, yield is also a problem.
Summary of the invention
The present invention is that this kind of semiconductor structure includes carrying about a kind of semiconductor structure and manufacture method thereof
New paragon for interconnection structure.
According to some embodiments, semiconductor package include a substrate, one first chip (chip),
One first dielectric layer, a dielectric enclosure layer and at least one first guide hole (via).First chip is arranged at base
On plate.First chip has one first touch-down zone.First dielectric layer is arranged on the first chip.Dielectric
First chip and the first dielectric layer are packaged in wherein by encapsulated layer.This at least one first guide hole runs through dielectric
Encapsulated layer and the first dielectric layer.This at least one first guide hole is connected to the first touch-down zone of the first chip.
According to some embodiments, the manufacture method of semiconductor package comprises the following steps.First,
One first chip is set on a substrate, and on the first chip, forms one first dielectric layer.First core
Sheet has one first touch-down zone.Then, a dielectric enclosure layer is formed, by the first chip and the first dielectric
Layer is packaged in wherein.Form at least one first perforation through dielectric enclosure layer.Extend this at least one
One perforation, through the first touch-down zone of the first dielectric layer to the first chip.Afterwards, conductor filled by one
To this at least one first perforation, to form at least the one the of the first touch-down zone being connected to the first chip
One guide hole.
More preferably understand in order to the above-mentioned and other aspect of the present invention is had, preferred embodiment cited below particularly,
And coordinate institute's accompanying drawings, it is described in detail below:
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the semiconductor package according to an embodiment.
Fig. 2 is the schematic diagram of the semiconductor package according to another embodiment.
Fig. 3 A～Fig. 3 F is the schematic diagram of the manufacture method of the semiconductor package according to an embodiment.
[symbol description]
100,100 ': semiconductor package
102: substrate
104, the 104 ': the first chip
104A, 104A ': the first touch-down zone
106, the 106 ': the first dielectric layer
108: the first guide holes
110: the second chips
110A, 110A ': the second touch-down zone
112: the second dielectric layers
114: the second guide holes
116: the three chips
116A: the three touch-down zone
118: the three dielectric layers
120: the three guide holes
122: fourth chip
122A: the four touch-down zone
124: the four dielectric layers
126: the four guide holes
128: dielectric enclosure layer
130: redistribution layer
A1: the area of section
A2: the area of section
A3: the area of section
A4: the area of section
O1, O1 ': the first perforation
O2, O2 ': the second perforation
O3, O3 ': the 3rd perforation
O4, O4 ': the 4th perforation
Detailed description of the invention
Refer to Fig. 1, it illustrates the semiconductor package 100 according to an embodiment.Semiconductor package
Assembling structure 100 includes substrate 102,1 first chip 104,1 first dielectric layer 106, dielectric
Encapsulated layer 128 and at least one first guide hole 108.First chip 104 is arranged on substrate 102.The
One chip 104 has one first touch-down zone 104A.Here, " touch-down zone " word means that chip can connect
It is connected to the region of guide hole.First dielectric layer 106 is arranged on the first chip 104.Dielectric enclosure layer 128
First chip 104 and the first dielectric layer 106 are packaged in wherein.First guide hole 108 runs through dielectric envelope
Dress layer 128 and the first dielectric layer 106.First guide hole 108 is connected to the first of the first chip 104
Land district 104A.Semiconductor package 100 may also include a redistribution layer (redistribution layer) 130,
It is arranged on dielectric enclosure layer 128.Redistribution layer 130 is connected to the first guide hole 108.
Semiconductor package 100 may also include one second chip 110,1 second dielectric layer 112 and
At least one second guide hole 114.Second chip 110 is arranged between substrate 102 and the first chip 104.
Second chip 110 has the one second touch-down zone 110A not covered by the first chip 104.Second is situated between
Electric layer 112 is arranged between the second chip 110 and the first chip 104.Dielectric enclosure layer 128 more will
Second chip 110 and the second dielectric layer 112 are packaged in wherein.Second guide hole 114 runs through dielectric enclosure
Layer 128 and the second dielectric layer 112.Second guide hole 114 is connected to the second landing of the second chip 110
District 110A.Redistribution layer 130 is further connected to the second guide hole 114.
In one embodiment, as it is shown in figure 1, the area of the second touch-down zone 110A is equal to or less than the
The area of one touch-down zone 104A.But, the present invention is not limited to this.As in figure 2 it is shown, half
In conductor package structure 100 ', the first chip 104 ' and the first dielectric layer 106 ' that size is less can be arranged
In the top.Now, the area of the second touch-down zone 110A ' can be more than the face of the first touch-down zone 104A '
Long-pending.In one embodiment, as it is shown in figure 1, the number of the second guide hole 114 is led equal to or less than first
The number in hole 108.But, the present invention is not limited to this.As in figure 2 it is shown, the second guide hole 114
Number can be more than the number of the first guide hole 108.In one embodiment, as it is shown in figure 1, second leads
Area of section A2 in hole 114 is equal to or more than area of section A1 of the first guide hole 108.But, this
Invention is not limited to this.
Semiconductor package 100 may also include one the 3rd chip 116, the 3rd dielectric layer 118 and
At least one the 3rd guide hole 120.3rd chip 116 is arranged between substrate 102 and the second chip 110.
3rd chip 116 has one the 3rd touch-down zone 116A not covered by the second chip 110.3rd is situated between
Electric layer 118 is arranged between the 3rd chip 116 and the second chip 110.Dielectric enclosure layer 128 more will
3rd chip 116 and the 3rd dielectric layer 118 are packaged in wherein.3rd guide hole 120 runs through dielectric enclosure
Layer 128 and the 3rd dielectric layer 118.3rd guide hole 120 is connected to the 3rd landing of the 3rd chip 116
District 116A.Redistribution layer 130 is further connected to the 3rd guide hole 120.
In one embodiment, as it is shown in figure 1, the area of the 3rd touch-down zone 116A is equal to or less than the
The area of two touch-down zone 110A.In one embodiment, as it is shown in figure 1, the number of the 3rd guide hole 120
Mesh is equal to or less than the number of the second guide hole 114.In one embodiment, as it is shown in figure 1, the 3rd leads
Area of section A3 in hole 120 is equal to or more than area of section A2 of the second guide hole 114.But, this
Invention is not limited to this.
Semiconductor package 100 may also include fourth chip 122, the 4th dielectric layer 124 and
At least one the 4th guide hole 126.Fourth chip 122 is arranged between substrate 102 and the 3rd chip 116.
Fourth chip 122 has one the 4th touch-down zone 122A not covered by the 3rd chip 116.4th is situated between
Electric layer 124 is arranged between fourth chip 122 and the 3rd chip 116.Dielectric enclosure layer 128 more will
Fourth chip 122 and the 4th dielectric layer 124 are packaged in wherein.4th guide hole 126 runs through dielectric enclosure
Layer 128 and the 4th dielectric layer 124.4th guide hole 126 is connected to the 4th landing of fourth chip 122
District 122A.Redistribution layer 130 is further connected to the 4th guide hole 126.
In one embodiment, as it is shown in figure 1, the area of the 4th touch-down zone 122A is equal to or less than the
The area of three touch-down zone 116A.In one embodiment, as it is shown in figure 1, the number of the 4th guide hole 126
Mesh is equal to or less than the number of the 3rd guide hole 120.In one embodiment, as it is shown in figure 1, the 4th leads
Area of section A4 in hole 126 is equal to or more than area of section A3 of the 3rd guide hole 120.But, this
Invention is not limited to this.
According to an embodiment, redistribution layer 130 can be formed by copper (Cu) or tungsten (W).According to an embodiment,
First guide hole the 108, second guide hole the 114, the 3rd guide hole 120 and the 4th guide hole 126 can be by copper or tungsten
Formed.According to an embodiment, first dielectric layer the 106, second dielectric layer the 112, the 3rd dielectric layer 118
And the 4th dielectric layer 124 be to be formed by the material of the material being different from dielectric enclosure layer 128.Citing comes
Say, the first dielectric layer the 106, second dielectric layer the 112, the 3rd dielectric layer 118 and the 4th dielectric layer 124
Can be formed by oxide, dielectric enclosure layer 128 can be formed by the polyimides of heliosensitivity.
Referring now to Fig. 3 A～Fig. 3 F, it illustrates the semiconductor package 100 according to an embodiment
Manufacture method.
Refer to Fig. 3 A, a substrate 102 arranges one first chip 104, and at the first chip
One first dielectric layer 106 is formed on 104.First chip 104 has one first touch-down zone 104A.This
Outward, one second chip 110 can be set between substrate 102 and the first chip 104, and at the second core
One second dielectric layer 112 is formed between sheet 110 and the first chip 104.Second chip 110 has not
The one second touch-down zone 110A covered by the first chip 104.Can be at substrate 102 and the second chip 110
Between one the 3rd chip 116 is set, and between the 3rd chip 116 and the second chip 110, form one
3rd dielectric layer 118.3rd chip 116 has one the 3rd landing not covered by the second chip 110
District 116A.One fourth chip 122 can be set between substrate 102 and the 3rd chip 116, and
One the 4th dielectric layer 124 is formed between four chips 122 and the 3rd chip 116.Fourth chip 122 has
There is one the 4th touch-down zone 122A not covered by the 3rd chip 116.In one embodiment, first is situated between
Electric layer the 106, second dielectric layer the 112, the 3rd dielectric layer 118 and the 4th dielectric layer 124 are by aoxidizing
Thing is formed.
According to an embodiment, the area of the first touch-down zone 104A can equal to or more than the second touch-down zone
The area of 110A, the area of the second touch-down zone 110A can be equal to or more than the 3rd touch-down zone 116A's
Area, and/or the area of the 3rd touch-down zone 116A can be equal to or more than the face of the 4th touch-down zone 122A
Long-pending.Consequently, it is possible to need the chip of more interconnection structure can be positioned over the top, and have bigger
Touch-down zone.
Refer to Fig. 3 B, form a dielectric enclosure layer 128.Dielectric enclosure layer 128 is by the first chip
104 and first dielectric layer 106 be packaged in wherein.Dielectric enclosure layer 128 also can by the second chip 110,
Second dielectric layer the 112, the 3rd chip the 116, the 3rd dielectric layer 118, fourth chip 122 and the 4th are situated between
Electric layer 124 is packaged in wherein.Dielectric enclosure layer 128 can be by being different from the first dielectric layer 106, second
The material of the material of dielectric layer the 112, the 3rd dielectric layer 118 and the 4th dielectric layer 124 is formed.One
In embodiment, dielectric enclosure layer 128 is to be formed by the polyimides of heliosensitivity, it is prone to carry out to process,
And there is the advantage on cost.It is also possible, however, to use other materials.
Refer to Fig. 3 C, form at least one first perforation O1 through dielectric enclosure layer 128.Can be same
Time formed through dielectric enclosure layer 128 at least one second perforation O2, at least one the 3rd perforation O3 and
At least one the 4th perforation O4.First perforation O1, the second perforation O2, the 3rd perforation O3 and the 4th wear
Hole O4 corresponds respectively to the first touch-down zone 104A, the second touch-down zone 110A, the 3rd touch-down zone 116A
And the 4th touch-down zone 122A.First perforation O1, the second perforation O2, the 3rd perforation O3 and the 4th wear
Hole O4 can be formed by photoetching process (lithography process).Optionally carry out baking process
(baking process) (for the polyimides of heliosensitivity, be not required to carry out this technique).
According to an embodiment, the number of the first perforation O1 can be equal to or more than the number of the second perforation O2
Mesh, the number of the second perforation O2 can equal to or more than the number of the 3rd perforation O3, and/or the 3rd wears
The number of hole O3 can be equal to or more than the number of the 4th perforation O4.Thus, it is possible to provide more
Guide hole give and be positioned at the top, need the chip of more interconnection structure.
According to an embodiment, the area of section of the first perforation O1 can be equal to or less than the second perforation O2
The area of section, second perforation O2 the area of section can equal to or less than the 3rd perforation O3 section
Area, and/or the area of section of the 3rd perforation O3 can be equal to or less than the section face of the 4th perforation O4
Long-pending.Owing to needing the chip of more interconnection structure to may be disposed at the top, the penetration depth of its correspondence can
With shallower.Consequently, it is possible to these perforation can have the less area of section, therefore the density of perforation can be
Improve.And the deeper perforation of the degree of depth can have the bigger area of section, therefore available bigger technique
Permissible range (process window).
Refer to Fig. 3 D, extend the first perforation O1, through the first dielectric layer 106 to the first chip 104
The first touch-down zone 104A.Meanwhile, extensible second perforation O2, through the second dielectric layer 112 to
Second touch-down zone 110A of the second chip 110.Extensible 3rd perforation O3, through the 3rd dielectric layer
3rd touch-down zone 116A of 118 to the 3rd chips 116.Further, extensible 4th perforation O4, wears
Cross the 4th touch-down zone 122A of the 4th dielectric layer 124 to fourth chip 122.The first perforation extended
O1 ', the second perforation O2 ', the 3rd perforation O3 ' and the 4th perforation O4 ' can be formed by etching technics.Phase
Compared with the straight-through silicon perforation formed through silicon substrate, the first perforation O1 ', the second perforation O2 ', the
Three perforation O3 ' and the 4th perforation O4 ' can be formed in easier mode, and therefore its yield is not constituted
Problem.Furthermore, owing to only carrying out a photoetching process and an etching technics, cost can reduce.
Refer to Fig. 3 E, conductor filled to the first perforation O1 ' by one, it is connected to the first core to be formed
At least one first guide hole 108 of the first touch-down zone 104A of sheet 104.Meanwhile, can be by conductor filled
To the second perforation O2 ', it is connected to the second touch-down zone 110A of the second chip 110 extremely to be formed
Few one second guide hole 114.The 3rd can be connected to be formed by conductor filled to the 3rd perforation O3 '
At least one the 3rd guide hole 120 of the 3rd touch-down zone 116A of chip 116.Further, conductor can be filled out
It is charged in the 4th perforation O4 ', is connected to the 4th touch-down zone 122A's of fourth chip 122 with formation
At least one the 4th guide hole 126.Conductor can be such as copper or tungsten.
The number of the first guide hole 108 can be equal to or more than the number of the second guide hole 114, the second guide hole 114
Number can be equal to or more than the number of the 3rd guide hole 120, and/or the number of the 3rd guide hole 120 can wait
In or more than the number of the 4th guide hole 126.Area of section A1 of the first guide hole 108 can be equal to or little
In area of section A2 of the second guide hole 114, area of section A2 of the second guide hole 114 can be equal to or little
In area of section A3 of the 3rd guide hole 120, and/or area of section A3 of the 3rd guide hole 120 can wait
In or less than area of section A4 of the 4th guide hole 126.
Owing to first guide hole the 108, second guide hole the 114, the 3rd guide hole 120 and the 4th guide hole 126 can
Being formed by identical step, therefore cost will not be affected by the number of guide hole and size.Additionally, the
The area of section of one guide hole the 108, second guide hole the 114, the 3rd guide hole 120 and the 4th guide hole 126 can
With only about 2 microns × 2 microns, the size of the connection pad generally used in connecting much smaller than routing is (such as
60 microns × 60 microns), therefore the density of conductive path can significantly promote.
Refer to Fig. 3 F, a redistribution layer 130 can be formed on dielectric enclosure layer 128.Redistribution layer 130
It is connected to the first guide hole 108.Redistribution layer 130 is also connected to the second guide hole the 114, the 3rd guide hole 120
And the 4th guide hole 126.Redistribution layer 130 can be formed by copper or tungsten.
In sum, although the present invention is disclosed above with preferred embodiment, and so it is not limited to
The present invention.Persond having ordinary knowledge in the technical field of the present invention, in the spirit without departing from the present invention
With in scope, when can make various changes with retouching.Therefore, protection scope of the present invention is when depending on enclosing
Being as the criterion of being defined of right.
Claims (10)
1. a semiconductor package, including:
One substrate；
One first chip, is arranged on this substrate, and this first chip has one first touch-down zone；
One first dielectric layer, is arranged on this first chip；
One dielectric enclosure layer, is packaged in this first chip and this first dielectric layer wherein；And
At least one first guide hole, runs through this dielectric enclosure layer and this first dielectric layer, and this is at least one first years old
Guide hole is connected to this first touch-down zone of this first chip.
Semiconductor package the most according to claim 1, further includes:
One redistribution layer, is arranged on this dielectric enclosure layer, and this redistribution layer is connected to this and at least one first leads
Hole.
Semiconductor package the most according to claim 2, further includes:
One second chip, is arranged between this substrate and this first chip, this second chip have not by
One second touch-down zone that this first chip covers；
One second dielectric layer, is arranged between this second chip and this first chip, wherein this dielectric envelope
This second chip and this second dielectric layer are more packaged in wherein by dress layer；And
At least one second guide hole, runs through this dielectric enclosure layer and this second dielectric layer, and this is at least one second years old
Guide hole is connected to this second touch-down zone of this second chip, wherein this redistribution layer be further connected to this at least one
Second guide hole.
Semiconductor package the most according to claim 3, the wherein face in this second touch-down zone
The long-pending area equal to or less than this first touch-down zone.
Semiconductor package the most according to claim 3, wherein this at least one second guide hole
Number equal to or less than the number of this at least one first guide hole.
Semiconductor package the most according to claim 3, wherein this at least one second guide hole
The area of section equal to or more than the area of section of this at least one first guide hole.
Semiconductor package the most according to claim 1, wherein this dielectric enclosure layer be by
The polyimides of heliosensitivity is formed.
8. a manufacture method for semiconductor package, including:
One first chip is set on a substrate, and on this first chip, forms one first dielectric layer,
Wherein this first chip has one first touch-down zone；
Form a dielectric enclosure layer, this first chip and this first dielectric layer are packaged in wherein；
Form at least one first perforation through this dielectric enclosure layer；
Extend this at least one first perforation, through this first dielectric layer to this first chip this first
Land district；And
Conductor filled to this at least one first perforation by one, it is connected to being somebody's turn to do of this first chip to be formed
At least one first guide hole in the first touch-down zone.
The manufacture method of semiconductor package the most according to claim 8, further includes:
Forming a redistribution layer on this dielectric enclosure layer, this redistribution layer is connected to this at least one first guide hole.
The manufacture method of semiconductor package the most according to claim 9,
Wherein in arranging this first chip on the substrate, and on this first chip, form this first Jie
The step of electric layer, arranges one second chip between this substrate and this first chip, and at this second core
Between sheet and this first chip formed one second dielectric layer, wherein this second chip have not by this first
One second touch-down zone that chip covers, and this dielectric enclosure layer is more by this second chip and this second dielectric
Layer is packaged in wherein；
Wherein in forming this at least one first step bored a hole through this dielectric enclosure layer, concurrently form
At least one second perforation through this dielectric enclosure layer；
Wherein in extending this at least one first perforation, through this first dielectric layer being somebody's turn to do to this first chip
The step in the first touch-down zone, extends this at least one second perforation, through this second dielectric layer to being somebody's turn to do simultaneously
This second touch-down zone of second chip；
Wherein in step to this at least one first perforation that this is conductor filled, this conductor is filled out simultaneously
It is charged in this at least one second perforation, is connected to this second touch-down zone of this second chip extremely to be formed
Few one second guide hole；And
Wherein this redistribution layer is further connected to this at least one second guide hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510147264.4A CN106158775A (en) | 2015-03-31 | 2015-03-31 | Semiconductor package and manufacture method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510147264.4A CN106158775A (en) | 2015-03-31 | 2015-03-31 | Semiconductor package and manufacture method thereof |
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|---|---|---|---|---|
| US20060125072A1 (en) * | 2004-12-14 | 2006-06-15 | Casio Computer Co., Ltd. | Semiconductor device having laminated semiconductor constructions and a manufacturing method thereof |
| US20100193930A1 (en) * | 2009-02-02 | 2010-08-05 | Samsung Electronics Co., Ltd. | Multi-chip semiconductor devices having conductive vias and methods of forming the same |
| US20120032340A1 (en) * | 2010-08-06 | 2012-02-09 | Stats Chippac, Ltd. | Semiconductor Die and Method of Forming FO-WLCSP Vertical Interconnect Using TSV and TMV |
| CN103872027A (en) * | 2012-12-10 | 2014-06-18 | 财团法人工业技术研究院 | Stack type power element module |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060125072A1 (en) * | 2004-12-14 | 2006-06-15 | Casio Computer Co., Ltd. | Semiconductor device having laminated semiconductor constructions and a manufacturing method thereof |
| US20100193930A1 (en) * | 2009-02-02 | 2010-08-05 | Samsung Electronics Co., Ltd. | Multi-chip semiconductor devices having conductive vias and methods of forming the same |
| US20120032340A1 (en) * | 2010-08-06 | 2012-02-09 | Stats Chippac, Ltd. | Semiconductor Die and Method of Forming FO-WLCSP Vertical Interconnect Using TSV and TMV |
| CN103872027A (en) * | 2012-12-10 | 2014-06-18 | 财团法人工业技术研究院 | Stack type power element module |
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