CN106158758B - Mask plate component, the preparation method of integrated circuit board and integrated circuit board - Google Patents
Mask plate component, the preparation method of integrated circuit board and integrated circuit board Download PDFInfo
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- CN106158758B CN106158758B CN201510163074.1A CN201510163074A CN106158758B CN 106158758 B CN106158758 B CN 106158758B CN 201510163074 A CN201510163074 A CN 201510163074A CN 106158758 B CN106158758 B CN 106158758B
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Abstract
The present invention provides the preparation methods and integrated circuit board of a kind of mask plate component, integrated circuit board, wherein, mask plate component includes: the first mask plate, it is provided with the first light-transparent pattern and the first impermeable light pattern, first mask plate is for the first time photoetching process processing in the preparation process of the integrated circuit board, wherein, first light-transparent pattern includes the figure of the Patterned masking layer above the first resistor rate structure sheaf to be prepared；Second mask plate, it is provided with the second light-transparent pattern and the second impermeable light pattern, second mask plate is for second of photoetching process processing in the preparation process of the integrated circuit board, wherein second light-transparent pattern includes the figure of the second resistance rate grid to be prepared.According to the technical solution of the present invention, at least two processing methods can be used to prepare above-mentioned integrated circuit board, reduce the processing cost of photoetching process, convenient for batch production integrated circuit board during carry out process optimization.
Description
Technical field
The present invention relates to ic manufacturing technology fields, in particular to a kind of mask plate component, a kind of integrated electricity
The preparation method of road plate and a kind of integrated circuit board.
Background technique
In the related art, integrated circuit board during the preparation process, generallys use a set of mask plate component to complete one kind
The manufacturing process of integrated circuit board, user during integrated design circuit board, if it is desired to verifying different process method can
Row and reliability, it is necessary to which preparation covers mask plate, and the cost of manufacture of mask plate component is high (thousands of to tens of thousands of), this just makes
At the raising of design cost, it is unfavorable for improving technique production method and Optimizing Technical.
Therefore, the system of a kind of mask plate component for being compatible with a variety of preparation methods and corresponding integrated circuit board how is designed
Standby scheme becomes technical problem urgently to be resolved.
Summary of the invention
The present invention is based at least one above-mentioned technical problem, and it is integrated to propose the new mask plate component of one kind, one kind
The preparation method of circuit board and a kind of integrated circuit board.
In view of this, the invention proposes a kind of mask plate components, comprising: the first mask plate is provided with the first light transmission figure
Case and the first impermeable light pattern, first mask plate is for the first time photoetching work in the preparation process of the integrated circuit board
Skill processing, wherein first light-transparent pattern includes the pattern mask above the first resistor rate structure sheaf to be prepared
The figure of layer；Second mask plate is provided with the second light-transparent pattern and the second impermeable light pattern, and second mask plate is for described
Second of photoetching process processing in the preparation process of integrated circuit board, wherein second light-transparent pattern includes to be prepared
The figure of the second resistance rate grid.
It in the technical scheme, can be using extremely by having rationally designed the pattern of the first mask plate and the second mask plate
Few two kinds of processing methods reduce the processing cost of photoetching process to prepare above-mentioned integrated circuit board, convenient for batch production collection
Process optimization is carried out during at circuit board.
Specifically, during integrated circuit prepares two kinds of resistivity structures, usually there are two types of processing methods:
Method one: carrying out ion implanting processing or doping treatment using Twi-lithography respectively, to form different ions concentration
Region；Processing is patterned to the region of different ions concentration.
Method two: the ion implanting processing or doping treatment of first area are carried out after first time photoetching, and to first area
It is patterned；The ion implanting processing or doping treatment of second area are carried out after second of photoetching, and first area is carried out
Graphically.
And under different process conditions, the reliability and performance of the integrated circuit of above two method preparation are can not
Precognition, especially in the case where the line width of integrated circuit varies widely, the mask plate that needs to propose through the invention
Component verifies the feasibility of technique and the reliability of device, to realize the batch production of integrated circuit, meanwhile, reduction is designed to
This.
Wherein, before carrying out first time photoetching, i.e., completion first time ion implanting or doping treatment, the first mask plate are used for
The window of reserved second of ion implanting, the second mask plate are used for the structure sheaf of graphical two kinds of different resistivities, can be simultaneously
Complete the preparation of mutually isostructural integrated circuit using the above method one and method two, and then comparative approach one and method two is excellent
It is anisotropic.
In the above-mentioned technical solutions, it is preferable that first light-transparent pattern and the Patterned masking layer to be prepared
Figure is consistent.
In the technical scheme, consistent with the image of Patterned masking layer by the first light-transparent pattern of setting, graphically cover
The reserved window of film layer is used to form the figure of first resistor rate structure sheaf, at this point it is possible to using method one in second of photoetching
Etching forms first resistor rate structure sheaf and second resistance rate grid afterwards, or is performed etching after first time photoetching using method two
To obtain second resistance rate grid.
In the above-mentioned technical solutions, it is preferable that second light-transparent pattern and the second resistance rate grid to be prepared
Figure it is consistent.
In the technical scheme, consistent with the figure of second resistance rate grid by the second light-transparent pattern of design, it can obtain
The excellent second resistance rate grid of lines is obtained, forms first resistor at this point it is possible to etch after second of photoetching using method one
Rate structure sheaf and second resistance rate grid, or use method two to perform etching after first time photoetching to obtain second resistance rate grid
Pole.
According to another aspect of the present invention, it is also proposed that a kind of preparation method of integrated circuit board, comprising: forming first
Mask layer is formed on the substrate of resistivity polysilicon layer；First time photoetching is carried out to the mask layer using first mask plate
Process, to form Patterned masking layer；The grid of second resistance rate are formed on the substrate for forming the Patterned masking layer
Polar region domain；After except the Patterned masking layer, using second mask plate to described the first of the formation area of grid
Resistivity polysilicon layer carries out second of photoetching process processing, to form the first resistor rate structure sheaf and second resistance rate grid
Pole, wherein the pattern of the first resistor rate polysilicon layer includes the figure of the first resistor rate structure sheaf, the gate regions
Domain includes the figure of the second resistance rate grid.
In the technical scheme, by after first time photoetching carry out second resistance rate area of grid (ion implanting or
Doping treatment), and second resistance rate grid and first resistor rate structure sheaf are once formed after second of photoetching, it reduces to quarter
The requirement for losing the alignment precision of second resistance rate grid and first resistor rate structure sheaf thereby reduces manufacturing cost and is designed to
This.
In the above-mentioned technical solutions, it is preferable that before forming mask layer on the substrate for forming first resistor rate polysilicon layer,
Comprising the following specific steps forming polysilicon layer on the substrate by chemical vapor deposition method；To the polysilicon layer
The second doping process processing is carried out to form the first resistor rate polysilicon layer.
In the technical scheme, it by carrying out second of doping process processing to the unlapped polysilicon layer of mask layer, mentions
The high ion concentration of the polysilicon layer in specified region, and then get ready to form low-resistivity grid, complete second
After secondary ion injection, the measurement of ion concentration, the technique that can effectively improve grid are carried out using four probe method to specified region
Accuracy.
In the above-mentioned technical solutions, it is preferable that second resistance rate is formed on the substrate for forming the Patterned masking layer
Area of grid, comprising the following specific steps to the mask layer after photoetching using at wet etching and/or dry etching
Reason, to form the Patterned masking layer of the first resistor rate structure sheaf to be prepared.
In the technical scheme, by forming Patterned masking layer, it can be used for the second doping process, or in the second doping
After technique, direct etching forms first resistor rate structure sheaf.
In the above-mentioned technical solutions, it is preferable that first time photoetching is carried out to the mask layer using first mask plate
Process, to form Patterned masking layer, comprising the following specific steps to forming described the first of the Patterned masking layer
The polysilicon layer of resistivity carries out the first doping process processing, in the formation second resistance of the first resistor rate polysilicon layer
The area of grid of rate.
According to the third aspect of the invention we, it is also proposed that a kind of preparation method of integrated circuit board, comprising: forming first
Mask layer is formed on the substrate of resistivity polysilicon layer；First time photoetching is carried out to the mask layer using first mask plate
Process, to form Patterned masking layer；The first resistor rate polysilicon layer is carried out based on the Patterned masking layer
Etching processing, to form the first resistor rate structure sheaf；Form the area of grid of second resistance rate；Using second exposure mask
Version carries out second of photoetching process processing to the area of grid；To the grid by second of photoetching process processing
Region carries out photoetching, to form the second resistance rate grid.
In the technical scheme, it after by forming first resistor rate polysilicon layer, deposits, adulterate, etched to be formed again
Second resistance rate grid, has been prepared apart the integrated circuit for having the structure of two kinds of conductivity.
In the above-mentioned technical solutions, it is preferable that the area of grid of second resistance rate is formed, comprising the following specific steps logical
It crosses chemical vapor deposition method processing and forms the polysilicon layer adulterated in situ on the substrate, wherein is described to adulterate in situ
Polysilicon layer is as the area of grid.
According to the fourth aspect of the invention, it is also proposed that a kind of integrated circuit board, using such as any of the above-described technical solution
The preparation method of the integrated circuit board is prepared.
By above technical scheme, by having rationally designed the pattern of the first mask plate and the second mask plate, can use
At least two processing methods reduce the processing cost of photoetching process to prepare above-mentioned integrated circuit board, convenient for batch production
Process optimization is carried out during integrated circuit board.
Detailed description of the invention
Figure 1A shows the pattern schematic diagram of the first mask plate according to an embodiment of the invention；
Figure 1B shows the pattern schematic diagram of the first mask plate according to an embodiment of the invention；
Fig. 2A shows the pattern schematic diagram of the first mask plate according to another embodiment of the invention；
Fig. 2 B shows the pattern schematic diagram of the first mask plate according to another embodiment of the invention；
Fig. 3 A shows the pattern schematic diagram of the first mask plate of still another embodiment in accordance with the present invention；
Fig. 3 B shows the pattern schematic diagram of the first mask plate of still another embodiment in accordance with the present invention；
Fig. 4 shows the schematic flow diagram of the preparation method of integrated circuit board according to an embodiment of the invention；
Fig. 5 shows the schematic flow diagram of the preparation method of integrated circuit board according to another embodiment of the invention；
Fig. 6 A shows the diagrammatic cross-section of the preparation method of integrated circuit board according to an embodiment of the invention；
Fig. 6 B shows the diagrammatic cross-section of the preparation method of integrated circuit board according to another embodiment of the invention；
Fig. 6 C shows the diagrammatic cross-section of the preparation method of the integrated circuit board of still another embodiment in accordance with the present invention；
Fig. 7 A shows the diagrammatic cross-section of the preparation method of integrated circuit board according to an embodiment of the invention；
Fig. 7 B shows the diagrammatic cross-section of the preparation method of integrated circuit board according to another embodiment of the invention.
Specific embodiment
To better understand the objects, features and advantages of the present invention, with reference to the accompanying drawing and specific real
Applying mode, the present invention is further described in detail.It should be noted that in the absence of conflict, the implementation of the application
Feature in example and embodiment can be combined with each other.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, still, the present invention may be used also
To be implemented using other than the one described here other modes, therefore, protection scope of the present invention is not by described below
Specific embodiment limitation.
Figure 1A, 1B, 2A, 2B, 3A and 3B show the various embodiments of the mask plate component of embodiment according to the present invention
Schematic diagram, the mask plate component of embodiment according to the present invention, comprising: the first mask plate, be provided with the first light-transparent pattern and
First impermeable light pattern, first mask plate are used at the first time photoetching process in the preparation process of the integrated circuit board
Reason, wherein first light-transparent pattern includes the Patterned masking layer above the first resistor rate structure sheaf to be prepared
Figure；Second mask plate is provided with the second light-transparent pattern and the second impermeable light pattern, and second mask plate is for described integrated
Second of photoetching process processing in the preparation process of circuit board, wherein second light-transparent pattern includes to be prepared described
The figure of second resistance rate grid.
It in the technical scheme, can be using extremely by having rationally designed the pattern of the first mask plate and the second mask plate
Few two kinds of processing methods reduce the processing cost of photoetching process to prepare above-mentioned integrated circuit board, convenient for batch production collection
Process optimization is carried out during at circuit board.
Specifically, during integrated circuit prepares two kinds of resistivity structures, usually there are two types of processing methods:
Method one: carrying out ion implanting processing or doping treatment using Twi-lithography respectively, to form different ions concentration
Region；Processing is patterned to the region of different ions concentration.
Method two: the ion implanting processing or doping treatment of first area are carried out after first time photoetching, and to first area
It is patterned；The ion implanting processing or doping treatment of second area are carried out after second of photoetching, and first area is carried out
Graphically.
And under different process conditions, the reliability and performance of the integrated circuit of above two method preparation are can not
Precognition, especially in the case where the line width of integrated circuit varies widely, the mask plate that needs to propose through the invention
Component verifies the feasibility of technique and the reliability of device, to realize the batch production of integrated circuit, meanwhile, reduction is designed to
This.
Wherein, before carrying out first time photoetching, i.e., completion first time ion implanting or doping treatment, the first mask plate are used for
The window of reserved second of ion implanting, the second mask plate are used for the structure sheaf of graphical two kinds of different resistivities, can be simultaneously
Complete the preparation of mutually isostructural integrated circuit using the above method one and method two, and then comparative approach one and method two is excellent
It is anisotropic.
In the above-mentioned technical solutions, it is preferable that first light-transparent pattern and the Patterned masking layer to be prepared
Figure is consistent.
In the technical scheme, consistent with the image of Patterned masking layer by the first light-transparent pattern of setting, graphically cover
The reserved window of film layer is used to form the figure of first resistor rate structure sheaf, at this point it is possible to using method one in second of photoetching
Etching forms first resistor rate structure sheaf and second resistance rate grid afterwards, or is performed etching after first time photoetching using method two
To obtain second resistance rate grid.
In the above-mentioned technical solutions, it is preferable that second light-transparent pattern and the second resistance rate grid to be prepared
Figure it is consistent.
In the technical scheme, consistent with the figure of second resistance rate grid by the second light-transparent pattern of design, it can obtain
The excellent second resistance rate grid of lines is obtained, forms first resistor at this point it is possible to etch after second of photoetching using method one
Rate structure sheaf and second resistance rate grid, or use method two to perform etching after first time photoetching to obtain second resistance rate grid
Pole.
In the case where all lithography steps are all made of negtive photoresist, first group of implementation of Figure 1A and Figure 1B composition mask plate component
Mode, Fig. 2A and Fig. 2 B constitute second group of embodiment of mask plate component, and Fig. 3 A and Fig. 3 B constitute the third of mask plate component
Group embodiment.
Fig. 4 shows the schematic flow diagram of the preparation method of integrated circuit board according to an embodiment of the invention.
As shown in figure 4, the preparation method of integrated circuit board according to an embodiment of the invention, comprising: step 402,
Mask layer is formed on the substrate for forming first resistor rate polysilicon layer；Step 404, it is covered using first mask plate to described
Film layer carries out the processing of first time photoetching process, to form Patterned masking layer；Step 406, the Patterned masking layer is being formed
Substrate on formed second resistance rate area of grid；Step 408, after except the Patterned masking layer, using described second
Mask plate carries out second of photoetching process processing to the first resistor rate polysilicon layer for forming the area of grid, to be formed
The first resistor rate structure sheaf and second resistance rate grid, wherein the pattern of the first resistor rate polysilicon layer includes institute
The figure of first resistor rate structure sheaf is stated, the area of grid includes the figure of the second resistance rate grid.
In the technical scheme, by after first time photoetching carry out second resistance rate area of grid (ion implanting or
Doping treatment), and second resistance rate grid and first resistor rate structure sheaf are once formed after second of photoetching, it reduces to quarter
The requirement for losing the alignment precision of second resistance rate grid and first resistor rate structure sheaf thereby reduces manufacturing cost and is designed to
This.
In the above-mentioned technical solutions, it is preferable that before forming mask layer on the substrate for forming first resistor rate polysilicon layer,
Comprising the following specific steps forming polysilicon layer on the substrate by chemical vapor deposition method；To the polysilicon layer
The second doping process processing is carried out to form the first resistor rate polysilicon layer.
In the technical scheme, it by carrying out second of doping process processing to the unlapped polysilicon layer of mask layer, mentions
The high ion concentration of the polysilicon layer in specified region, and then get ready to form low-resistivity grid, complete second
After secondary ion injection, the measurement of ion concentration, the technique that can effectively improve grid are carried out using four probe method to specified region
Accuracy.
In the above-mentioned technical solutions, it is preferable that second resistance rate is formed on the substrate for forming the Patterned masking layer
Area of grid, comprising the following specific steps to the mask layer after photoetching using at wet etching and/or dry etching
Reason, to form the Patterned masking layer of the first resistor rate structure sheaf to be prepared.
In the technical scheme, by forming Patterned masking layer, it can be used for the second doping process, or in the second doping
After technique, direct etching forms first resistor rate structure sheaf.
In the above-mentioned technical solutions, it is preferable that first time photoetching is carried out to the mask layer using first mask plate
Process, to form Patterned masking layer, comprising the following specific steps to forming described the first of the Patterned masking layer
The polysilicon layer of resistivity carries out the first doping process processing, in the formation second resistance of the first resistor rate polysilicon layer
The area of grid of rate.
Fig. 5 shows the schematic flow diagram of the preparation method of integrated circuit board according to another embodiment of the invention.
As shown in figure 5, the preparation method of integrated circuit board according to another embodiment of the invention, comprising: step
502, mask layer is formed on the substrate for forming first resistor rate polysilicon layer；Step 504, using first mask plate to institute
It states mask layer and carries out the processing of first time photoetching process, to form Patterned masking layer；Step 506, it is based on the pattern mask
Layer performs etching processing to the first resistor rate polysilicon layer, to form the first resistor rate structure sheaf；Step 508, shape
At the area of grid of second resistance rate；Step 510, second of photoetching is carried out to the area of grid using second mask plate
Process；Step 512, photoetching is carried out to the area of grid by second of photoetching process processing, to be formed
State second resistance rate grid.
In the technical scheme, it after by forming first resistor rate polysilicon layer, deposits, adulterate, etched to be formed again
Second resistance rate grid, has been prepared apart the integrated circuit for having the structure of two kinds of conductivity.
In the above-mentioned technical solutions, it is preferable that the area of grid of second resistance rate is formed, comprising the following specific steps logical
It crosses chemical vapor deposition method processing and forms the polysilicon layer adulterated in situ on the substrate, wherein is described to adulterate in situ
Polysilicon layer is as the area of grid.
It is carried out in conjunction with preparation process of Fig. 6 A to Fig. 6 C to integrated circuit board according to an embodiment of the invention specific
It introduces.
As shown in Figure 6A, after forming first resistor rate polysilicon on substrate, dielectric layer is formed on its surface as exposure mask
Layer simultaneously carries out graphical treatment, and after carrying out the second doping, the region on first resistor rate polysilicon layer there is no dielectric layer is formed
The area of grid of second resistance rate.
As shown in Figure 6B, the area of grid of second resistance rate is formed during adulterating for second.
As shown in Figure 6 C, second resistance rate grid and first resistor rate structure sheaf to be formed by once etching.
It is carried out in conjunction with preparation process of Fig. 7 A to Fig. 7 B to integrated circuit board according to an embodiment of the invention specific
It introduces.
As shown in Figure 7 A, it after carrying out the first doping treatment, etches to form first resistor rate structure sheaf.
As shown in Figure 7 B, second of deposition process is carried out, and forms second resistance rate grid by the second doping and etching.
The technical scheme of the present invention has been explained in detail above with reference to the attached drawings, it is contemplated that how to design one kind and is compatible with a variety of systems
The technical issues of preparation method of the mask plate component of Preparation Method and corresponding integrated circuit board.Therefore, the invention proposes one
The new mask plate component of kind, a kind of preparation method of integrated circuit board and a kind of integrated circuit board, by having rationally designed first
The pattern of mask plate and the second mask plate can use at least two processing methods to prepare above-mentioned integrated circuit board, reduce
The processing cost of photoetching process, convenient for batch production integrated circuit board during carry out process optimization.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of mask plate component, suitable for preparing the integrated circuit including first resistor rate structure sheaf and second resistance rate grid
Plate, which is characterized in that the mask plate component includes:
First mask plate is provided with the first light-transparent pattern and the first impermeable light pattern, and first mask plate is for described integrated
First time photoetching process processing in the preparation process of circuit board, wherein first light-transparent pattern includes to be prepared described
The figure of Patterned masking layer above first resistor rate structure sheaf；
Second mask plate is provided with the second light-transparent pattern and the second impermeable light pattern, and second mask plate is for described integrated
Second of photoetching process processing in the preparation process of circuit board, wherein second light-transparent pattern includes to be prepared described
The figure of second resistance rate grid；
First mask plate is used to reserve the window of second of ion implanting, and second mask plate is used for graphical two kinds not
With the structure sheaf of resistivity.
2. mask plate component according to claim 1, which is characterized in that first light-transparent pattern with it is to be prepared described
The figure of Patterned masking layer is consistent.
3. mask plate component according to claim 2, which is characterized in that second light-transparent pattern with it is to be prepared described
The figure of second resistance rate grid is consistent.
4. a kind of preparation method of integrated circuit board, the integrated circuit board includes first resistor rate structure sheaf and second resistance rate
The photoetching process processing of grid, the integrated circuit board uses mask plate component as claimed in claim 1 or 2, and feature exists
In the preparation method includes:
Mask layer is formed on the substrate for forming first resistor rate polysilicon layer；
The processing of first time photoetching process is carried out to the mask layer using first mask plate, to form Patterned masking layer；
The area of grid of second resistance rate is formed on the substrate for forming the Patterned masking layer；
After except the Patterned masking layer, using second mask plate to the first resistor for forming the area of grid
Rate polysilicon layer carries out second of photoetching process processing, to form the first resistor rate structure sheaf and second resistance rate grid,
Wherein, the pattern of the first resistor rate polysilicon layer includes the figure of the first resistor rate structure sheaf, the grid
Region includes the figure of the second resistance rate grid.
5. the preparation method of integrated circuit board according to claim 4, which is characterized in that forming first resistor rate polycrystalline
Before forming mask layer on the substrate of silicon layer, comprising the following specific steps
Polysilicon layer is formed on the substrate by chemical vapor deposition method；
Second doping process processing is carried out to form the first resistor rate polysilicon layer to the polysilicon layer.
6. the preparation method of integrated circuit board according to claim 4, which is characterized in that forming the pattern mask
The area of grid of second resistance rate is formed on the substrate of layer, comprising the following specific steps
The mask layer after photoetching is handled using wet etching and/or dry etching, to form to be prepared described first
The Patterned masking layer of resistivity structure layer.
7. the preparation method of integrated circuit board according to claim 4, which is characterized in that use first mask plate pair
The mask layer carries out the processing of first time photoetching process, to form Patterned masking layer, comprising the following specific steps
First doping process processing is carried out to the polysilicon layer for the first resistor rate for forming the Patterned masking layer, with
The area of grid of the formation second resistance rate of the first resistor rate polysilicon layer.
8. a kind of preparation method of integrated circuit board, the integrated circuit board includes first resistor rate structure sheaf and second resistance rate
The photoetching process processing of grid, the integrated circuit board uses mask plate component as claimed in claim 1 or 2, and feature exists
In the preparation method includes:
Mask layer is formed on the substrate for forming first resistor rate polysilicon layer；
The processing of first time photoetching process is carried out to the mask layer using first mask plate, to form Patterned masking layer；
Processing is performed etching to the first resistor rate polysilicon layer based on the Patterned masking layer, to form first electricity
Resistance rate structure sheaf；
Form the area of grid of second resistance rate；
Second of photoetching process processing is carried out to the area of grid using second mask plate；
Photoetching is carried out to the area of grid by second of photoetching process processing, to form the second resistance rate grid
Pole.
9. the preparation method of integrated circuit board according to claim 8, which is characterized in that form the grid of second resistance rate
Region, comprising the following specific steps
It is handled by chemical vapor deposition method and forms the polysilicon layer adulterated in situ on the substrate, wherein the original position
The polysilicon layer of doping is as the area of grid.
10. a kind of integrated circuit board, which is characterized in that using the integrated circuit board as described in any one of claim 4 to 9
Preparation method is prepared.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510163074.1A CN106158758B (en) | 2015-04-08 | 2015-04-08 | Mask plate component, the preparation method of integrated circuit board and integrated circuit board |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510163074.1A CN106158758B (en) | 2015-04-08 | 2015-04-08 | Mask plate component, the preparation method of integrated circuit board and integrated circuit board |
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| CN106158758A CN106158758A (en) | 2016-11-23 |
| CN106158758B true CN106158758B (en) | 2018-12-28 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101826458A (en) * | 2009-03-02 | 2010-09-08 | 中芯国际集成电路制造(上海)有限公司 | Etching method and double-depth groove formation method |
| CN101996945A (en) * | 2009-08-17 | 2011-03-30 | 上海宏力半导体制造有限公司 | Method for forming semiconductor device |
| US20120056278A1 (en) * | 2010-06-22 | 2012-03-08 | Huical Zhong | Method for Manufacturing Contacts for a Semiconductor Device, and Semiconductor Device Having Such Contacts |
| CN102800576A (en) * | 2011-05-26 | 2012-11-28 | 中芯国际集成电路制造(上海)有限公司 | Method for graphing membrane layer and methods for forming gate and metal oxide semiconductor (MOS) transistor |
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2015
- 2015-04-08 CN CN201510163074.1A patent/CN106158758B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101826458A (en) * | 2009-03-02 | 2010-09-08 | 中芯国际集成电路制造(上海)有限公司 | Etching method and double-depth groove formation method |
| CN101996945A (en) * | 2009-08-17 | 2011-03-30 | 上海宏力半导体制造有限公司 | Method for forming semiconductor device |
| US20120056278A1 (en) * | 2010-06-22 | 2012-03-08 | Huical Zhong | Method for Manufacturing Contacts for a Semiconductor Device, and Semiconductor Device Having Such Contacts |
| CN102800576A (en) * | 2011-05-26 | 2012-11-28 | 中芯国际集成电路制造(上海)有限公司 | Method for graphing membrane layer and methods for forming gate and metal oxide semiconductor (MOS) transistor |
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| CN106158758A (en) | 2016-11-23 |
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