CN106158651B - The forming method and ldmos transistor of ldmos transistor - Google Patents

The forming method and ldmos transistor of ldmos transistor Download PDF

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CN106158651B
CN106158651B CN201510181790.2A CN201510181790A CN106158651B CN 106158651 B CN106158651 B CN 106158651B CN 201510181790 A CN201510181790 A CN 201510181790A CN 106158651 B CN106158651 B CN 106158651B
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fin
barrier layer
grid
source electrode
isolation
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CN106158651A (en
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李勇
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Abstract

A kind of forming method and ldmos transistor of ldmos transistor, wherein, the forming method of ldmos transistor includes: offer semiconductor substrate, and the semiconductor substrate has the first fin, the second fin and the first isolation structure between the first fin, the second fin；It is developed across the first grid structure of first fin, the first grid structure covers top and the side wall of the first fin, the first isolation structure of the first grid structure covering part；The first source electrode is formed in the first fin far from first isolation structure side of the first grid structure；Drain electrode is formed in the second fin.The performance of ldmos transistor can be improved using method of the invention.

Description

The forming method and ldmos transistor of ldmos transistor
Technical field
The present invention relates to semiconductor field more particularly to the forming methods and ldmos transistor of ldmos transistor.
Background technique
LDMOS transistor (Lateral Diffusion MOS, LDMOS), due to having High-breakdown-voltage, the characteristic compatible with CMOS technology, is widely used in power device.Compared with Conventional MOS transistors, LDMOS device at least one isolation structure between drain region and grid.When LDMOS connects high pressure, held by the isolation structure By higher voltage drop, the purpose of high-breakdown-voltage is obtained.
Referring to figs. 1 to Fig. 8, prior art discloses a kind of fin ldmos transistor, above-mentioned fin ldmos transistor Forming method is as follows:
With reference to Fig. 1 and Fig. 2, semiconductor substrate 10 is provided, the semiconductor substrate has the first fin 111, the second fin 112 and the third fin 113 between the first fin 111, the second fin 112.The length of third fin 113 is much smaller than first Fin 111 and the second fin 112.
The first fleet plough groove isolation structure 121,112 He of the second fin are formed between the first fin 111 and third fin 113 The second fleet plough groove isolation structure 122 is formed between third fin 113.First shallow trench isolation
Structure 121 and the second fleet plough groove isolation structure 122 are lower than the first fin 111 to third fin 113.
It is developed across the first grid structure 131 of the first fin 111, the first grid structure 131 covers the first fin 111 top and side wall.First grid structure 131 is polysilicon gate construction, including the first silicon oxide layer (not shown) and position In the first polysilicon layer on the first silicon oxide layer.
It is developed across the second grid structure 132 of the second fin 112, the second grid structure 132 covers the second fin 112 top and side wall.Second grid structure 132 also be polysilicon gate construction, including the second silicon oxide layer (not shown) and The second polysilicon layer on the second silicon oxide layer.
Then, with reference to Fig. 3, in first fin of the first grid structure 131 far from 121 side of the first fleet plough groove isolation structure The first source electrode groove 141a are formed in 111, second grid structure 132 far from 122 side of the second fleet plough groove isolation structure the The second source electrode groove 142a is formed in two fins 112.Drain recesses 15a is formed in third fin 113.
Then, with reference to Fig. 4, in the first source electrode groove 141a (referring to Fig. 3), the second source electrode groove 142a (referring to Fig. 3) shape At germanium silicon layer, ion implanting then is carried out to the germanium silicon layer, respectively corresponds to form the first source electrode 141 and the second source electrode 142.? Germanium silicon layer is formed in drain recesses 15a (referring to Fig. 3), ion implanting is carried out to the germanium silicon layer of drain recesses, forms drain electrode 15.Its Middle germanium silicon layer is all higher than each fin, and the source electrode and drain electrode being correspondingly formed also all is higher than each fin.
Then, with reference to Fig. 5, dielectric layer 16 is formed, covers the first fin 111, the first source electrode 141, first grid structure 131, the first fleet plough groove isolation structure 121, drain electrode 15, third fin 113, the second fleet plough groove isolation structure 122, second grid knot Structure 132, the second source electrode 142 and the second fin 112.
Then, with reference to Fig. 6, using chemical mechanical grinding method by dielectric layer 16 be ground to first grid structure 131, Second grid structure 132 is equal.
Then, with reference to Fig. 7, first grid structure 131 is removed using the method for wet etching, forms the in dielectric layer 16 One gate structure groove 171a, the first fin 111 is exposed in the bottom first grid texture grooves 171a.Remove second grid knot Structure 132, forms second grid texture grooves 172a in dielectric layer, and the bottom second grid texture grooves 172a exposes second Fin 112.
Referring next to Fig. 8, the first aluminum gate structure material layer is filled in first grid texture grooves 171a, forms first Aluminum gate structure 171.Wherein, the first aluminum gate structure 171 including the first high-k gate dielectric layer (not shown) and is located at the first high k The first aluminium layer on gate dielectric layer.It fills the second aluminum gate structure material layer in second grid texture grooves 172a, forms the Two aluminum gate structures 172.Wherein, the second aluminum gate structure 172 includes the second high-k gate dielectric layer (not shown) and is located at second high The second aluminium layer on k gate dielectric layer.
When ldmos transistor is opened, apply voltage in drain electrode 15 and the first source electrode 141, electric current can be by the first source electrode 141 During flowing to drain electrode 15, due to the presence of the first fleet plough groove isolation structure 121, the field distribution of ldmos transistor is changed Become, the first fleet plough groove isolation structure 121 bears biggish electric field.Apply voltage in drain electrode 15 and the second source electrode 142, electric current can During flowing to drain electrode 15 by the second source electrode 142, due to the presence of the second fleet plough groove isolation structure 122, the second shallow trench every It is changed from the field distribution around structure 122, the second fleet plough groove isolation structure 122 bears biggish electric field.
However, the performance of the fin ldmos transistor of the prior art is bad.
Summary of the invention
Problems solved by the invention is that the performance of the fin ldmos transistor of the prior art is bad.
To solve the above problems, the present invention provides a kind of forming method of ldmos transistor, comprising:
Semiconductor substrate is provided, the semiconductor substrate has the first fin, the second fin and is located at the first fin, second The first isolation structure between fin；
It is developed across the first grid structure of first fin, the first grid structure covers first fin Top and side wall, the first isolation structure described in the first grid structure covering part；
The first source electrode is formed in first fin of the first grid structure far from first isolation structure side；
Drain electrode is formed in second fin.
Optionally, the length of the first isolation structure described in the first grid structure covering part be more than or equal to 50nm and Less than or equal to 0.1 μm.
Optionally, it is formed before drain electrode in second fin, is developed across the first barrier layer of second fin, First barrier layer is located at second fin close to one end of the first fin and far from one end of first fin, is used for Define position and the size of drain electrode.
Optionally, it is formed before first source electrode, in the first grid structure far from first isolation structure Side forms the second barrier layer, and second barrier layer is across first fin, and second barrier layer is for defining first The position of source electrode and size.
Optionally, first barrier layer and the second barrier layer are polysilicon gate construction.
Optionally, when the first grid structure is the first metal gate structure, before forming the first source electrode and drain electrode, in institute Formation third barrier layer on the first isolation structure is stated, the first metal gate structure top depression is prevented.
Optionally, the semiconductor substrate also has third fin and between second fin, third fin Second isolation structure；
It is developed across the second grid structure of the third fin, the top of the second grid structure covering third fin And side wall；
The second source electrode is formed in the third fin far from second isolation structure side of the second grid structure.
Optionally, it is formed before second source electrode, in the second grid structure far from second isolation structure Side form the 4th barrier layer, the 4th barrier layer is across the third fin, and the 4th barrier layer is for defining the The position of two source electrodes and size.
Optionally, the 4th barrier layer is polysilicon gate construction.
Optionally, the second isolation structure of the second grid structure covering part.
Optionally, the length of the second isolation structure of the second grid structure covering part is more than or equal to 50nm and to be less than Equal to 0.1 μm.
Optionally, first first isolation structure of barrier layer covering part of described close first fin one end, it is described separate First barrier layer portions of first fin one end cover second isolation structure.
Optionally, when the second grid structure is the second metal gate structure, before forming the second source electrode, described second The 5th barrier layer is formed on isolation structure, prevents the second metal gate structure top depression.
The present invention also provides a kind of ldmos transistors, comprising:
Semiconductor substrate, the semiconductor substrate have the first fin, the second fin and are located at the first fin, the second fin Between the first isolation structure；
Across the first grid structure of first fin, the first grid structure covers the top and side of the first fin Wall；
The first source electrode in the first fin far from first isolation structure side of first grid structure；
Drain electrode in the second fin；
Further include: the first isolation structure of the first grid structure covering part.
Optionally, the length of the first isolation structure of the first grid structure covering part is more than or equal to 50nm and to be less than Equal to 0.1 μm.
Optionally, ldmos transistor of the invention further include:
Across the first barrier layer of second fin, first barrier layer is located at close the first of second fin One end of one end of fin and separate first fin, for defining position and the size of drain electrode.
Optionally, the side far from first isolation structure of the first grid structure has the second barrier layer, institute The second barrier layer is stated across first fin, the position of first source electrode of second barrier layer for defining and size.
Optionally, the semiconductor substrate also has third fin and between second fin, third fin Second isolation structure；
Across the second grid structure of the third fin, the top and side of the second grid structure covering third fin Wall；
The second source electrode in the third fin far from second isolation structure side of the second grid structure；
4th barrier layer of the side positioned at the second grid structure far from second isolation structure, the described 4th Barrier layer is across the third fin, position and size of the 4th barrier layer for the second source electrode of definition.
Optionally, have the when the first grid structure is the first metal gate structure, on first isolation structure Three barrier layers；
Have the 5th to stop when the second grid structure is the second metal gate structure, on second isolation structure Layer.
Compared with prior art, technical solution of the present invention has the advantage that
First grid structure the first isolation structure of covering part can avoid the photoetching essence generated when etching first grid structure Offset issue is spent, to avoid first grid structure and the first fin that there is distance between one end of the first isolation structure Problem.In the growth step of source electrode material layer and drain material layer, it can be avoided and leaned in first grid structure and the first fin One source electrode material layer of growth regulation in the distance between one end of nearly first isolation structure, that is to say, that can be kept away in the first fin Exempt to form contra-doping layer.In addition, increasing drop, the ldmos transistor formed afterwards can be improved with resistance to pressure.
Detailed description of the invention
Fig. 1 is the semiconductor substrate with the first fin to third fin in the fin ldmos transistor of the prior art Schematic perspective view；
Fig. 2 is the schematic diagram of the section structure of the Fig. 1 along the direction A1A1；
Fig. 3 to Fig. 8 is the schematic diagram of the section structure along the direction A1A1 to form the fin ldmos transistor of the prior art；
Fig. 9 is the semiconductor substrate with the first fin to third fin in the fin ldmos transistor of the present embodiment Schematic perspective view；
Figure 10 is the schematic diagram of the section structure of the Fig. 9 along the direction B1B1；
Figure 11 to Figure 16 is the section knot along the direction B1B1 to form the fin ldmos transistor of first embodiment of the invention Structure schematic diagram；
Figure 17 is the schematic diagram of the section structure along the direction B1B1 of the fin ldmos transistor of second embodiment of the invention.
Specific embodiment
By finding and analyzing, the reason that the performance of the fin ldmos transistor of the prior art is bad is as follows:
(1) it combines referring to figs. 2 to Fig. 8, first grid structure 131 should be aligned in and 121 phase of the first fleet plough groove isolation structure One end of the first adjacent fin 111.But due to the influence of lithographic accuracy, first grid structure 131 always can be to far from first The direction of fleet plough groove isolation structure 121 deviates, that is to say, that first grid structure 131 and the first fin 111 are close to the first shallow ridges One end of recess isolating structure 121 has certain distance.The step of forming the first source electrode groove 141a and the second source electrode groove 142a Later, the groove structure as the first source electrode groove 141a depth can be also formed in the first fin 111 of the distance segment 143a, later, during the first source electrode groove 141a, the second source electrode groove 142a form germanium silicon layer, groove structure 143a In can also grow germanium silicon layer, thus influence the first fin performance.Later, recessed to the first source electrode groove 141a, the second source electrode During germanium silicon layer in slot 142a and drain recesses 15a carries out ion implanting, in the germanium silicon layer in groove structure 143a It can be injected, be formed " contra-doping layer ", further influence the performance of the first fin, to influence the LDMOS crystal being subsequently formed The stability of pipe.
Similarly, it during forming second grid structure 132, also will receive the influence of lithographic accuracy, and make second Gate structure 132 is deviated to the direction far from the second fleet plough groove isolation structure 122.And then during forming the second source electrode, The performance of second fin 112 is severely impacted, to further influence the stability for the ldmos transistor being subsequently formed.
(2) Fig. 4 to Fig. 8 is referred to, the germanium silicon layer at the first source electrode 141 needs to be higher than the first fin 111, such first source electrode Germanium silicon layer at 141 and at drain electrode 15 can apply optimum stress to the channel under first grid structure 131, maximumlly improve The mobility of carrier.Similarly, the germanium silicon layer at the second source electrode 142 needs to be higher than the second fin 112, the germanium silicon layer at drain electrode 15 It needs to be higher than third fin 113.In this way, the germanium silicon layer at the second source electrode 142 and at drain electrode 15 can be under second grid structure 132 Channel apply optimum stress, maximumlly to improve the mobility of carrier.
However, the growing height of germanium silicon layer is directly proportional to the size of the growing space of germanium silicon layer.For fin LDMOS crystal For pipe, the life of the germanium silicon layer at the first source electrode groove 141a, the second source electrode groove 142a and drain recesses 15a how is accurately controlled Long height, existing technique are difficult to accomplish.Following situations can occur:
1. being illustrated for forming germanium silicon layer in drain recesses 15a.
With reference to Fig. 4, the growing height and first grid structure 131, second grid structure of the germanium silicon layer in drain recesses The distance between 132 is directly proportional.In the prior art, the distance between first grid structure 131 and second grid structure 132 compared with Greatly, therefore, the height that germanium silicon layer is grown in drain recesses not only can be more than the height of the first, second fleet plough groove isolation structure, And it may also exceed the height of first grid structure 131, second grid structure 132.First grid structure 131 and second grid knot The germanium silicon layer formed between structure 132 is sufficiently bulky, is spherical.
2. being illustrated for forming germanium silicon layer in the first source electrode groove 141a.
With reference to Fig. 4, only first grid structure 131 is restricted to the growing height of the germanium silicon layer of the first source electrode groove. Therefore, in the prior art, the growth technique of the germanium silicon layer at the first source electrode is difficult accurately to control the growing height of germanium silicon layer, the Germanium silicon layer volume at one source electrode also can be very big, is spherical, and be higher than first grid structure 131.
3. the case where the case where forming germanium silicon layer in the second source electrode groove in the first source electrode groove with germanium silicon layer is formed Identical, volume also can be very big, is in spherical and is higher than second grid structure 132.
Therefore, the height for the germanium silicon layer that the method for the prior art is formed all can be more than first grid structure 131, second grid Structure 132.It is equal with first grid structure 131, second grid structure 132 being ground to dielectric layer using chemical mechanical grinding When, germanium silicon layer also can be equal with first grid structure 131, second grid structure 132.In this way, the method using wet etching is gone During first grid structure 131, second grid structure 132, germanium silicon layer can also be removed accordingly.In subsequent step, It will be in first grid texture grooves 171a, the first source electrode groove 141a, second grid texture grooves 172a, the second source electrode groove Metallic aluminium can be all filled in 142a, drain recesses 15a.In this way, the first source electrode of the ldmos transistor being subsequently formed, the first grid Pole structure, drain electrode, second drain, can be connected between second grid structure.
(3) it combines and refers to Fig. 5 to Fig. 8, in the prior art, first grid structure 131 and second grid structure 132 are longer. During forming the first aluminum gate structure 171 and the second aluminum gate structure 172, the first aluminium layer is more soft longer, chemical machine When tool grinding operation forms the first aluminium layer, it is easy to appear recess (dishing) phenomenon.Therefore, it is formed using existing method The performance of first aluminum gate structure 171 is bad.In addition, the second aluminium layer is more soft longer, chemical mechanical grinding operates to form second When aluminium layer, it also will appear depressed phenomenon.Therefore, the performance of the second aluminum gate structure 172 formed using existing method is not yet It is good.
Therefore, in order to solve the above technical problem, the present invention provides a kind of forming methods of ldmos transistor, using this The forming method of the ldmos transistor of invention can be improved the performance for the ldmos transistor being subsequently formed.Correspondingly, of the invention A kind of ldmos transistor is also provided.Specific embodiments of the present invention are described in detail with reference to the accompanying drawing.
Embodiment one
The present embodiment is illustrated with the case where two adjacent ldmos transistor common drains.
In conjunction with reference Fig. 9 and Figure 10, semiconductor substrate 20 is provided, the semiconductor substrate 20 has the first fin 211, the Two fins 212 and third fin 213, and the first isolation structure 221 between the first fin 211, the second fin 212, The second isolation structure 222 between the second fin 212 and third fin 213.
In the present embodiment, semiconductor substrate 20 is silicon substrate, the interior transistor for having and being subsequently formed of semiconductor substrate 20 The first opposite well region of type, has the second well region 215 identical with the transistor types being subsequently formed in the first well region.? There is the first isolation structure 221, the second isolation structure 222 in second well region 215.And first isolation structure 221, the second isolation junction Structure 222 is fleet plough groove isolation structure.In other embodiments, the first isolation structure 221, the second isolation structure 222 are this field skill Other isolation structures known to art personnel also belong to protection scope of the present invention.
Specific forming method is as follows:
Patterned first mask layer (not shown), patterned first mask layer are formed in semiconductor substrate 20 The first fin 211 to be formed is defined to the position of third fin 213；It is carved by exposure mask of patterned first mask layer It loses semiconductor substrate 20 and forms equal the first bulge-structure of height to third protrusion structure, then in the first bulge-structure and the The first isolation structure 221 lower than the first, second bulge-structure is formed between two bulge-structures, in the second bulge-structure and third The second isolation structure 222 for being lower than second, third bulge-structure is formed between bulge-structure.Higher than 221 He of the first isolation structure First bulge-structure of the second isolation structure 222 to third protrusion structure respectively corresponds as the first fin 211 to third fin 213。
Wherein, the second fin 212 is only used for forming common drain, and the width of the first fin and third fin is respectively greater than second The width of fin.
First fin 211 other fin (not shown) adjacent thereto, third fin 213 other fins adjacent thereto Also there is third isolation structure 202 between (not shown).Wherein, isolation structure 202 is also fleet plough groove isolation structure.First isolation Structure 221, the second isolation structure 222 and third isolation structure 202 play insulating effect.
In other embodiments, semiconductor substrate is silicon-on-insulator (SOI).Silicon-on-insulator includes bottom silicon layer, is located at Isolation structure layer on bottom silicon layer, the top silicon layer on isolation structure layer.The top silicon layer is used to form at least One fin to third fin also belongs to protection scope of the present invention.
Then, with reference to Figure 11, in third isolation structure 202, the first fin 211, the first isolation structure 221, the second fin 212, dummy gate structure layer 23 is formed on the second isolation structure 222.Dummy gate structure layer 23 is including grid oxide layer and is located at grid oxide layer On polycrystalline silicon gate layer.
Wherein, the forming method of the grid oxide layer in dummy gate structure 23 is furnace oxidation, the formation side of polycrystalline silicon gate layer Method is deposition.
Then, with reference to Figure 12, dummy gate structure layer 23 is etched, forms the pseudo- grid of the first discrete dummy gate structure A1 to the tenth Pole structure A10.
Detailed process is as follows:
Patterned second mask layer (not shown), patterned second exposure mask are formed on dummy gate structure layer 23 Layer defines the positions and dimensions of the first dummy gate structure A1 to the tenth dummy gate structure A10.With patterned second exposure mask Layer is mask etching dummy gate structure layer 23, forms discrete the first dummy gate structure A1 to the tenth dummy gate structure A10.
Wherein, the second dummy gate structure A2 is the first grid structure 231 for the ldmos transistor being subsequently formed (with reference to figure 16), the second dummy gate structure A2 covers the first fin 211 across first fin 211, the first grid structure 231 Top and side wall.
In the present embodiment, second the first isolation structure of dummy gate structure A2 covering part 221.In this way, will avoid etching The lithographic accuracy deviation of the second dummy gate structure A2 is formed, to avoid the second dummy gate structure A2 and the first fin 211 close The problem of one end of first isolation structure 221 is misaligned avoids in the second dummy gate structure A2 and the first fin 211 close to One source electrode material layer of growth regulation between one end of one isolation structure 221, and then avoid influencing the second well region in the first fin 211 215 performance.In addition, the second dummy gate structure A2 covering part first isolation 211, increases drop, is formed afterwards Ldmos transistor can be improved with resistance to pressure.
Further, the length H1 of the first isolation structure of the second dummy gate structure A2 covering part 221 is (with reference to figure 12) for more than or equal to 50nm and less than or equal to 0.1 μm.The length of second the first isolation structure of dummy gate structure A2 covering part 221 If it is too big to spend H1, the size for the first grid structure 231 (with reference to Figure 16) being subsequently formed can be very long, the third resistance of formation The number of barrier 263 (referring to Figure 16) can be reduced.If first grid structure is the first metal gate structure, still cannot have Recess (dishing) phenomenon occurs at the top of the first metal gates of effect prevented in first metal gate structure.Second pseudo- grid If the length H1 of pole the first isolation structure of structure A2 covering part 221 is too small, it is not avoided that the second dummy gate structure of etching still The lithographic accuracy deviation generated when A2 influences the performance of the first fin 211.Wherein, the second dummy gate structure A2 covering part The length H1 of one isolation structure 221 is the first isolation structure 221 and 211 boundary of the first fin to the second dummy gate structure A2 and the The distance between one isolation structure, 221 boundary.
9th dummy gate structure A9 is the second grid structure 232 (with reference to Figure 16) for the ldmos transistor being subsequently formed, the Nine dummy gate structure A9 across the third fin 213, the top of the 9th dummy gate structure A9 covering third fin 213 and Side wall.
In the present embodiment, the 9th the second isolation structure of dummy gate structure A9 covering part 222.In this way, will avoid etching The lithographic accuracy deviation of the 9th dummy gate structure A9 is formed, to avoid the 9th dummy gate structure A9 and third fin 213 close The problem of one end of second isolation structure 222 is misaligned, and then avoid influencing the performance of the second well region 215 in third fin. In addition, the 9th dummy gate structure A9 covering part second isolation 211, increases drop, the ldmos transistor formed afterwards can It is improved with resistance to pressure.
Further, the length H1 of the second isolation structure of the 9th dummy gate structure A9 covering part 222 is (with reference to figure 12) for more than or equal to 50nm and less than or equal to 0.1 μm.The length of 9th the second isolation structure of dummy gate structure A9 covering part 222 If it is too big to spend H1, the size for the second grid structure 232 (with reference to Figure 16) being subsequently formed can be very long, the 5th resistance of formation The number of barrier 265 (referring to Figure 16) can be reduced.If second grid structure is the second metal gate structure, still cannot have Recess (dishing) phenomenon occurs at the top of the second metal gates of effect prevented in the metal gate structure.9th dummy grid knot If the length H1 of the second isolation structure of structure A9 covering part 222 is too small, it is still unavoidable from the second dummy gate structure A9 of etching When generate lithographic accuracy deviation, can third fin 213 inside formed contra-doping layer.Wherein, the second isolation junction of covering part The length H1 of structure 222 is the second isolation structure 222 and 213 boundary of third fin to the 9th dummy gate structure A9 and the second isolation junction The distance between 222 boundary of structure.
In other embodiments, the 9th dummy gate structure A9 not the second isolation structure of covering part 222 is also belonged to of the invention Protection scope.
5th dummy gate structure A5 and the 6th dummy gate structure A6 can be used as the LDMOS being subsequently formed in the next steps First barrier layer 261 (referring to Figure 16) of transistor.5th dummy gate structure A5 and the 6th dummy gate structure A6 is respectively across Two fins 212 cover top and the side wall of the second fin 212.5th dummy gate structure A5 and the 6th dummy gate structure A6 difference Positioned at the two sides of the second fin 212, that is to say, that the 5th dummy gate structure A5 is located at the second fin 212 close to the first fin 211 One end, the 6th dummy gate structure A6 is located at the second fin 212 far from first fin 211 (close to third fin 213) One end.The distance between first barrier layer 261 H2 defines position and the size of drain electrode.That is, the 5th dummy gate structure A5 The distance between 6th dummy gate structure A6 H2 defines position and the size of drain electrode.
In the present embodiment, the reason of the first barrier layer 261 why are arranged, is as follows:
Just because of there is the presence on the first barrier layer 261, in subsequent technique, the growing space of drain material layer can be reduced, The height of the drain material layer of formation can reduce, at least the height for being highly not less than the second fin 212, be not higher than each dummy grid The height of structure.In this way, being subsequently formed the interlayer dielectric layer equal with the first dummy gate structure A1 to the tenth dummy gate structure A10 After 25, interlayer dielectric layer 25 can cover drain material layer.During removing the second dummy gate structure, the 9th dummy gate structure, The interlayer dielectric layer 25 being covered on drain material layer protects the drain material layer not removed therewith.In this way, forming first It, can be to avoid leaking when the first metal gate layers of metal gate structure, the second metal gate layers of the second metal gate structure The metal gate layers are formed in the groove of pole, to avoid the drain electrode being subsequently formed and the first metal gate structure, the second gold medal Belong to the connected situation of gate structure, to improve the performance for the LDMOS being subsequently formed.
Further, the distance between first barrier layer 261 in the present embodiment H2 be more than or equal to 0.01 micron and Less than or equal to 0.2 micron.If the distance between the first barrier layer 261 H2 is too big, the prior art still not can solve The problem of (2).If the distance between the first barrier layer 261 H2 is too small, it is not easy to it is formed and is higher than the second fin 212 drain material layer.
In the present embodiment, the 5th the first isolation structure of dummy gate structure A5 covering part 221.6th dummy gate structure A6 covers The second isolation structure of cover 222.In this way, the 5th dummy gate structure A5 and the second fin 212 are close to one end of the first fin 211 Would not be because of photoetching deviation appearance distance, the 6th dummy gate structure A6 and the second fin 212 are close to one end of third fin 211 Contra-doping layer will not will not be formed at the distance to influence during subsequent source and drain injection because of photoetching deviation appearance distance The performance of second well region 215 in second fin 212.
Further, the length H3 of the first isolation structure of the 5th dummy gate structure A5 covering part 221 is (with reference to figure 12) for more than or equal to 50nm and less than or equal to 0.1 μm.The length of 5th the first isolation structure of dummy gate structure A5 covering part 221 If spent, H3 is too big, and the number on the third barrier layer 263 (with reference to Figure 16) formed can be reduced.If first grid structure is the When one metal gate structure, it still cannot effectively prevent from being recessed at the top of the first metal gates in the metal gate structure (dishing) phenomenon.If the length H3 of the 5th the first isolation structure of dummy gate structure A5 covering part 221 is too small, still cannot Avoid lithographic accuracy deviation, the 5th dummy gate structure A5 and the second fin 212 between one end of the first fin 211 still Distance is had, still will form contra-doping layer in the second fin 212 at the distance and position.Wherein, the first isolation junction of covering part The length H3 of structure 221 is the first isolation structure 221 and 212 boundary of the second fin to the 5th dummy gate structure A5 and the first isolation junction The distance between 221 boundary of structure.
The length H3 (refer to Figure 12) of the second isolation structure of the 6th dummy gate structure A6 covering part 222 be greater than etc. In 50nm and it is less than or equal to 0.1 μm.If the length H3 of the 6th the second isolation structure of dummy gate structure A6 covering part 222 is too Greatly, then the number on the 5th barrier layer 265 (with reference to Figure 16) formed can be reduced.If second grid structure is the second metal gates When structure, it still cannot effectively prevent from being recessed at the top of the second metal gates in second metal gate structure (dishing) phenomenon.If the length H3 of the 6th the second isolation structure of dummy gate structure A6 covering part 222 is too small, it is not easy to Lithographic accuracy deviation is avoided, the 6th dummy gate structure A6 and the second fin 212 still can between one end of third fin 213 There is distance, still will form contra-doping layer in the second fin 212 at the distance and position.Wherein, the second isolation junction of covering part The length H3 of structure 222 is the second isolation structure 222 and 212 boundary of the second fin to the 6th dummy gate structure A6 and the second isolation junction The distance between 222 boundary of structure.
In other embodiments, the 5th dummy gate structure A5 does not cover the first isolation structure 221 or the 6th puppet Gate structure A6 does not cover the second isolation structure 222, also belongs to protection scope of the present invention.
In other embodiments, the 5th dummy gate structure A5 does not cover the first isolation structure 221, also, the described 6th Dummy gate structure A6 does not cover the second isolation structure 222, also belongs to protection scope of the present invention.
First dummy gate structure A1 can be used as the second barrier layer of the ldmos transistor being subsequently formed in the next steps 262 (refer to Figure 16), the first dummy gate structure A1 is in the second dummy gate structure A2 far from first isolation structure 221 sides.First dummy gate structure A1 covers top and the side wall of the first fin 211 across the first fin 211, with second Dummy gate structure A2 is parallel.Moreover, the distance between the first dummy gate structure A1 and the second dummy gate structure A2 H4 can be defined The position of first source electrode and size.
In the present embodiment, the reason of the second barrier layer 262 why are arranged, is as follows:
Just because of there is the presence on the second barrier layer 262, the growth of the first source electrode material layer in the subsequent process can be made The height of reduced space, the first source electrode material layer of formation can reduce, at least the height for being highly not less than the first fin 211, Not higher than the height of each dummy gate structure.It is subsequently formed equal to the tenth dummy gate structure A10 with the first dummy gate structure A1 After interlayer dielectric layer 25, interlayer dielectric layer 25 can cover the first source electrode material layer.Remove the second dummy gate structure, the 9th dummy grid During structure, the interlayer dielectric layer 25 being covered in the first source electrode material protects the first source electrode material layer will not be by therewith Removal.In this way, forming the second metal gates of the first metal gate layers of the first metal gate structure, the second metal gate structure When layer, the metal gate layers can be formed to avoid in the first source electrode groove.To avoid the first source electrode being subsequently formed Situation about being connected with the first metal gate structure, the second metal gate structure, to improve the performance for the LDMOS being subsequently formed.
Further, the first dummy gate structure A1 in the present embodiment and the distance between the second dummy gate structure A2 H4 is More than or equal to 0.01 micron and it is less than or equal to 0.2 micron.Between first dummy gate structure A1 and the second dummy gate structure A2 away from If too big from H4, problems of the prior art (2) will be generated.First dummy gate structure A1 and the second dummy gate structure If the distance between A2 H4 is too small, it is not easy to form the first source electrode material layer for being higher than the first fin 211.
In the present embodiment, the first dummy gate structure A1 (the second barrier layer 262) part covering and 211 phase of the first fin Adjacent third isolation structure 202.In this way, the lithographic accuracy deviation of the first dummy gate structure A1 of etching formation will be avoided, thus It avoids the problem that the first dummy gate structure A1 is misaligned with the first fin 211 close to one end of third isolation structure 202, and then keeps away Exempt to form contra-doping layer in the first fin 211 during forming the first source electrode material, influences first in the first fin 211 The performance of well region.
Further, the part the first dummy gate structure A1 covers the third isolation structure adjacent with the first fin 211 202 length H5 (referring to Figure 12) is more than or equal to 50nm and to be less than or equal to 0.1 μm.First dummy gate structure A1 covering part If the length H5 of three isolation structures is too big, the size for the ldmos transistor being subsequently formed can be made bigger than normal.It is multiple when needing When above-mentioned size transistor bigger than normal, the area occupied on chip is more, can reduce the utilization rate of chip.First dummy gate structure If the length H5 of A1 covering part third isolation structure is too small, generation when being still unavoidable from the first dummy gate structure A1 of etching Lithographic accuracy deviation can form contra-doping layer in the inside of the first fin 211.Wherein, the first dummy gate structure A1 covering part The length H5 of third isolation structure 202 be third isolation structure 202 and 211 boundary of the first fin to the first dummy gate structure A1 and The distance between 202 boundary of third isolation structure.
In other embodiments, the first dummy gate structure A1 does not cover the third isolation structure adjacent with the first fin 211 202, also belong to protection scope of the present invention.
In other embodiments, two or more first dummy gate structure A1 can also be formed, in this way, the first dummy gate structure The distance between A1 defines position and the size of the first source electrode, also belongs to protection scope of the present invention.
Third dummy gate structure A3, the 4th dummy gate structure A4 can be used as the LDMOS being subsequently formed in the next steps The third barrier layer 263 (referring to Figure 16) of transistor, is formed on the first isolation structure 221.Why third dummy grid is formed Structure A3, the 4th dummy gate structure A4, the reason is as follows that:
The material of first metal gate layers is aluminium, and the material is soft.The mistake of above-mentioned the first metal gate layers of chemical mechanical grinding Cheng Zhong will appear recess (dishing) when grinding the first so long metal gate layers without the support on third barrier layer 263 Phenomenon.
Further, in the present embodiment, when third barrier layer 263 is two (respectively thirds on the first isolation structure 221 Dummy gate structure A3, the 4th dummy gate structure A4) when, it can maximumlly alleviate the first gold medal in the third barrier layer of separate structure Belong to grid layer top depression phenomenon.
In other embodiments, in the spatial dimension of limited first isolation structure, in the third barrier layer of separate structure 263 numbers are unrestricted, also belong to protection scope of the present invention.
In other embodiments, third barrier layer is formed not on the first isolation structure, also belongs to protection scope of the present invention.
Tenth dummy gate structure A10 can be used as the 4th blocking of the ldmos transistor being subsequently formed in the next steps Layer 264 (refers to Figure 16), and the tenth dummy gate structure A10 is in the 9th dummy gate structure A9 far from second isolation structure 222 sides.Tenth dummy gate structure A10 covers top and the side wall of third fin 213 across third fin 213, with Nine dummy gate structure A9 are parallel.Moreover, the tenth dummy gate structure A10 and the distance between the 9th dummy gate structure A9 H4 can determine The position of adopted second source electrode and size.
In the present embodiment, the reason of why the 4th barrier layer 264 being arranged, is as follows:
Just because of there is the presence on the 4th barrier layer 264, in subsequent technique, the height of the second source electrode material layer of formation can drop It is low, at least height for being highly not less than third fin 213, not higher than the height of each dummy gate structure.It is subsequently formed and first After dummy gate structure A1 to the tenth dummy gate structure A10 equal interlayer dielectric layer 25, interlayer dielectric layer 25 can cover the second source Pole material layer.During removing the second dummy gate structure, the 9th dummy gate structure, the interlayer that is covered in the second source electrode material Dielectric layer 25 protects the second source electrode material layer not removed therewith.In this way, forming the first gold medal of the first metal gate structure When belonging to the second metal gate layers of grid layer, the second metal gate structure, the gold can be formed to avoid in the second source electrode groove Belong to grid layer.To avoid the second source electrode being subsequently formed and the first metal gate structure, the second metal gate structure phase Even the case where, to improve the performance for the LDMOS being subsequently formed.
Further, the 4th barrier layer 264 in the present embodiment is with the distance between the 9th dummy gate structure A9 H4 More than or equal to 0.01 micron and it is less than or equal to 0.2 micron.The distance between 4th barrier layer 264 and the 9th dummy gate structure A9 H4 If too big, problems of the prior art (2) will be generated.Between 4th barrier layer 264 and the 9th dummy gate structure A9 If distance H4 it is too small, it is not easy to formed be higher than third fin 213 the second source electrode material layer.
In the present embodiment, the tenth dummy gate structure A10 (the 4th barrier layer 264) part covering and third fin 213 Adjacent third isolation structure 202.In this way, the lithographic accuracy deviation of the tenth dummy gate structure A10 of etching formation will be avoided, from And avoid the problem that the tenth dummy gate structure A10 is misaligned with third fin 213 close to one end of third isolation structure 202, into And avoid forming contra-doping layer in third fin 213 during forming the second source electrode material, it influences in third fin 213 The performance of first well region.
Further, the tenth dummy gate structure A10 covering part third isolation structure adjacent with third fin 213 202 length H5 (referring to Figure 16) is more than or equal to 50nm and to be less than or equal to 0.1 μm.Tenth dummy gate structure A10 covering part If the length H5 of third isolation structure is too big, the size for the ldmos transistor being subsequently formed can be made bigger than normal.It is more when needing When a above-mentioned size transistor bigger than normal, the area occupied on chip is more, can reduce the utilization rate of chip.Tenth dummy grid knot If the length H5 of structure A10 covering part third isolation structure 202 is too small, it is still unavoidable from the tenth dummy gate structure of etching Lithographic accuracy deviation is generated when A10, can form contra-doping layer in the inside of third fin 213.Wherein, the tenth dummy gate structure The length H5 of the A10 covering part third isolation structure 202 adjacent with third fin 213 is third isolation structure 202 and third 213 boundary of fin is to the distance between the tenth dummy gate structure A10 and 202 boundary of third isolation structure.
In other embodiments, the tenth dummy gate structure A10 does not cover the third isolation structure adjacent with third fin 213 202, also belong to protection scope of the present invention.
In other embodiments, two or more tenth dummy gate structure A10 can also be formed, in this way, the tenth dummy grid knot The distance between structure A10 defines position and the size of the second source electrode, also belongs to protection scope of the present invention.
7th dummy gate structure A7, the 8th dummy gate structure A8 can be used as in the next steps to be subsequently formed 5th barrier layer 265 (referring to Figure 16) of ldmos transistor, is formed on the second isolation structure 222.Why seventh puppet is formed Gate structure A7, the 8th dummy gate structure A8, the reason is as follows that:
The material of second metal gate layers is aluminium, and the material is soft.The mistake of above-mentioned the second metal gate layers of chemical mechanical grinding Cheng Zhong will appear recess (dishing) when grinding the second so long metal gate layers without the support on the 5th barrier layer 265 Phenomenon.
Further, in the present embodiment, when the 5th barrier layer 265 is two the (the respectively the 7th on the second isolation structure 222 Dummy gate structure A7, the 8th dummy gate structure A8) when, can maximumlly alleviate in the 5th barrier layer of separate structure second The depressed phenomenon occurred at the top of metal gate layers.
In other embodiments, in the spatial dimension of limited second isolation structure, in the 5th barrier layer of separate structure 265 numbers are unrestricted, also belong to protection scope of the present invention.
In other embodiments, the 5th barrier layer is formed not on the second isolation structure, also belongs to protection scope of the present invention.
Therefore, effective grid that the second dummy gate structure A2 and the 9th dummy gate structure A9 are the LDMOS being subsequently formed.Its The non-effective grid that remaining dummy gate structure is the LDMOS being subsequently formed.
It should be noted that the length of the first dummy gate structure A1 to the tenth dummy gate structure A10 is distinguished in the present embodiment For more than or equal to 0.01 μm and less than or equal to 0.1 μm, the gross density of each dummy gate structure is more than or equal to 5% and to be less than or equal to 30%.If the length of the first dummy gate structure A1 to the tenth dummy gate structure A10 is too long, it is subsequently formed the first, second metal When gate structure or each barrier layer, it is easy to produce recess.The length of first dummy gate structure A1 to the tenth dummy gate structure A10 If degree is too short, lithographic accuracy limitation is received, each pseudo- grid structure can not be formed.
Then, 2 are continued to refer to figure 1, in each pseudo- grid structure week of the first dummy gate structure A1 to the tenth dummy gate structure A10 It encloses and is respectively formed side wall.
In the present embodiment, the reason of formation side wall, is as follows around each dummy gate structure:
(1) side wall around the side wall and the 6th dummy gate structure A6 around the 5th dummy gate structure A5 defines subsequent shape At drain electrode position and size.
Side wall definition between side wall and the second dummy gate structure A2 around (2) first dummy gate structure A1 is subsequently formed The first source electrode position and size.
The side wall between side wall and the tenth dummy gate structure A10 around (3) the 9th dummy gate structure A9 defines subsequent shape At the second source electrode position and size.
(4) around each gate structure if without side wall, subsequent source electrode material layer and drain material layer in formation In the process, source electrode material layer and drain material layer can also be grown on corresponding polysilicon gate in each dummy gate structure.Subsequent shape At source electrode material layer and the volume of drain material layer can be bigger, the height meeting of the source electrode material layer and drain material layer of formation It is relatively high.But the volume of the source electrode material layer of formation and drain material layer and height are smaller than the prior art.
In other embodiments, if not forming side wall around each gate structure, the scope of protection of the invention is also belonged to.
Then, right using the side wall between the first dummy gate structure A1 and the second dummy gate structure A2 as exposure mask with reference to Figure 13 First fin performs etching, and forms the first source electrode groove；Between 5th dummy gate structure A5 and the 6th dummy gate structure A6 Side wall is exposure mask, is performed etching to the second fin, and drain recesses are formed；With the 9th dummy gate structure A9 and the tenth dummy gate structure Side wall between A10 is exposure mask, is performed etching to third fin, and the second source electrode groove is formed.
In the present embodiment, the first source electrode groove, the second source electrode groove, drain recesses are formed simultaneously.Specifically forming method is The known technology of those skilled in the art, details are not described herein.
Then, 3 are continued to refer to figure 1, forms the first source electrode material layer in the first source electrode groove, in the second source electrode groove The second source electrode material layer is formed, forms drain material layer in drain recesses.
In the present embodiment, when the ldmos transistor that is subsequently formed is PMOS transistor, then the first source electrode material layer, second Source electrode material layer and drain material layer are germanium silicon layer.
The method for forming germanium silicon layer is selective epitaxial growth.
In the present embodiment, the first source electrode material layer, the second source electrode material layer and drain material layer are all higher than corresponding fin, And it is lower than the height of each dummy gate structure.
In ldmos transistor in the prior art, the first source electrode material layer, the second source electrode material layer and drain material are formed The space of layer is larger, however, the first source electrode material layer, the second source electrode material layer and drain material layer only need in the transistor To exceed a little height of fin, optimum stress otherwise can not be applied to the channel under corresponding grid.But control first It is very in practical growth technique that source electrode material layer, the second source electrode material layer and drain material layer, which only exceed a little height of fin, It is rambunctious.
Therefore, the present embodiment leads to according to the principle of " growing height of germanium silicon layer is directly proportional to the growing space of germanium silicon layer " The growing space of control germanium silicon layer is crossed, to control the growing height of germanium silicon layer.Compared with the existing technology, by reducing germanium silicon layer Growing space, to reduce the growing height of germanium silicon layer.
Specifically, passing through the distance between the 5th dummy gate structure A5 and the 6th dummy gate structure A6 H2 in the present embodiment The growing space that (referring to Figure 12) defines drain electrode, makes it be less than the growing space to drain in the prior art.
By the distance between the first dummy gate structure A1 and the second dummy gate structure A2 H4 (with reference to figure in the present embodiment 12) growing space for defining the first source electrode material layer makes it be less than the growing space of the first source electrode in the prior art.
By the distance between the 9th dummy gate structure A9 and the tenth dummy gate structure A10 H4 (with reference to figure in the present embodiment 12) growing space for defining the second source electrode material layer makes it be less than the growing space of the second source electrode in the prior art.
After forming above-mentioned germanium silicon layer, silicon cap layer (not shown) is formed on above-mentioned germanium silicon layer respectively.Form the work of silicon cap layer With are as follows: in subsequent step, need to form metal silicide layer on germanium silicon layer.Germanium silicon layer is germanic too many, is formed on germanium silicon layer The performance of metal silicide is bad.And the better performances of metal silicide layer are formed on silicon.So needing be subsequently formed Silicon cap layer is formed between metal silicide layer and above-mentioned germanium silicon layer.
Then, ion implanting is carried out to the first source electrode material layer, the second source electrode material layer and drain material layer, be correspondingly formed First source electrode 241, the second source electrode 243 and drain electrode 242.Wherein drain electrode is the common drain of two ldmos transistors.
In other embodiments, when the ldmos transistor being subsequently formed is NMOS.Then the first source electrode material layer, the second source electrode Material layer and drain material layer are silicon carbide layer, because belonging to the scope of protection of the present invention.
Then, with reference to Figure 14, in semiconductor substrate 20, the first dummy gate structure A1 to the tenth dummy gate structure A10, first Interlayer dielectric layer 25 is formed in source electrode 241, the second source electrode 243 and drain electrode 242.
The material of interlayer dielectric layer 25 is silica, silicon carbide or silicon oxynitride.Interlayer dielectric layer 25 or low k material The dielectric constant of material or ultralow-k material film, the low-k materials is less than or equal to 3, and the dielectric constant of the ultralow-k material film is less than or equal to 2.7.The forming method of interlayer dielectric layer 25 is deposition.It is specifically as follows high-density plasma (High Density Plasma, HDP) chemical vapor deposition either high depth ratio fill out ditch technique (High Aspect Ratio Process, HARP) Or flowing chemical vapor deposition (Flowable Chemical Vapor Deposition, FCVD).Using above-mentioned three kinds of sides Method filling capacity is stronger, and 25 consistency of interlayer dielectric layer of formation is relatively high.Certainly, interlayer dielectric layer 25 is also possible to this field Other depositing operations known to technical staff, also belong to protection scope of the present invention.
After forming interlayer dielectric layer 25, the first dummy gate structure A1 to the tenth will be above using the method for chemical mechanical grinding The interlayer dielectric layer 25 of dummy gate structure A10 removes, in this way, remaining interlayer dielectric layer 25 can be with the first dummy gate structure A1 extremely Tenth dummy gate structure A10 is equal.
Then, in conjunction with reference Figure 15, the second dummy gate structure A2, the 9th dummy grid knot are removed using the method for wet etching Structure A9 is respectively formed first grid texture grooves 231a and second grid texture grooves 232a in interlayer dielectric layer 25, described The first fin 211 and third fin are exposed in first grid texture grooves 231a and the bottom second grid texture grooves 232a respectively 213。
In the present embodiment, during removing the second dummy gate structure A2, the 9th dummy gate structure A9, remaining puppet grid Pole structure can also be removed by the way.That is, the first dummy gate structure A1, third dummy gate structure A3, the 4th dummy grid knot Structure A4 can be also removed to the 8th dummy gate structure A8, the tenth dummy gate structure A10, be respectively formed phase in interlayer dielectric layer 25 The gate structure groove answered.
Then, with reference to Figure 16, in the bottom and side of first grid texture grooves 231a and second grid texture grooves 232a Wall is respectively formed the first high-k gate dielectric layer and the second high-k gate dielectric layer.First high-k gate dielectric layer and the second high k in the present embodiment Gate dielectric layer material is identical.At this moment, the bottom and side wall of remaining each gate structure groove is respectively formed with the first high-k gate dielectric Layer and/or the second high-k gate dielectric layer material.Later, it is formed on the first high-k gate dielectric layer and the second high-k gate dielectric layer respectively The first metal layer and second metal layer, the first metal layer and second metal layer are higher than each dummy gate structure and interlayer dielectric layer 25.In the present embodiment, the first metal layer and second metal layer are all identical.At this moment, it can also be filled out in remaining each gate structure groove Fill the first metal layer or second metal layer.
Later, it is gone using the metal layer that the method for chemical mechanical grinding will be above each dummy gate structure and interlayer dielectric layer 25 It removes, is respectively formed the first metal gate layers and the second metal gate layers.First metal gate layers and the first high-k gate dielectric layer are formed First grid structure 231.Second metal gate layers and the second high-k gate dielectric layer form second grid structure 232.Remaining Each dummy gate structure also becomes metal gate structure, that is, above-mentioned each barrier layer, specific as follows:
5th dummy gate structure A5 and the 6th dummy gate structure A6 becomes the first barrier layer 261, the first dummy gate structure A1 As the second barrier layer 262, third dummy gate structure A3 and the 4th dummy gate structure A4 become third barrier layer 263, and the tenth is pseudo- Gate structure A10 becomes the 4th barrier layer 264, and the 7th dummy gate structure A7 and the 8th dummy gate structure A8 become the 5th barrier layer 265。
In other embodiments, first grid structure 231 and second grid structure 232 can also be polysilicon gate construction, Each barrier layer is polysilicon gate construction, also belongs to protection scope of the present invention.If first grid structure 231 and second gate Pole structure 232 is polysilicon gate construction, and each barrier layer is polysilicon gate construction, then above-mentioned formation first grid structure is recessed The step of slot 231a, second grid texture grooves 232a, each gate structure groove and in first grid texture grooves 231a, It is respectively formed the first and second high-k gate dielectric layers in two gate structure groove 232a and each gate structure groove, corresponding is located at the One and the forming step of second the first and second metal gate layers on high-k gate dielectric layer can be omitted.
Embodiment two
With reference to Figure 16, the present invention also provides a kind of LDMOS transistor structure, two adjacent ldmos transistors share one A drain electrode.It specifically includes:
Semiconductor substrate 20, the semiconductor substrate 20 have the first fin 211, the second fin 212 and third fin 213.The semiconductor substrate 20 also has first isolation structure 221, position between the first fin 211 and the second fin 212 The second isolation structure 222 between the second fin 212 and third fin 213；
Across the first grid structure 231 of the first fin 211, the first grid structure 231 covers the first fin 211 Top and side wall；
Across the second grid structure 232 of third fin 213, the second grid structure 232 covers third fin 213 Top and side wall；
First in the first fin 211 far from 221 side of the first isolation structure of first grid structure 231 Source electrode 241；
The is formed in third fin 213 of the second grid structure 232 far from 222 side of the second isolation structure Two source electrodes 243；
Drain electrode 242 in the second fin 212；
Further include:
231 first isolation structure of covering part 221 of first grid structure.
In the present embodiment, the length of the first isolation structure of the first grid structure covering part be more than or equal to 50nm and Less than or equal to 0.1 μm.
In the present embodiment, the ldmos transistor further include: across the first barrier layer 261 of second fin 212, First barrier layer 261 is located at one end and separate described first close to the first fin 211 of second fin 212 One end of fin 211, for defining position and the size of drain electrode 242；The second fin to drain between the first barrier layer 261 In 212.
In the present embodiment, 261 part of the first barrier layer close to 221 one end of the first isolation structure covers the first isolation structure 221.The length H1 of first barrier layer, 261 first isolation structure of covering part 221 is more than or equal to 50nm and to be less than or equal to 0.1μm。
In the present embodiment, 261 part of the first barrier layer close to 222 one end of the second isolation structure covers the first isolation structure 222.The length H1 of first barrier layer, 261 first isolation structure of covering part 222 is more than or equal to 50nm and to be less than or equal to 0.1μm。
In the present embodiment, the side far from first isolation structure 221 of the first grid structure 231 has second Barrier layer 262, second barrier layer 262 is across the first grid structure 231, and second barrier layer 262 is for defining The first source electrode 241 position and size.
In the present embodiment, the side far from second isolation structure 222 of the second grid structure 232 has the 4th Barrier layer 264, the 4th barrier layer 264 is across the second grid structure 232, and the 4th barrier layer 264 is for defining The second source electrode 243 position and size.
In the present embodiment, when the first grid structure 231 is the first metal gate structure, first isolation structure There is third barrier layer 263 on 221.
When the material of the first metal gate layers is aluminium, the material is soft.Above-mentioned the first metal gate layers of chemical mechanical grinding In the process, without the support on third barrier layer 263, it will appear recess when grinding the first so long metal gate layers (dishing) phenomenon.
Further, in the present embodiment, when third barrier layer 263 is two (in conjunction with reference to figure on the first isolation structure 221 12 and Figure 16, respectively third dummy gate structure A3 and the 4th dummy gate structure A4) when, it can in the third barrier layer of separate structure Maximumlly to alleviate the depressed phenomenon occurred at the top of the first metal gate layers.
In other embodiments, does not have third barrier layer 263 on the first isolation structure 221 and also belong to what the present invention protected Range.
In the present embodiment, when the second grid structure 232 is the second metal gate structure, second isolation structure There is the 5th barrier layer 265 on 222.
When the material of the second metal gate layers is aluminium, the material is soft.Above-mentioned the second metal gate layers of chemical mechanical grinding In the process, without the support on the 5th barrier layer 265, it will appear recess when grinding the second so long metal gate layers (dishing) phenomenon.
Further, in the present embodiment, when the 5th barrier layer 265 is two (in conjunction with reference to figure on the second isolation structure 222 12 and Figure 16, respectively the 7th dummy gate structure A7, the 8th dummy gate structure A8) when, it can in the 5th barrier layer of separate structure Maximumlly to alleviate the depressed phenomenon occurred at the top of the second metal gate layers.
In other embodiments, on second isolation structure 222 do not have the 5th barrier layer 265 also belong to it is of the invention Protection scope.
In the present embodiment, first barrier layer 261, the second barrier layer 262, third barrier layer 263, the 4th barrier layer 264 and the 5th barrier layer 265 be metal gate structure.
In the present embodiment, 232 second isolation structure of covering part 222 of second grid structure.The second grid knot The length of 232 the second isolation structure of covering part of structure is more than or equal to 50nm and to be less than or equal to 0.1 μm.
In the present embodiment, 262 part of the second barrier layer covers the third isolation structure adjacent with the first fin 211 202.The length H5 of second barrier layer, the 262 covering part third isolation structure 202 is more than or equal to 50nm and to be less than or equal to 0.1μm。
In the present embodiment, 264 part of the 4th barrier layer covers the third isolation structure adjacent with third fin 213 202.The length H5 of 4th barrier layer, the 264 covering part third isolation structure 202 is more than or equal to 50nm and to be less than or equal to 0.1μm。
Specifically please refer to embodiment one.
Embodiment three
With reference to Figure 17, the present embodiment provides a kind of forming method of ldmos transistor, the areas of the present embodiment and embodiment one Not are as follows: there are two source electrodes, respectively the first source electrode and the second source electrode for the tool of embodiment one.First source electrode and the second source electrode share one Drain electrode.Only one source electrode 341 of the ldmos transistor of the present embodiment, drain electrode 342 is not common drain.That is, the present embodiment In, without third fin and the second fleet plough groove isolation structure.It specifically includes:
Semiconductor substrate 30 is provided, the semiconductor substrate has the first fin 311, the second fin 312 and positioned at first The first isolation structure 321 between fin 311, the second fin 312；
It is developed across the gate structure 331 of first fin 311, the gate structure 331 covers the first fin 311 Top and side wall, the first isolation structure of the first grid structure covering part；
Source electrode is formed in the first fin 311 far from 321 side of the first isolation structure of the gate structure 331 341；
Drain electrode 342 is formed in the second fin 312.
In the present embodiment, the length H1 of the first isolation structure of the first grid structure covering part is more than or equal to 50nm And it is less than or equal to 0.1 μm.
It in the present embodiment, is formed before drain electrode 342 in the second fin 312, is developed across the of second fin 312 One barrier layer 361, first barrier layer 361 be located at second fin 312 close to one end of the first fin 311 and separate One end of first fin 311, for defining position and the size of drain electrode 342.
It in the present embodiment, is formed before the source electrode 341, in the gate structure 331 far from first isolation junction The side of structure 321 forms the second barrier layer 362, and second barrier layer 362 is across first fin 311, second resistance Barrier 362 is used to define position and the size of source electrode 341.
In the present embodiment, the first grid structure is the first metal gate structure, is had on first isolation structure Third barrier layer 363 prevents the first metal gate layers in the first metal gate structure from generating recess.
In the present embodiment, first barrier layer 361, the second barrier layer 362 and third barrier layer 363 are metal gates knot Structure.
In the present embodiment, 361 part of the first barrier layer close to 321 one end of the first isolation structure covers the first isolation structure 321.The length H3 of first barrier layer, 361 first isolation structure of covering part 321 is more than or equal to 50nm and to be less than or equal to 0.1μm。
In the present embodiment, the covering of 361 part of the first barrier layer and the second fin far from 322 one end of the first isolation structure 312 the second adjacent isolation structures 302.First barrier layer, 361 covering part, second isolation junction adjacent with the second fin 312 302 length H3 of structure is more than or equal to 50nm and to be less than or equal to 0.1 μm.
In the present embodiment, 262 part of the second barrier layer covers second isolation structure adjacent with the first fin 211 302.Second barrier layer, 262 part cover the length H5 of second isolation structure 302 adjacent with the first fin 211 for greater than Equal to 50nm and it is less than or equal to 0.1 μm.
Specifically please refer to embodiment one.
Example IV
The present invention provides a kind of ldmos transistor, comprising:
Semiconductor substrate 30, the semiconductor substrate 30 have the first fin 311, the second fin 312 and are located at the first fin The first isolation structure 321 between portion 311, the second fin 312；
Across the gate structure 331 of first fin 311, the gate structure 331 covers the top of the first fin 311 And side wall；
Source electrode 341 in the first fin 311 far from 321 side of the first isolation structure of gate structure 331；
Drain 342 in the second fin 312.
Further include:
331 first isolation structure of covering part 321 of first grid structure.
In the present embodiment, the length H1 of the first isolation structure of the first grid structure covering part is more than or equal to 50nm And it is less than or equal to 0.1 μm.
In the present embodiment, the ldmos transistor also has across the first barrier layer 361 of second fin 312, institute State the first barrier layer 361 be located at second fin 312 close to one end of the first fin 311 and far from first fin The one end in portion 311, for defining position and the size of drain electrode 342.
With first can be referred to 3rd embodiment.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute Subject to the range of restriction.

Claims (17)

1. a kind of forming method of ldmos transistor characterized by comprising
Semiconductor substrate is provided, the semiconductor substrate has the first fin, the second fin and is located at the first fin, the second fin Between the first isolation structure；
It is developed across the first grid structure of first fin, the first grid structure covers the top of first fin And side wall, the first isolation structure described in the first grid structure covering part；
The first source electrode is formed in first fin of the first grid structure far from first isolation structure side；
Drain electrode is formed in second fin；
The length of first isolation structure described in the first grid structure covering part is more than or equal to 50nm and to be less than or equal to 0.1 μm。
2. forming method as described in claim 1, which is characterized in that formed before drain electrode, formed in second fin Across the first barrier layer of second fin, first barrier layer is located at second fin close to one end of the first fin With far from first fin one end, for defining position and the size of drain electrode.
3. forming method as claimed in claim 2, which is characterized in that formed before first source electrode, in the first grid Pole structure forms the second barrier layer far from the side of first isolation structure, and second barrier layer is across first fin Portion, second barrier layer are used to define position and the size of the first source electrode.
4. forming method as claimed in claim 3, which is characterized in that first barrier layer and the second barrier layer are polysilicon Gate structure.
5. forming method as described in claim 1, which is characterized in that the first grid structure is the first metal gate structure When, before forming the first source electrode and drain electrode, third barrier layer is formed on first isolation structure, prevents first metal gate Pole structural top recess.
6. forming method as described in claim 1, which is characterized in that the semiconductor substrate also has third fin and is located at The second isolation structure between second fin, third fin；
It is developed across the second grid structure of the third fin, the top and side of the second grid structure covering third fin Wall；
The second source electrode is formed in the third fin far from second isolation structure side of the second grid structure.
7. forming method as claimed in claim 6, which is characterized in that formed before second source electrode, in the second gate The side far from second isolation structure of pole structure forms the 4th barrier layer, and the 4th barrier layer is across the third fin Portion, the 4th barrier layer are used to define position and the size of the second source electrode.
8. forming method as claimed in claim 7, which is characterized in that the 4th barrier layer is polysilicon gate construction.
9. forming method as claimed in claim 6, which is characterized in that the second isolation junction of the second grid structure covering part Structure.
10. forming method as claimed in claim 9, which is characterized in that the second grid structure covering part second is isolated The length of structure is more than or equal to 50nm and to be less than or equal to 0.1 μm.
11. forming method as claimed in claim 6, which is characterized in that formed before drain electrode, formed in second fin Across the first barrier layer of second fin, first barrier layer is located at second fin close to one end of the first fin With far from first fin one end, for defining position and the size of drain electrode；The first of described close first fin one end The first isolation structure of barrier layer covering part, the first barrier layer portions covering described the of described separate first fin one end Two isolation structures.
12. forming method as claimed in claim 6, which is characterized in that the second grid structure is the second metal gates knot When structure, before forming the second source electrode, the 5th barrier layer is formed on second isolation structure, prevents the second metal gates knot Structure top depression.
13. a kind of ldmos transistor, comprising:
Semiconductor substrate, the semiconductor substrate have the first fin, the second fin and between the first fin, the second fins The first isolation structure；
Across the first grid structure of first fin, the first grid structure covers top and the side wall of the first fin；
The first source electrode in the first fin far from first isolation structure side of first grid structure；
Drain electrode in the second fin；
It is characterized by further comprising:
The first isolation structure of the first grid structure covering part；
The length of the first isolation structure of the first grid structure covering part is more than or equal to 50nm and to be less than or equal to 0.1 μm.
14. ldmos transistor as claimed in claim 13, which is characterized in that further include:
Across the first barrier layer of second fin, first barrier layer is located at close first fin of second fin One end and far from first fin one end, for defining position and the size of drain electrode.
15. ldmos transistor as claimed in claim 13, which is characterized in that the first grid structure far from described the The side of one isolation structure has the second barrier layer, and second barrier layer is across first fin, second barrier layer The position of the first source electrode for definition and size.
16. ldmos transistor as claimed in claim 13, which is characterized in that the semiconductor substrate also has third fin And the second isolation structure between second fin, third fin；
Across the second grid structure of the third fin, the top of the second grid structure covering third fin and side wall；
The second source electrode in the third fin far from second isolation structure side of the second grid structure；
Stop positioned at the 4th barrier layer of the side far from second isolation structure of the second grid structure, the described 4th Layer is across the third fin, position and size of the 4th barrier layer for the second source electrode of definition.
17. ldmos transistor as claimed in claim 16, which is characterized in that the first grid structure is the first metal gate When the structure of pole, there is third barrier layer on first isolation structure；
When the second grid structure is the second metal gate structure, there is the 5th barrier layer on second isolation structure.
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CN105826189A (en) * 2015-01-06 2016-08-03 中芯国际集成电路制造(上海)有限公司 Formation method of LDMOS (Lateral Diffusion MOS) transistor and LDMOS transistor

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