CN106130380A - A kind of mixing one circle control method improved in modular multilevel commutator - Google Patents

Abstract

The invention discloses the mixing Cycle Control method improved in a kind of modular multilevel commutator.On the basis of classical Cycle Control (OCC) and the weber principle of equal effects, establish modular multilevel commutator MMR bridge arm equivalent dutycycle and the corresponding relation between the working cycle of each submodule；Then by the virtual cyclic mapping under correct direction, balance dynamic capacitance voltage and reduce the switching frequency of submodule, eliminating DC voltage second harmonic, there is singlephase earth fault fault-tolerant ability, propose negative sequence voltage penalty method based on power limitation control, thus eliminate DC voltage ripple.Owing to commutator is operated in unity power factor, the requirement of gate inductance has been declined by it.Whole control scheme has only to a PI controller, therefore the control program of this simplification greatly reduces system cost and the complexity of system control.

Description

A kind of mixing one circle control method improved in modular multilevel commutator

Technical field

The present invention relates to the mixing one circle control method improved in modular multilevel commutator, the method is based on the monocycle Control and virtual cyclic mapping method, signal is processed, belongs to modular multilevel commutator technical field.

Background technology

Transducer, as an important component part in energy conversion system, is usually designed to be converted to alternating current Direct current (commutator) or direct current is converted to exchange (inverter).Through the development of more than 20 years, in various changer skills In art, Modular multilevel converter (MMC) is rising, and it has much compared with traditional multi-level converter Advantage, such as, the degree of modularity is high, the low and low total harmonic distortion of switching frequency (THD).

In practice, a large amount of topologys back-to-back that use, wherein commutator and inverter connect and and dc bus back-to-back Voltage is relevant.The design of commutator keeps DC bus-bar voltage constant, is the key of whole MMC systematic function.Meanwhile, MMC quilt It is used at Balanced or unbalanced network operation.Such as, single-phase earthing (SLG) fault, cause the imbalance of line voltage and electric current, Cause MMC poor performance, such as, DC voltage ripple and ac bus current imbalance.In this case, MMC is required knot Close effective control program, to eliminate or to alleviate the impact of unbalanced power grid, it is ensured that its performance.

Nearest document proposes substantial amounts of MMC control program under the conditions of unbalanced power supply.Such as, it is proposed that one The individual double-current control program for MMC and positive and negative sequence current controller, and an extra zero-sequence current controller controlling party The design of case suppresses DC voltage ripple voltage uneven；Propose second harmonic in suppression MMC-HVDC system dc voltage A secondary control scheme, but this need a particular design second order filter, add the complexity of system；Propose Ratio resonance (PR) control program is with suppression harmonic circulating current and eliminates the power swing at DC side.

The major part that note that above-mentioned control program is based on instantaneous power theory.They utilize proportional integral (PI) Controller or a kind of system of 3 axes PR controller of use, including dq synchronous rotating frame, a-b-c frozen frozen mass, and alpha-beta is static Frame.But, coordinate transform increases control system and the complexity of transformation matrix, reduces the speed of service of whole MMC system. Such as, each as there being two PI controllers to produce multiple PI parameters, add enforcement difficulty.

By contrast, one circle control (OCC) scheme is feasible and simple.One typical OCC scheme can only make Realize with a PI controller, thus reduce the complexity of system and meet the requirement of the certain MMC application of performance requirement. Although, owing to the OCC scheme that the limitation of self is traditional is seldom used in MMC capacitor voltage balance and reduces on switching frequency.

Therefore extremely it is necessary at present to develop and is applicable to the Cycle Control scheme of MMC and realizes active voltage balancing, and reduce Switching frequency.

Summary of the invention

In order to overcome above-mentioned the deficiencies in the prior art, the invention provides improvement in a kind of modular multilevel commutator Mixing one circle control method, the method based on One-Cycle Control and virtual cyclic mapping method, only needs in the design of commutator Wanting a PI controller, structure is simplified, and optimizes rectification effect simultaneously, greatly reduces the complexity of system control and is System cost.

The technical scheme is that the mixing one circle control method improved in a kind of modular multilevel commutator, On the basis of classical one circle control and the weber principle of equal effects, establish the upper bridge of any one phase of modular multilevel commutator Arm and the equivalent dutycycle of lower brachium pontis and the corresponding relation between the working cycle of each submodule, modular multilevel commutator list Input phase voltage U mutually_j, the scope of j=a, b, c can be divided into four region I IV；

Table one VSM transfer relationship is analyzed

Wherein: V_cFor submodule capacitor voltage, 1 ' to 4 ' represents four virtual subnet modules VSM of upper arm, and 5 ' to 8 ' generations Four virtual subnet modules VSM of table underarm；1 represents that VSM is open-minded, and 0 represents that VSM turns off；(1:0) pulse width modulation (PWM) letter is represented Number change to 0 from 1, bridge arm equivalent dutycycle d in correspondence_jn, j=a, b, c, n=1～4, d_jnThe n-th of expression jth phase is virtual The upper bridge arm equivalent dutycycle of submodule VSM；(0:1) representing that pwm signal changes to 1 from 0, the working cycle is equal to (1-d_jn).This A little particularly arrangements combine with suitable cyclic mapping direction and can reduce the switching frequency of MMC.

Further, when electrical network generation singlephase earth fault SLG, by regulation upper and lower bridge arm equivalence dutycycle, it is possible to Suppression DC voltage fluctuation, maintains stablizing of DC bus-bar voltage；According to voltage-second balance, when being operated in four region I IV, under Bridge arm equivalent dutycycle D_jnWith upper bridge arm equivalent dutycycle d_jnBetween be respectively present following relation as shown in Table 2:

Table two D_jnAnd d_jnRelation table

Wherein: U_jnFor input AC phase voltage, U_dcFor dc bus output voltage, D_jnThe n-th of expression jth phase is virtual The lower bridge arm equivalent dutycycle of submodule VSM；

Utilize table two relation can balance each submodule dynamic capacity voltage and reduce insulated gate in each submodule The switching frequency of bipolar transistor IGBT, substitutes into the number of modular multilevel commutator as described below by above-mentioned table two relation Model expression:

$R_s{I}_j==\frac{R_s}{2R_e}{U}_{dc}(1-2D_{jn}-\frac{4e_{j-}}{U_{dc}})=V_m(1-2D_{jn}-\frac{4e_{j-}}{U_{dc}})$

Obtain each region mixing Cycle Control final formula:

Region I:

Region II:

Region III:

Region IV:

In formula, R_sIt is the inductive reactance of input current, R_eFor power equivalent resistance, I_jFor j phase input current；By above formula, Each region can be obtained and input the control signal of virtual cyclic mapping VLM.

The mixing technical scheme taked of one circle control method improved in modular multilevel commutator of the present invention include as Lower step:

(1) DC voltage controls to obtain V through PI_mValue.

(2) to signal V_m(-tx/ τ) is integrated, integral result and the voltage feedback value of negative sequence component and output unidirectional current The error controling signal superposition of pressure, obtains final argument.

(3) supposing that upper and lower arm SM number is 4 (n=4), real submodule (RSM) is numbered from 1 to 8.By multistage single-revolution Phase controls (MOCC) and amplifies PWM output, and RSMS is transformed into RSM by virtual cyclic mapping (VLM) from VSM.

(4) in this case, MMR input voltage (UJ) scope can be divided into four region I IV, and transfer truth table is table One, 1 to 4 represents upper arm VSM, and 5 to 8 represent underarm VSM.Here " 1 " means what corresponding VSM was on, " 0 " table Show shutoff.(1:0) represent pwm signal from " 1 " to " 0 ", duty ratio corresponding d_jn.(0:1) represent that pwm signal changes to from " 0 " " 1 ", and its working cycle is equal to (1-d_jn).These particularly arrange to combine can reduce with suitable cyclic mapping direction The switching frequency of MMC.According to voltage-second balance, D_jnAnd d_jnBetween there is following relation as shown in Table 3.Above-mentioned relation is substituted into The mathematical model expression formula of modular multilevel commutator as described below:

$R_s{I}_j==\frac{R_s}{2R_e}{U}_{dc}(1-2D_{jn}-\frac{4e_{j-}}{U_{dc}})=V_m(1-2D_{jn}-\frac{4e_{j-}}{U_{dc}})$

(5) the final formula finally trying to achieve each region in table three third column utilizes the final argument obtained, in each cycle In, with parameter R_xixCompare.When each cycle starts, final parameter is less than R_xix, comparative result is after not gate Control signal as output.

Table three mixes the derivation of Cycle Control HOCC formula

(6) when final argument is equal to R_xix, output state changes, and this state will be continued until this end cycle, and now amass Point device composes 0 value final control signal through VLM, respectively as the control signal of each submodule.

Entirety of the present invention mixing Cycle Control scheme, has an advantage in that: having only to a PI controller, structure is able to letter Change, optimize rectification effect simultaneously, greatly reduce complexity and system cost that system controls.

Accompanying drawing explanation

Fig. 1 is modular multilevel rectifier topology structure；

Fig. 2 is the FB(flow block) of the present invention；

Fig. 3 is modular multilevel commutator equivalent model figure；

Fig. 4 is upper brachium pontis virtual cyclic mapping graph of a relation；

Fig. 5 is lower brachium pontis virtual cyclic mapping graph of a relation；

Fig. 6 is electrical network three-phase alternating voltage (e_a, e_b, e_c), modular multilevel commutator input AC electric current (I_a, I_b, I_c) and dc bus output voltage (U_dc) oscillogram；

Fig. 7 is a phase virtual subnet module 1 '～4 ' pwm control signal figure；

Fig. 8 is true the submodule 1～4PWM control signal figure of a phase；

Fig. 9 is electrical network a phase voltage e_a, MMR a phase input current I_a, MMR exports DC bus-bar voltage U_dc；

Figure 10 is MMR a phase middle point voltage U_aPwm signal with SM1；

Figure 11 is a phase input current of MMR when there is single-phase earthing SLG fault；

Figure 12 is for introducing MMR input current when a phase after fault tolerant mechanism occurs single-phase earthing SLG fault；

Figure 13 is DC bus-bar voltage ripple during generation a phase SLG fault.

Figure 14 is submodule (SM) topological diagram.

Detailed description of the invention

Below in conjunction with drawings and Examples, the invention will be further described.

Fig. 1 is modular multilevel rectifier topology figure, and wherein SM represents submodule as shown in figure 14, and L represents each The inductance of each brachium pontis mutually, A, B are dc bus.

Traditional Three-Phase PWM Rectifier Cycle Control is theoretical as follows:

In Three-Phase PWM Rectifier Cycle Control system, if V_dcFor rectifier DC side voltage, i_a,i_b,i_cFor net side three Cross streams electric current, if brachium pontis switching tube S under commutator_an,S_bn,S_cnDutycycle be respectively d_an、d_bn、d_cn, then commutator equivalence Circuit is as shown in Figure 3.

According to the equivalent circuit of Fig. 3, node A is surveyed in commutator exchange, and B, the C average voltage relative to node N is:

u_Xn=d_xpv_dc

In formula: x=A, B, C, x=a, b, c.Relative to neutral point O, line voltage vectorExchange with photovoltaic DC-to-AC converter Side voltage vectorMeet

${\stackrel{\→}{u}}_{Xo}={\stackrel{\→}{u}}_{xo}+{\mathrm{j\ω}}_{O}L{\stackrel{\→}{i}}_x$

In formula: ω₀For electrical network power frequency angular frequency；L is that inductance surveyed by three-phase bridge net.Less in view of net side inductance, negligible The power frequency pressure drop of inductance, then line voltage meets with Three-Phase PWM Rectifier each brachium pontis dutycycle:

$\left[\begin{array}{ccc}-2/3& 1/3& 1/3\\ 1/3& -2/3& 1/3\\ 1/3& 1/3& 2/3\end{array}\right]\left[\begin{array}{c}{d}_{an}\\ d_{bn}\\ d_{cn}\end{array}\right]\frac{1}{v_{dc}}\left[\begin{array}{c}{e}_a\\ e_b\\ e_c\end{array}\right]---\left(1\right)$

In formula (1), the order of coefficient matrix is 2, therefore there is the most possible solution, i.e.

$\left\{\begin{array}{c}{d}_{an}=k_1^{,}-e_a/v_{dc}\\ d_{bn}=k_1^{,}-e_b/v_{dc}\\ d_{cn}=k_1^{,}-e_c/v_{dc}\end{array}\right.---\left(2\right)$

In formula, k '₁It can be arbitrary constant.Owing to dutycycle d meets 0 < d < 1, can obtain:

$\frac{e_x}{v_{dc}}<k_1^{,}<1+e_x/v_{dc}---\left(3\right)$

According to above formula, for ensureing k '₁Being a constant not changed with electrical network instantaneous voltage, formula (3) must is fulfilled for

max(e_x/v_dc)<min(1+e_x/v_dc)

Therefore k '₁Must meet

$\frac{E_{mx}}{v_{dc}}<k_1^{,}<1-\frac{E_{mx}}{v_{dc}}---\left(4\right)$

In formula, E_mxFor grid voltage amplitude.Understand according to formula (4), three-phase rectifier Cycle Control system dc side voltage Following relation is met, i.e. with voltage on line side amplitude

$\frac{E_{mx}}{v_{dc}}<1-\frac{E_{mx}}{v_{dc}}$

Obtain:

v_dc>2E_mx (5)

On the premise of meeting formula (5), k₁The midpoint of bound in retrievable (4), i.e.

k’₁=0.5

When commutator unity power factor runs, line voltage meets following relation, i.e. with net side alternating current

i_x=e_x/R_e (6)

In formula: R_eFor power equivalent resistance.

Introduce current sampling resistor R_s, formula (6) is represented by

$R_s{i}_x=\frac{k_1^{,}{R}_s}{R_e}{v}_{dc}(1-\frac{d_{xn}}{k_1^{\&prime;}})---\left(8\right)$

In formula, x=a, b, c, by dutycycleSubstitute into (8) to obtain

$R_s{i}_x=\frac{k_1^{,}{R}_s}{R_e}{v}_{dc}(1-\frac{t_s}{T_s{k}_1^{\&prime;}})---\left(9\right)$

T_sSwitch periods for IGBT；v_mFor DC side error control voltage, τ is the long-pending of integrator in Cycle Control system Divide time constant, τ=k '₁T_s。

$\left\{\begin{array}{c}{R}_s{i}_a=-v_m(\frac{t_a}{\mathrm{\&tau;}}-1)\\ R_s{i}_b=-v_m(\frac{t_b}{\mathrm{\&tau;}}-1)\\ R_s{i}_c=-v_m(\frac{t_c}{\mathrm{\&tau;}}-1)\end{array}\right.---\left(10\right)$

Three-Phase PWM Rectifier Cycle Control system structure can be obtained according to formula (10).

As in figure 2 it is shown, in above-mentioned traditional three-phase grid-connected inverter Cycle Control theoretical basis, for a kind of modularity The mixing one circle control method that multi-level rectifier improves, comprises the steps:

In outer voltage, DC voltage controls to obtain V through PI_mValue,

$V_m=(K_p+\frac{K_I}{s})(U_{dc}^{*}-U_{dc})$

1) combining relevant parameter, submodule electric capacity is 2200 μ F, brachium pontis inductance 2mH, K_pTake 0.5, K_ITake 10.

2) to signal V_m(-tx/ τ) is integrated, the integration time constant of integrator during wherein τ is Cycle Control system, Result superposes with voltage feedback value and the error controling signal of the negative sequence component of every phase input voltage, obtains final argument.

$R_s{I}_j=V_m(1-\frac{d_{jn}}{2}-\frac{4e_{j-}}{U_{dc}})$

$R_s{I}_j=V_m(\frac{1}{2}-\frac{d_{jn}}{2}-\frac{4e_{j-}}{U_{dc}})$

$R_s{I}_j=V_m(-\frac{d_{jn}}{2}-\frac{4e_{j-}}{U_{dc}})$

$R_s{I}_j=V_m(-\frac{1}{2}-\frac{d_{jn}}{2}-\frac{4e_{j-}}{U_{dc}})$

3) final argument obtained is utilized, within each cycle, with parameter R_xixCompare.When each cycle starts, Final argument is less than R_xix, comparative result after not gate as output control signal.

4) when final argument is equal to R_xix, changing output state, this state will be continued until this end cycle, now amass Device is divided to compose 0 value.Final control signal is through VLM, respectively as the control signal of each submodule.

Fig. 4 and Fig. 5 be respectively patterned into different display for upper, lower brachium pontis virtual cyclic mapping relation；Rising edge touches Send out enumerator " CMU " or " CML " (count range 0 (n-1)) with the true submodule of i-th or jth regulate together VSM and VLM between RSM.In this case, if C_MU=0,1 '-2 '-3 '-4 VSM will be mapped to that 1-2-3-4 RSM, as Really C_MU=1 and, 4 '-1 '-2 '-3 ' a number VSM will be mapped to that 1-2-3-4 RSM.

In simulations, as shown in Table 1, during electrical network 1 second there is single-phase fault in a phase to experiment relevant parameter, opens when 1.3s Fault recovery.In this case, line voltage, result such as Fig. 6 institute of the input current of MMR and dc bus output voltage Show.As seen from the figure, after SLG fault (t=1.3s), line voltage and the unexpected disequilibrium of MMC input current, a phase line voltage Drastically decline with a phase input current.Result causes DC bus-bar voltage second order ripple occur, as shown in Fig. 6 (c), and its peak-to-peak value Being about 5V, this is equivalent to the 3.3% of dc bus average voltage.By contrast, there is the system of fault-tolerant ability, at relevant recovering After action enforcement (T=1.3s), the peak-to-peak value of second order ripple is significantly reduced to 1.5V, 1/4 before fluctuation only, is about average The 1% of DC bus-bar voltage.Obviously, the control strategy of proposition eliminates second harmonic ripple and the MMR realization of DC voltage The fault-tolerant ability of singlephase earth fault.

Table one simulation parameter

Additionally, Fig. 7 and Fig. 8 and provide the pwm signal of virtual and true submodule between 1.20s to 1.26s respectively.Can by figure Seeing, a phase virtual subnet module 1 '～4 ' pwm signal is widely different, especially duty cycle signals；Virtual subnet module 1 '～4 ' PWM believes Number with virtual cyclic mapping to true submodule.From a point of circulation, signal is averaged and is assigned to each true submodule. The difference of submodule switching frequency is to be limited to a certain extent.The capacitance voltage unbalance condition that dutycycle difference causes Make moderate progress.Additionally, the final switching frequency of virtual subnet module is fs/4, the most about 500Hz.This considerably reduce equipment Switching loss.

Fig. 9 to 13 shows corresponding experimental result.First, under conditions of grid balance, the control program proposed is entered Go test.Line voltage e_a, a phase current I_a, Fig. 9 bottom waveform is MMR dc bus output voltage U_dcWaveform, at this In the case of DC voltage ripple the least, MMR a phase mid-point voltage U_aWith true submodule pwm signal as shown in Figure 10.

The above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art For Yuan, under the premise without departing from the principles of the invention, it is also possible to make some improvements and modifications, these improvements and modifications also should It is considered as protection scope of the present invention.

Claims (2)

1. the mixing one circle control method improved in a modular multilevel commutator, it is characterised in that: at classical single-revolution Phase controls and on the basis of the weber principle of equal effects, establishes the upper brachium pontis of any one phase of modular multilevel commutator and lower brachium pontis Equivalent dutycycle and corresponding relation between the working cycle of each submodule, the single-phase input of modular multilevel commutator is mutually electric Pressure U_j, the scope of j=a, b, c can be divided into four region I IV；

Table one VSM transfer relationship is analyzed

Wherein: V_cFor submodule capacitor voltage, 1 ' to 4 ' represents four virtual subnet modules VSM of upper arm, and 5 ' to 8 ' represent underarm Four virtual subnet modules VSM；1 represents that VSM is open-minded, and 0 represents that VSM turns off；(1:0) represent that pulse width modulation (PWM) signal becomes from 1 Change to 0, bridge arm equivalent dutycycle d in correspondence_jn, j=a, b, c, n=1～4, d_jnRepresent the n-th virtual subnet module of jth phase The upper bridge arm equivalent dutycycle of VSM；(0:1) representing that pwm signal changes to 1 from 0, the working cycle is equal to (1-d_jn)。

The mixing one circle control method improved in modular multilevel commutator the most according to claim 1, its feature exists In: during at electrical network generation singlephase earth fault SLG, by regulation upper and lower bridge arm equivalence dutycycle, it is possible to suppression DC voltage ripple Dynamic, maintain stablizing of DC bus-bar voltage；According to voltage-second balance, when being operated in four region I IV, lower bridge arm equivalent dutycycle D_jnWith upper bridge arm equivalent dutycycle d_jnBetween be respectively present following relation as shown in Table 2:

Table two D_jnAnd d_jnRelation table

Wherein: U_jnFor commutator exchange input phase voltage, U_dcFor dc bus output voltage, D_jnRepresent the n-th void of jth phase Intend the lower bridge arm equivalent dutycycle of submodule VSM；

Utilize table two relation can balance each submodule dynamic capacity voltage and reduce insulated gate bipolar in each submodule The switching frequency of transistor npn npn IGBT, substitutes into the mathematical modulo of modular multilevel commutator as described below by above-mentioned table two relation Type expression formula:

$R_s{I}_j==\frac{R_s}{2R_e}{U}_{dc}(1-2D_{jn}-\frac{4e_{j-}}{U_{dc}})=V_m(1-2D_{jn}-\frac{4e_{j-}}{U_{dc}})$

Obtain each region mixing Cycle Control final formula:

Region I:

Region II:

Region III:

Region IV:

In formula, R_sIt is the inductive reactance of input current, I_jFor j phase input current；Pass through above formula, it is possible to obtain each region input void Intend the control signal of cyclic mapping VLM.