CN106129173B - A kind of manufacture method of N-type double-side cell - Google Patents
A kind of manufacture method of N-type double-side cell Download PDFInfo
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- CN106129173B CN106129173B CN201610514814.6A CN201610514814A CN106129173B CN 106129173 B CN106129173 B CN 106129173B CN 201610514814 A CN201610514814 A CN 201610514814A CN 106129173 B CN106129173 B CN 106129173B
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- 238000000034 method Methods 0.000 title claims abstract description 74
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 66
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 65
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 65
- 239000010703 silicon Substances 0.000 claims abstract description 65
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 47
- 229910052796 boron Inorganic materials 0.000 claims abstract description 47
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical group CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 claims abstract description 36
- 239000005297 pyrex Substances 0.000 claims abstract description 36
- 229910004205 SiNX Inorganic materials 0.000 claims abstract description 32
- 238000009792 diffusion process Methods 0.000 claims abstract description 23
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 22
- 239000011521 glass Substances 0.000 claims abstract description 22
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 22
- 239000011574 phosphorus Substances 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 20
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 11
- 210000002268 wool Anatomy 0.000 claims abstract description 9
- 238000002360 preparation method Methods 0.000 claims description 10
- 238000007650 screen-printing Methods 0.000 claims description 9
- 239000002002 slurry Substances 0.000 claims description 6
- 238000002161 passivation Methods 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 230000008020 evaporation Effects 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 3
- 239000007788 liquid Substances 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 238000003631 wet chemical etching Methods 0.000 claims description 3
- 229910021426 porous silicon Inorganic materials 0.000 abstract description 8
- 150000001875 compounds Chemical class 0.000 abstract description 6
- 230000005611 electricity Effects 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000002209 hydrophobic effect Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- HIVGXUNKSAJJDN-UHFFFAOYSA-N [Si].[P] Chemical compound [Si].[P] HIVGXUNKSAJJDN-UHFFFAOYSA-N 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
This application discloses a kind of manufacture method of N-type double-side cell, including：Silicon chip is cleaned and surface wool manufacturing；Boron diffusion is carried out in the front and back of the silicon chip, front boron is formed and expands layer and back side boron expansion layer, the surface that the front boron expands layer is Pyrex；SiN is prepared in the front of the silicon chipxMask；Etch away the SiNxMask and the back side boron expand layer；Front side of silicon wafer formation is protected using the Pyrex, phosphorus diffusion is carried out at the back side of the silicon chip, back side phosphorus is formed and expands layer, the surface that the back side phosphorus expands layer is phosphorosilicate glass；Etch away the Pyrex and the phosphorosilicate glass；SiN is prepared in the front and back of the silicon chipxPassivating film, and preceding electrode and back electrode are prepared respectively.The above method can reduce the time of HF etchings, it is to avoid the formation of back side porous silicon, so that the effectively compound parallel resistance and open-circuit voltage so as to improve battery of reduction cell backside, improves battery efficiency.
Description
Technical field
The invention belongs to photovoltaic apparatus manufacturing technology field, more particularly to a kind of manufacture method of N-type double-side cell.
Background technology
AT＆T Labs of the U.S. in 1954 prepares the single crystal silicon solar cell that first piece of conversion efficiency is 6% in the world,
By scientist's continuous exploration of more than 60 years, solar cell achieves huge breakthrough, and highest conversion efficiency has reached
46% (light-focusing multi-junction GaAs).Occupy the p-type crystal silicon solar battery of photovoltaic market for many years and gradually show the tired state of efficiency growth, light
The inferior position such as the amplitude that declines is excessive.Although being substituted with Ga, B is atom doped can to avoid photo attenuation effect, caused wide therefrom
Resistivity distribution and Fe element pollution problems, can still restrict the further raising of p-type battery efficiency.N-type sun electricity
Chi Ze has benefited from its high efficiency, the advantage of low decay, as study hotspot new in photovoltaic industry.In high-efficiency N-type technical elements,
Most typical representative is the IBC batteries of SunPower companies of the U.S. and the HIT batteries of Panasonic companies of Japan.But both
The shortcoming of battery technology is that very expensive production equipment, complex process, manufacturing cost are very high, also has very high art wall in addition
Build.And the final goal of photovoltaic industry is reduction cost of electricity-generating, the research and development of N-type high-efficiency battery must avoid the technology path of complexity
To reduce process costs.The technology path of N-type double-side cell merely add back side diffusion and passivation work than conventional P-type battery
Skill, nearly all equipment can be developed using existing volume production equipment, and increased equipment and technology cost is very low, be that most have can
Volume production can be realized.
When preparing double-side cell, realizing the method for one side diffusion has：Ion implanting, one side etching and gluing diffusion, this three
Planting technique all can not be compatible with existing conventional polycrystalline producing line, and ion implanting and one side etching are required for introducing expensive set
It is standby, and B glue can then introduce Organic Pollution in high-temperature diffusion process.The method compatible with conventional polycrystalline producing line is positive B
Utilization SiN is expandedxFilm does back side P diffusion masks, then recycles HF to remove front SiNx, BSG and back side PSG films.But
Thus have a problem that：SiNxFilm is after P expands high temperature, and etch rate is very low, so that cause etch period long, this
Sample will overleaf form porous silicon, and porous silicon can make back side specific surface area increase, and passivation effect is deteriorated, and battery is compound to be increased
Plus, reduce battery efficiency.
The content of the invention
To solve the above problems, the invention provides a kind of manufacture method of N-type double-side cell, HF etchings can be reduced
Time, it is to avoid the formation of back side porous silicon, so that the effectively compound parallel resistance so as to improve battery of reduction cell backside
And open-circuit voltage, improve battery efficiency.
A kind of manufacture method for N-type double-side cell that the present invention is provided, including：
Silicon chip is cleaned and surface wool manufacturing；
Boron diffusion is carried out in the front and back of the silicon chip, front boron is formed and expands layer and back side boron expansion layer, the front
The surface that boron expands layer is Pyrex；
SiN is prepared in the front of the silicon chipxMask；
Etch away the SiNxMask and the back side boron expand layer；
Front side of silicon wafer formation is protected using the Pyrex, phosphorus diffusion, shape are carried out at the back side of the silicon chip
Expand layer into back side phosphorus, the surface that the back side phosphorus expands layer is phosphorosilicate glass；
Etch away the Pyrex and the phosphorosilicate glass；
SiN is prepared in the front and back of the silicon chipxPassivating film, and preceding electrode and back electrode are prepared respectively.
It is preferred that, in the manufacture method of above-mentioned N-type double-side cell,
It is described to etch away the SiNxMask and the back side boron, which expand layer, to be included：
Utilize the concentration of etching liquid, etch rate and the SiNxThe thickness of mask, calculates etch period, Ran Hougen
According to the etch period, the SiN is etched awayxMask and the back side boron expand layer.
It is preferred that, in the manufacture method of above-mentioned N-type double-side cell,
It is described to etch away the SiNxMask and the back side boron expand layer：
The SiN that the HF solution refractive index for being 5% to 10% using concentration is 2.1 and thickness is 30nm to 40nmxMask
Etching 5 minutes to 10 minutes.
It is preferred that, in the manufacture method of above-mentioned N-type double-side cell,
It is described to etch away the Pyrex and the phosphorosilicate glass is：
The Pyrex and the phosphorosilicate glass are etched 10 minutes to 20 for 5% to 10% HF solution using concentration
Minute.
It is preferred that, in the manufacture method of above-mentioned N-type double-side cell,
The front and back in the silicon chip prepares SiNxPassivating film includes：
Prepare that ranges of indices of refraction is 2.04 to 2.11 and thickness range is 60nm to 80nm's in the front of the silicon chip
SiNxPassivating film, in the back side preparation ranges of indices of refraction of the silicon chip be 2.04 to 2.11 and thickness range is 80nm to 100nm
SiNxPassivating film.
It is preferred that, in the manufacture method of above-mentioned N-type double-side cell,
It is described silicon chip to be cleaned and surface wool manufacturing includes：
Silicon chip is cleaned, and in the positive gold that the surface shape of the silicon chip is at 45 ° by the way of wet chemical etching technique
Word tower matte.
It is preferred that, in the manufacture method of above-mentioned N-type double-side cell,
The thickness that the front boron expands the Pyrex on the surface of layer is 100nm to 200nm.
It is preferred that, in the manufacture method of above-mentioned N-type double-side cell,
The front in the silicon chip prepares SiNxMask is：
The silicon chip front using plasma reinforced chemical vapour deposition mode prepare thickness range for 10nm extremely
80nm SiNxMask.
It is preferred that, in the manufacture method of above-mentioned N-type double-side cell,
Electrode and back electrode include before the preparation：
The preceding electrode and the back electrode are prepared using silk-screen printing, evaporation or sputtering mode.
It is preferred that, in the manufacture method of above-mentioned N-type double-side cell,
Electrode and back electrode include before the preparation：
The preceding electrode is prepared by the way of silk-screen printing Ag slurries, institute is prepared by the way of silk-screen printing Al slurries
Back electrode is stated, and is sintered.
By foregoing description, the manufacture method for the N-type double-side cell that the present invention is provided, due to including：Silicon chip is entered
Row cleaning and surface wool manufacturing；Boron diffusion is carried out in the front and back of the silicon chip, front boron is formed and expands layer and back side boron expansion layer,
The surface that the front boron expands layer is Pyrex；SiN is prepared in the front of the silicon chipxMask；Etch away the SiNxMask
Expand layer with the back side boron；Front side of silicon wafer formation is protected using the Pyrex, carried out at the back side of the silicon chip
Phosphorus diffusion, forms back side phosphorus and expands layer, the surface that the back side phosphorus expands layer is phosphorosilicate glass；Etch away the Pyrex and described
Phosphorosilicate glass；SiN is prepared in the front and back of the silicon chipxPassivating film, and preceding electrode and back electrode, therefore energy are prepared respectively
The time of HF etchings is enough reduced, it is to avoid the formation of back side porous silicon, so that effective reduction cell backside is compound so as to improving
The parallel resistance and open-circuit voltage of battery, improve battery efficiency.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the accompanying drawing used required in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
The embodiment of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can also basis
The accompanying drawing of offer obtains other accompanying drawings.
The schematic diagram of the manufacture method for the first N-type double-side cell that Fig. 1 provides for the embodiment of the present application；
Fig. 2-Fig. 8 is corresponding for each step of the manufacture method with the first N-type double-side cell that the embodiment of the present application is provided
Device schematic diagram.
Embodiment
The present invention core concept be to provide a kind of manufacture method of N-type double-side cell, can reduce HF etching when
Between, it is to avoid the formation of back side porous silicon so that the compound parallel resistance so as to improve battery of effective reduction cell backside and
Open-circuit voltage, improves battery efficiency.
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
The manufacture method for the first N-type double-side cell that the embodiment of the present application is provided is as shown in figure 1, Fig. 1 is that the application is real
The schematic diagram of the manufacture method of the first N-type double-side cell of example offer is provided.This method comprises the following steps：
S1：Silicon chip is cleaned and surface wool manufacturing；
In this step, with reference to Fig. 2, what can be selected is the silicon chip 1 of p-type, using ripe monocrystalline silicon wafer alkaline flocking work
Skill, the matte 2 of Pyramid is totally prepared in its surface clean afterwards.
S2：Carry out boron diffusion in the front and back of the silicon chip, form front boron and expand layer and back side boron and expand layer, it is described just
The surface that face boron expands layer is Pyrex；
In this step, with reference to Fig. 3, by taking front side of silicon wafer as an example, form front boron and expand layer 3, boron expands the upper of layer 3 in front
Face is Pyrex 4, and sheet resistance is about 60-200 Ω/sq after the completion of diffusion, and junction depth is 0.3-0.6um.
S3：SiN is prepared in the front of the silicon chipxMask；
With reference to Fig. 4, layer of sin is made on the surface of above-mentioned Pyrex 4xMask 5, the thickness and etching of SiNx masks 5
Technique is relevant, it is ensured that SiN after etchingxPositive BSG thickness can not be damaged by complete etching again.
S4：Etch away the SiNxMask and the back side boron expand layer；
With reference to Fig. 5, SiN is utilizedxMask can prevent positive Pyrex to be etched away.After etching, leave behind just
Face boron expands layer 3 and Pyrex 4, overleaf forms smooth surface.The technique and SiN of etchingxThe thickness of etch mask needs
Constantly adjustment, the boron at the back side, which expands layer and BSG, to be etched away completely, positive SiNxEtch mask should also be removed completely, but front
BSG films need to completely retain.
S5：Front side of silicon wafer formation is protected using the Pyrex, phosphorus diffusion is carried out at the back side of the silicon chip,
Form back side phosphorus and expand layer, the surface that the back side phosphorus expands layer is phosphorosilicate glass；
With reference to Fig. 6, after the back side phosphorus diffusion of silicon chip, form back side phosphorus and expand layer 6, that is, n+ layers, overleaf phosphorus
The surface for expanding layer 6 is phosphorosilicate glass 7, can be realized, spread using diffusion technique ripe on manufacture of solar cells line
It is about 80-100 Ω/sq into rear sheet resistance, junction depth is about 0.3um.Here with Pyrex formed to positive protection, due to
This Pyrex are easily removed in follow-up process, thus avoid etch period it is long caused by back side porous silicon formed.
S6：Etch away the Pyrex and the phosphorosilicate glass；
With reference to Fig. 7, now leave behind front boron and expand layer 3 and back side phosphorus expansion layer 6, due to the Pyrex and the phosphorus silicon
Glass surface is all hydrophilic, and Si surfaces are then hydrophobic properties.It is etched to visual observation battery front side and the back side is all hydrophobic, then
Represent that the Pyrex and the phosphorosilicate glass have been completely removed.
S7：SiN is prepared in the front and back of the silicon chipxPassivating film, and preceding electrode and back electrode are prepared respectively.
With reference to Fig. 8, SiN is made in front side of silicon wafer and the back sidexPassivating film 8, can reduce the reflection of positive light, again can be with
Effective surface passivation effect is played, and produces preceding electrode 9 and back electrode 10, finally using sintering process, is formed well
Ohmic contact, this completes the making of whole battery.
The manufacture method of the first the above-mentioned N-type double-side cell provided by foregoing description, the embodiment of the present application, by
In including：Silicon chip is cleaned and surface wool manufacturing；Boron diffusion is carried out in the front and back of the silicon chip, front boron is formed and expands
Layer and back side boron expand layer, and the surface that the front boron expands layer is Pyrex；SiN is prepared in the front of the silicon chipxMask；Carve
SiN described in eating awayxMask and the back side boron expand layer；Front side of silicon wafer formation is protected using the Pyrex, in institute
The back side for stating silicon chip carries out phosphorus diffusion, forms back side phosphorus and expands layer, the surface that the back side phosphorus expands layer is phosphorosilicate glass；Etch away institute
State Pyrex and the phosphorosilicate glass；SiN is prepared in the front and back of the silicon chipxPassivating film, and preceding electricity is prepared respectively
Pole and back electrode, therefore, it is possible to reduce the time of HF etchings, it is to avoid the formation of back side porous silicon, so that the effectively reduction battery back of the body
The compound parallel resistance and open-circuit voltage so as to improve battery in face, improves battery efficiency.
The manufacture method for second of N-type double-side cell that the embodiment of the present application is provided, is in the above-mentioned two-sided electricity of the first N-type
On the basis of the manufacture method in pond, in addition to following technical characteristic：
It is described to etch away the SiNxMask and the back side boron, which expand layer, to be included：
Utilize the concentration of etching liquid, etch rate and the SiNxThe thickness of mask, calculates etch period, Ran Hougen
According to the etch period, the SiN is etched awayxMask and the back side boron expand layer., it is necessary to be carried out to technique real during concrete operations
When adjust, it is ensured that the two can be entirely removed simultaneously.
The manufacture method for the third N-type double-side cell that the embodiment of the present application is provided, is in the above-mentioned two-sided electricity of the first N-type
On the basis of the manufacture method in pond, in addition to following technical characteristic：
It is described to etch away the SiNxMask and the back side boron expand layer：
The SiN that the HF solution refractive index for being 5% to 10% using concentration is 2.1 and thickness is 30nm to 40nmxMask
Etching 5 minutes to 10 minutes.The etch rate for the HF solution that such as concentration is 10% is 4nm/min, if surface plating 40nm
Film, then need to etch 10min.
The manufacture method for the 4th kind of N-type double-side cell that the embodiment of the present application is provided, is in the above-mentioned two-sided electricity of the first N-type
On the basis of the manufacture method in pond, in addition to following technical characteristic：
It is described to etch away the Pyrex and the phosphorosilicate glass is：
The Pyrex and the phosphorosilicate glass are etched 10 minutes to 20 for 5% to 10% HF solution using concentration
Minute.Using the cooperation of above-mentioned kinds of processes parameter, preferred plan is found, Pyrex and phosphorosilicate glass can be removed simultaneously.
The manufacture method for the 5th kind of N-type double-side cell that the embodiment of the present application is provided, be it is above-mentioned the first to the 4th kind of N
In the manufacture method of type double-side cell on the basis of any method, in addition to following technical characteristic：
The front and back in the silicon chip prepares SiNxPassivating film includes：
Prepare that ranges of indices of refraction is 2.04 to 2.11 and thickness range is 60nm to 80nm's in the front of the silicon chip
SiNxPassivating film, in the back side preparation ranges of indices of refraction of the silicon chip be 2.04 to 2.11 and thickness range is 80nm to 100nm
SiNxPassivating film.Here SiNxPassivating film can use the plural layers of gradually changed refractive index.
The manufacture method for the 6th kind of N-type double-side cell that the embodiment of the present application is provided, is in the above-mentioned 5th kind of two-sided electricity of N-type
On the basis of the manufacture method in pond, in addition to following technical characteristic：
It is described silicon chip to be cleaned and surface wool manufacturing includes：
Silicon chip is cleaned, and in the positive gold that the surface shape of the silicon chip is at 45 ° by the way of wet chemical etching technique
Word tower matte.
The manufacture method for the 7th kind of N-type double-side cell that the embodiment of the present application is provided, is in the above-mentioned 6th kind of two-sided electricity of N-type
On the basis of the manufacture method in pond, in addition to following technical characteristic：
The thickness that the front boron expands the Pyrex on the surface of layer is 100nm to 200nm.
The manufacture method for the 8th kind of N-type double-side cell that the embodiment of the present application is provided, is in the above-mentioned 7th kind of two-sided electricity of N-type
On the basis of the manufacture method in pond, in addition to following technical characteristic：
The front in the silicon chip prepares SiNxMask is：
Plasma reinforced chemical vapour deposition mode (PECVD is utilized in the front of the silicon chip:Plasma enhanced
Chemical vapor deposition) prepare the SiN that thickness range is 10nm to 80nmxMask.
The manufacture method for the 9th kind of N-type double-side cell that the embodiment of the present application is provided, is in the above-mentioned 8th kind of two-sided electricity of N-type
On the basis of the manufacture method in pond, in addition to following technical characteristic：
Electrode and back electrode include before the preparation：
The preceding electrode and the back electrode are prepared using silk-screen printing, evaporation or sputtering mode.
The manufacture method for the tenth kind of N-type double-side cell that the embodiment of the present application is provided, is in the above-mentioned 8th kind of two-sided electricity of N-type
On the basis of the manufacture method in pond, in addition to following technical characteristic：
Electrode and back electrode include before the preparation：
The preceding electrode is prepared by the way of silk-screen printing Ag slurries, institute is prepared by the way of silk-screen printing Al slurries
Back electrode is stated, and is sintered.
In summary, the above-mentioned various methods that the embodiment of the present application is provided, by SiNxMask etching technique is applied to N-type too
Positive energy battery etching and diffusion technique, one side method of diffusion are simple, and compatible with conventional polysilicon volume production line, process costs are low, and
And avoid Organic Pollution in high-temperature diffusion process.It is most of it is compatible with existing conventional solar cell preparation technology before
Put, the technique for simplifying N-type double-side cell, it is to avoid the introducing of expensive device, reduce being manufactured into for N-type double-side cell
This.So as to move towards practical, the creation of value.The present invention has the advantages that upper many and practical value, technically there is larger
It is progressive, and handy and practical effect is generated, thus more suitable for practicality.
The foregoing description of the disclosed embodiments, enables professional and technical personnel in the field to realize or using the present invention.
A variety of modifications to these embodiments will be apparent for those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, it is of the invention
The embodiments shown herein is not intended to be limited to, and is to fit to and principles disclosed herein and features of novelty phase one
The most wide scope caused.
Claims (10)
1. a kind of manufacture method of N-type double-side cell, it is characterised in that including：
Silicon chip is cleaned and surface wool manufacturing；
Boron diffusion is carried out in the front and back of the silicon chip, front boron is formed and expands layer and back side boron expansion layer, the front boron expands
The surface of layer is Pyrex；
SiN is prepared in the front of the silicon chipxMask；
Etch away whole SiNxMask and the back side boron expand layer；
Front side of silicon wafer formation is protected using the Pyrex, phosphorus diffusion is carried out at the back side of the silicon chip, the back of the body is formed
Face phosphorus expands layer, and the surface that the back side phosphorus expands layer is phosphorosilicate glass；
Etch away the Pyrex and the phosphorosilicate glass；
SiN is prepared in the front and back of the silicon chipxPassivating film, and preceding electrode and back electrode are prepared respectively.
2. the manufacture method of N-type double-side cell according to claim 1, it is characterised in that
It is described to etch away the SiNxMask and the back side boron, which expand layer, to be included：
Utilize the concentration of etching liquid, etch rate and the SiNxThe thickness of mask, calculates etch period, then according to institute
Etch period is stated, the SiN is etched awayxMask and the back side boron expand layer.
3. the manufacture method of N-type double-side cell according to claim 1, it is characterised in that
It is described to etch away the SiNxMask and the back side boron expand layer：
The SiN that the HF solution refractive index for being 5% to 10% using concentration is 2.1 and thickness is 30nm to 40nmxMask etching 5
Minute was to 10 minutes.
4. the manufacture method of N-type double-side cell according to claim 1, it is characterised in that
It is described to etch away the Pyrex and the phosphorosilicate glass is：
The Pyrex and the phosphorosilicate glass are etched 10 minutes to 20 points for 5% to 10% HF solution using concentration
Clock.
5. the manufacture method of the N-type double-side cell according to claim any one of 1-4, it is characterised in that
The front and back in the silicon chip prepares SiNxPassivating film includes：
The SiN that ranges of indices of refraction is 2.04 to 2.11 and thickness range is 60nm to 80nm is prepared in the front of the silicon chipxPassivation
Film, the SiN that ranges of indices of refraction is 2.04 to 2.11 and thickness range is 80nm to 100nm is prepared at the back side of the silicon chipxIt is blunt
Change film.
6. the manufacture method of N-type double-side cell according to claim 5, it is characterised in that
It is described silicon chip to be cleaned and surface wool manufacturing includes：
Silicon chip is cleaned, and in the positive pyramid that the surface shape of the silicon chip is at 45 ° by the way of wet chemical etching technique
Matte.
7. the manufacture method of N-type double-side cell according to claim 6, it is characterised in that
The thickness that the front boron expands the Pyrex on the surface of layer is 100nm to 200nm.
8. the manufacture method of N-type double-side cell according to claim 7, it is characterised in that
The front in the silicon chip prepares SiNxMask is：
The silicon chip front using plasma reinforced chemical vapour deposition mode prepare thickness range for 10nm to 80nm's
SiNxMask.
9. the manufacture method of N-type double-side cell according to claim 8, it is characterised in that
Electrode and back electrode include before the preparation：
The preceding electrode and the back electrode are prepared using silk-screen printing, evaporation or sputtering mode.
10. the manufacture method of N-type double-side cell according to claim 8, it is characterised in that
Electrode and back electrode include before the preparation：
The preceding electrode is prepared by the way of silk-screen printing Ag slurries, the back of the body is prepared by the way of silk-screen printing Al slurries
Electrode, and be sintered.
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| CN107394008A (en) * | 2017-08-02 | 2017-11-24 | 浙江晶科能源有限公司 | A kind of N-type double-sided solar battery piece and preparation method thereof |
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