CN106129114A - Groove power device and manufacture method - Google Patents
Groove power device and manufacture method Download PDFInfo
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- CN106129114A CN106129114A CN201610556911.1A CN201610556911A CN106129114A CN 106129114 A CN106129114 A CN 106129114A CN 201610556911 A CN201610556911 A CN 201610556911A CN 106129114 A CN106129114 A CN 106129114A
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- 238000000034 method Methods 0.000 title claims abstract description 77
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 60
- 239000000463 material Substances 0.000 claims abstract description 66
- 230000003647 oxidation Effects 0.000 claims abstract description 12
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims description 84
- 239000004065 semiconductor Substances 0.000 claims description 82
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 27
- 229910052751 metal Inorganic materials 0.000 claims description 25
- 239000002184 metal Substances 0.000 claims description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 21
- 229910052710 silicon Inorganic materials 0.000 claims description 21
- 239000010703 silicon Substances 0.000 claims description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 18
- 229920005591 polysilicon Polymers 0.000 claims description 17
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 16
- 235000012239 silicon dioxide Nutrition 0.000 claims description 13
- 239000000377 silicon dioxide Substances 0.000 claims description 13
- 238000005516 engineering process Methods 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- 229910052796 boron Inorganic materials 0.000 claims description 8
- 229910052698 phosphorus Inorganic materials 0.000 claims description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 7
- 239000011574 phosphorus Substances 0.000 claims description 7
- 230000008569 process Effects 0.000 claims description 7
- 239000011521 glass Substances 0.000 claims description 6
- 238000002161 passivation Methods 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims description 2
- 238000012545 processing Methods 0.000 abstract description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 13
- 239000001301 oxygen Substances 0.000 description 13
- 229910052760 oxygen Inorganic materials 0.000 description 13
- 150000002500 ions Chemical class 0.000 description 10
- 238000013461 design Methods 0.000 description 7
- 238000002513 implantation Methods 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 238000000137 annealing Methods 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 230000002159 abnormal effect Effects 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 238000011161 development Methods 0.000 description 3
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- 230000003628 erosive effect Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- RCJVRSBWZCNNQT-UHFFFAOYSA-N dichloridooxygen Chemical compound ClOCl RCJVRSBWZCNNQT-UHFFFAOYSA-N 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 241000790917 Dioxys <bee> Species 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910021478 group 5 element Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- VDGJOQCBCPGFFD-UHFFFAOYSA-N oxygen(2-) silicon(4+) titanium(4+) Chemical group [Si+4].[O-2].[O-2].[Ti+4] VDGJOQCBCPGFFD-UHFFFAOYSA-N 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
Abstract
Present invention is disclosed a kind of groove power device and manufacture method.A kind of groove power device of present invention offer and manufacture method; by the described gate material layers in groove being had higher than a part for the second trapping layer and this partial oxidation being produced the second oxide layer; and described second oxide layer covering part the second trapping layer; again by forming side wall; so that whole slot grid structure is all protected; slot grid structure is made not affected by contact hole instability technique in processing technique under the conditions of existing lithographic equipment; realize less live width and the production of bigger alignment surplus product, make the parameter of product and reliability meet requirement.
Description
Technical field
The present invention relates to field of semiconductor devices, particularly relate to a kind of groove power device and manufacture method.
Background technology
Power device can be divided into Power IC (integrated circuit) device and power discrete device two class, and power discrete device wraps again
(insulated gate bipolar is brilliant to include power MOSFET (Metal-Oxide Semiconductor field-effect transistor), high power transistor and IGBT
Body pipe) etc. device.Power device is all based on planar technology and produces in early days, but along with the development of semiconductor technology, small size, big
Power, high-performance become main development trend.As a example by planar technology MOSFET element, due to itself internal JFET
The restriction of (junction field effect transistor) dead resistance, the area of single primitive unit cell reduces limited, thus makes increase primitive unit cell density
Become highly difficult, be difficult to make the conducting resistance (RDSON) of planar technology MOSFET to reduce further.Trench process is due to by raceway groove
Become vertical from level, eliminate the impact of planar structure parasitism JFET resistance, make cellular size be substantially reduced, on this basis
Primitive unit cell density can be increased, the overall width of raceway groove in raising unit are chip, it is possible to make device ditch on unit silicon chip
Road breadth length ratio increases so that electric current increases, conducting resistance declines and relevant parameter is optimized, it is achieved that smaller size of
Tube core has greater power and high performance target, and therefore trench process is more and more applies in New Type Power Devices.
Along with the development of semiconductor technology, persistently diminish to realize lower cost advantage and minimum feature, existing
In typical groove power device, the live width of groove and contact hole diminishes, and Pitch (pitch) width compresses simultaneously so that contact hole
With the spacing between gate trench narrows, if now the live width of contact hole is not accomplished sufficiently small, inclined precision cannot be met remaining
Amount requirement, and then occur the technological problems such as partially, it will the structure directly resulting in device is difficult to, and then causes Vth (threshold value
Voltage), the abnormal parameters such as BVds (drain-source breakdown voltage), Rdson even GS short circuit (grid source short circuit), form security risk.
Fig. 1 show MOSFET easy appearance under lithographic equipment limit capacity in groove power device in prior art
Problem schematic diagram.Wherein, what a-quadrant represented is the normal pattern of contact hole 4, and now contact hole 4 is in Semiconductor substrate 1 surface shape
The live width become is d1, and the spacing of the groove 5 that contact hole 4 is adjacent is respectively a1 and a2.When the width of d1 is at lithographic equipment
Time in limit of power, its contact hole 4 does not haves under-exposure, the resolution topography issues caused such as the best.When equipment alignment
Ability preferably in the case of, a1 and a2 all can meet product design to inclined margin range, a1-a2 is the smaller the better, works as a1-a2
When=0, illustrating that alignment precision is optimal, alignment ability is optimal.
B Regional Representative's is when the lithographic line width of contact hole 4 by the design of equipment limit capacity but still is unsatisfactory for predetermined
Live width design requirement, finally makes contact hole 4 will contact when having contacted upper with the grid oxygen 3 in groove 5, polysilicon 2
Abnormal pattern.The live width that now contact hole 4 is formed on Semiconductor substrate 1 surface is d2, the groove 5 that contact hole 4 is adjacent
Spacing is respectively b1 and b2.When b1 and b2 is respectively less than the pitch requirements that product allows, it may appear that Vth, BVds, Rdson etc. join
Number is abnormal, there is security risk.When b1 and b2 the most infinitely small even negative time, contact hole 4 with in groove 5
Grid oxygen 3, polysilicon 2 contact, it may appear that the abnormal parameters such as GS short circuit.This is that typical live width is bigger than normal, capacity of equipment can not meet
The failure conditions of product smaller szie processing.
C Regional Representative's is when the lithographic line width of contact hole 4 meets little linewidth requirements, but lithographic equipment alignment ability can not
Meet product structure requirement, finally make contact hole 4 not cause the structure and morphology of abnormal parameters in the centre of left and right groove 5.Now
The live width that contact hole 4 is formed on Semiconductor substrate 1 surface is d3, the spacing of the groove 5 that contact hole 4 is adjacent be respectively c1 and
C2, wherein, c1 much larger than product design to inclined margin range, c2 is again less than even the contacting inclined margin range of product design
Grid oxygen 3 in hole 4 infinite approach groove 5, polysilicon 2, the most easily occur that the parameters such as Vth, BVds, Rdson even GS short circuit are different
Often.This is that normally but alignment precision can not meet the smaller size of failure conditions of product to typical lithographic equipment live width ability.As
Fruit is in C region, c1 and c2 all then can avoid various inefficacy in product design in the range of partially.
Therefore, how under the conditions of existing lithographic equipment, less live width is realized, it is ensured that the spacing of contact hole to slot grid structure,
So that contact hole and groove set are carved with enough surpluses, thus realize the production of the device architecture of less live width, make product simultaneously
Parameter and the reliability of product meet requirement, are the contents that those skilled in the art is to be studied.
Summary of the invention
It is an object of the invention to provide a kind of groove power device and manufacture method, protect slot grid structure, at existing light
Carving under appointed condition makes slot grid structure not affected by contact hole instability technique in processing technique, it is achieved less live width and
The production of bigger alignment surplus product, makes the parameter of product and reliability meet requirement.
For solving above-mentioned technical problem, the present invention provides the manufacture method of a kind of groove power device, including:
Semiconductor substrate is provided；
Sequentially form the first trapping layer, the second trapping layer and the 3rd trapping layer on the semiconductor substrate；
Etch described 3rd trapping layer, the second trapping layer, the first trapping layer and part semiconductor substrate to form the first ditch
Groove and the second groove；
Gate dielectric layer is grown on first groove and the sidewall of the second groove and diapire described in described Semiconductor substrate；
In described first groove and the second groove, form gate material layers, remove the 3rd trapping layer, described grid material
Layer has the part higher than described second trapping layer；
Oxidation gate material layers so that described gate material layers produces the second oxygen higher than a part for described second trapping layer
Change layer, and described second oxide layer covering part the second trapping layer；
Remove the part not covered by described second oxide layer in described second trapping layer；
In described Semiconductor substrate, the first groove and the second groove both sides form p-well；
N-type region is formed in p-well described in first groove and the second groove both sides in described Semiconductor substrate；
Against the sidewall of described second oxide layer and formed by the sidewall of the second trapping layer of described second oxide layer covering
Side wall；
Form blanket dielectric layer on the semiconductor substrate；
Etching in described blanket dielectric layer extremely described Semiconductor substrate, form contact hole, described contact hole is positioned at the first ditch
In groove both sides and the second groove；And
P type island region is formed bottom described contact hole.
Optionally, for the manufacture method of described groove power device, described first trapping layer, the second trapping layer and
The material of three trapping layers is silicon dioxide, silicon nitride, silicon oxynitride, the one of polysilicon or combination.
Optionally, for the manufacture method of described groove power device, the thickness of described first trapping layer isThe thickness of described second trapping layer isThe thickness of described 3rd trapping layer is
Optionally, for the manufacture method of described groove power device, the width of described first groove is 0.05 μm-1 μ
M, the degree of depth is 0.1 μm-10 μm；The width of described second groove is 0.5 μm-5 μm, and the degree of depth is 0.1 μm-50 μm.
Optionally, for the manufacture method of described groove power device, after forming the first groove and the second groove,
Before growth gate dielectric layer, also include:
Described in described Semiconductor substrate, the first groove and the sidewall of the second groove and diapire form the first oxide layer；
Remove described first oxide layer.
Optionally, for the manufacture method of described groove power device, shape in described first groove and the second groove
After becoming gate material layers, before removing the 3rd trapping layer, also include:
Produce the gate material layers on described 3rd trapping layer surface when removing deposit, make the upper of described gate material layers
Surface and the upper surface flush of described 3rd trapping layer.
Optionally, for the manufacture method of described groove power device, wet process oxidation technology is used to form described second
Oxide layer.
Optionally, for the manufacture method of described groove power device, described second oxidated layer thickness is
Optionally, for the manufacture method of described groove power device, the described sidewall against described second oxide layer
And included by the sidewall formation side wall of the second trapping layer of described second oxide layer covering:
The 4th trapping layer is formed between described second oxide layer and the second trapping layer by described second oxide layer covering；
Return and carve described 4th trapping layer, to form described side wall.
Optionally, for the manufacture method of described groove power device, the material of described 4th trapping layer is titanium dioxide
Silicon, silicon nitride, silicon oxynitride, the one of polysilicon or combination, the thickness of described 4th trapping layer is
Optionally, for the manufacture method of described groove power device, carve for described time as using isotropic dry method to carve
Erosion.
Optionally, for the manufacture method of described groove power device, described side wall has round and smooth sidewall and presents narrow
Lower wide shape structure.
Optionally, for the manufacture method of described groove power device, described blanket dielectric layer includes covering described half
The first medium layer of conductor substrate.
Optionally, for the manufacture method of described groove power device, described blanket dielectric layer also includes that covering is described
The second dielectric layer of first medium layer.
Optionally, for the manufacture method of described groove power device, the material of described first medium layer is for undoping
Silicon dioxide, silicon nitride, silicon oxynitride one or more combination；The material of described second dielectric layer is boron-phosphorosilicate glass.
Optionally, for the manufacture method of described groove power device, described first medium layer and second dielectric layer are all
Formed by chemical vapor deposition method.
Optionally, for the manufacture method of described groove power device, the reaction source gas of described second dielectric layer is formed
Including SiH4、B2H6And/or PH3；In described second dielectric layer, the mass percent of boron is 1～5%, and the mass percent of phosphorus is 2
～6%.
Optionally, for the manufacture method of described groove power device, the thickness of described first medium layer isThe thickness of described second dielectric layer is
Optionally, for the manufacture method of described groove power device, the sidewall of described contact hole and the prolongation of diapire
Line is 80 ° of-89 ° of angles, and the degree of depth of described contact hole is less than or equal to 1 μm.
Optionally, for the manufacture method of described groove power device, bottom described contact hole formed p type island region it
After, also include:
Forming metal level in described blanket dielectric layer, described metal level fills described contact hole；And
Described metal level is formed passivation layer.
The present invention also provides for a kind of groove power device, including:
Semiconductor substrate；
The first trapping layer being positioned in described Semiconductor substrate；
It is positioned at the second trapping layer on described first trapping layer；
Run through described second trapping layer, the first trapping layer the first groove and second extending in described Semiconductor substrate
Groove；
It is positioned at the first groove described in described Semiconductor substrate and the sidewall of the second groove and the gate dielectric layer of diapire；
It is positioned at the gate material layers in described first groove and the second groove；
It is positioned at the second oxide layer in described second trapping layer and described gate material layers；
It is positioned at the first groove and the p-well of the second groove both sides in described Semiconductor substrate；
It is positioned at the N-type region in p-well described in the first groove and the second groove both sides in described Semiconductor substrate；
It is positioned on described first trapping layer, against the sidewall of described second trapping layer and the side of the sidewall of the second oxide layer
Wall；
It is positioned at the blanket dielectric layer in described Semiconductor substrate；
Contact hole, described contact hole is positioned at described first groove both sides and runs through described blanket dielectric layer, the first trapping layer also
Extend in described Semiconductor substrate, and be positioned in described second groove and extend in described gate material layers；
It is positioned at the p type island region bottom described contact hole.
Optionally, for described groove power device, the thickness of described first trapping layer isDescribed
The thickness of the second trapping layer is
Optionally, for described groove power device, the material of described first trapping layer and the second trapping layer is dioxy
SiClx, silicon nitride, silicon oxynitride, the one of polysilicon or combination.
Optionally, for described groove power device, the width of described first groove is 0.05 μm-1 μm, and the degree of depth is
0.1μm-10μm；The width of described second groove is 0.5 μm-5 μm, and the degree of depth is 0.1 μm-50 μm.
Optionally, for described groove power device, described second oxidated layer thickness is
Optionally, for described groove power device, described blanket dielectric layer includes covering described Semiconductor substrate
First medium layer.
Optionally, for described groove power device, described blanket dielectric layer also includes covering described first medium layer
Second dielectric layer.
Optionally, for described groove power device, the material of described first medium layer be plain silicon dioxide,
Silicon nitride, one or more combinations of silicon oxynitride；The material of described second dielectric layer is boron-phosphorosilicate glass.
Optionally, for described groove power device, in described second dielectric layer, the mass percent of boron is 1～5%,
The mass percent of phosphorus is 2～6%.
Optionally, for described groove power device, the thickness of described first medium layer isDescribed
The thickness of second dielectric layer is
Optionally, for described groove power device, described side wall has round and smooth sidewall and in up-narrow and down-wide shape structure.
Optionally, for described groove power device, the sidewall of described contact hole and the extended line of diapire are 80 °-89 °
Angle, the degree of depth that described contact hole is positioned in described Semiconductor substrate is less than or equal to 1 μm.
Optionally, for described groove power device, also include:
Being positioned at the metal level in described blanket dielectric layer, described metal level fills described contact hole；And
It is positioned at the passivation layer on described metal level.
Compared with prior art, a kind of groove power device of present invention offer and manufacture method, by by groove
Described gate material layers has higher than a part for the second trapping layer and this partial oxidation is formed the second oxide layer, and described
Second oxide layer covering part the second trapping layer, then by forming side wall, so that whole slot grid structure is all protected, existing
Slot grid structure is made not affected by contact hole instability technique in processing technique under the conditions of having lithographic equipment, it is achieved less line
The production of wide and bigger alignment surplus product, makes the parameter of product and reliability meet requirement.
Accompanying drawing explanation
Fig. 1 is MOSFET easy produced problem under lithographic equipment limit capacity in groove power device in prior art
Schematic diagram；
Fig. 2 is the flow chart of the groove power device manufacture method in one embodiment of the invention；
Fig. 3-12 is the structural representation in the manufacturing process of the groove power device in the embodiment of the present invention one embodiment.
Detailed description of the invention
Below in conjunction with schematic diagram, groove power device and the manufacture method of the present invention are described in more detail, wherein
Illustrate the preferred embodiments of the present invention, it should be appreciated that those skilled in the art can revise invention described herein, and still
So realize the advantageous effects of the present invention.Therefore, it is widely known that description below is appreciated that for those skilled in the art,
And it is not intended as limitation of the present invention.
Referring to the drawings the present invention the most more particularly described below in the following passage.Want according to following explanation and right
Book, advantages and features of the invention is asked to will be apparent from.It should be noted that, accompanying drawing all uses the form simplified very much and all uses non-
Ratio accurately, only in order to facilitate, to aid in illustrating lucidly the purpose of the embodiment of the present invention.
The present invention provides a kind of groove power device and manufacture method, and the manufacture method of described groove power device includes:
Step S11, offer Semiconductor substrate；
Step S12, sequentially form the first trapping layer, the second trapping layer and the 3rd trapping layer on the semiconductor substrate；
Step S13, etch described 3rd trapping layer, the second trapping layer, the first trapping layer and part semiconductor substrate with shape
Become the first groove and the second groove；
Step S14, described in described Semiconductor substrate, grow grid on the first groove and the sidewall of the second groove and diapire
Dielectric layer；
Step S15, the gate material layers that formed in described first groove and the second groove, removal the 3rd trapping layer, described
Gate material layers has the part higher than described second trapping layer；
Step S16, oxidation gate material layers so that described gate material layers is higher than the part product of described second trapping layer
Raw second oxide layer, and described second oxide layer covering part the second trapping layer；
Step S17, remove in described second trapping layer the part not covered by described second oxide layer；
Step S18, in described Semiconductor substrate, the first groove and the second groove both sides form p-well；
Step S19, in described Semiconductor substrate, in p-well described in the first groove and the second groove both sides, form N-type region；
Step S20, the sidewall against described second oxide layer and the second trapping layer by described second oxide layer covering
Sidewall forms side wall；
Step S21, form blanket dielectric layer on the semiconductor substrate；
Step S22, etch described blanket dielectric layer in described Semiconductor substrate, form contact hole, described contact hole position
In the first groove both sides and the second groove；And
Step S23, bottom described contact hole formed p type island region.
Groove power device and manufacture method incorporated by reference to-12 couples of present invention of Fig. 2 and Fig. 3 describe in detail below.
First, step S11 is performed, as shown in Figure 3, it is provided that Semiconductor substrate 20.Preferably, described Semiconductor substrate 20 can
To be silicon substrate, germanium silicon substrate, III-group Ⅴ element compound substrate or to well known to a person skilled in the art other semi-conducting materials
Substrate, uses silicon substrate in the present embodiment.Further, the silicon substrate used in the present embodiment could be formed with MOSFET
The quasiconductor such as (mos field effect transistor), IGBT (isolated-gate field effect transistor (IGFET)), Schottky diode
Device.Described Semiconductor substrate 20 can also carry out N-type and the p-type doping of certain impurity level according to the characteristic of required product.
Then, perform step S12, described Semiconductor substrate 20 is sequentially formed with first trapping layer the 21, second trapping layer
22 and the 3rd trapping layer 23.Described the first trapping layer the 21, second trapping layer 22 and the 3rd resistance formed in Semiconductor substrate 20
Only layer 23 can use the means such as oxidation or deposit to be formed.Such as, described first trapping layer the 21, second trapping layer 22 and the 3rd stops
The material of layer 23 can be one or more combinations of silicon dioxide, silicon nitride, silicon oxynitride, polysilicon etc..It is also preferred that the left it is described
The thickness of the first trapping layer isThe thickness of described second trapping layer isDescribed 3rd stops
The thickness of layer is
Then, perform step S13, etch described 3rd trapping layer the 23, second trapping layer the 22, first trapping layer 21 and part
Semiconductor substrate 20, in described 3rd trapping layer 23 of etching erosion at once to described Semiconductor substrate 20, to form the first groove 241
With the second groove 242.Refer to Fig. 4, the first groove 241 region is first window district 24a, the second groove 242 location
Territory is the second window region 24b.Described first window district 24a refers to the primitive unit cell district of power device, and the second window region 24b refers to
The termination environment of power device.
This step S13 passes through the selectively opened window of photoetching, uses photoresist to shelter, by the window region opened from upper past
After lower etching described 3rd trapping layer the 23, second trapping layer 21 to the greatest extent and the first trapping layer 21, it is further continued for going deep into etching semiconductor lining
The end 20, to form first groove 241 and second groove 242 with one fixed width and the degree of depth.Wherein, described first groove 241
Can design according to product structure with the layout of the second groove 242, the width of described first groove 241 and the second groove 242 can
Determining according to product structure and technological ability, the degree of depth can determine according to the parameter such as pressure of product.
Further, in the present embodiment, the width of the first groove 241 of formation and the second groove 242 all 0.05 μm-
Between 5 μm, the degree of depth is all between 0.1 μm-50 μm.Concrete, for the first groove 241 in first window district 24a, its width
L1 can determine according to product conducting density, and minimum feature can be more than or equal to the limit capacity of equipment, and L1 can be 0.05 μm-1 μm；
Degree of depth h1 can determine according to the parameter such as pressure of product, and h1 can be 0.1-10 μm.For second in the second window region 24b
Groove 242, it is contemplated that will fill polysilicon in its groove, width needs to meet carrying high pressure, the demand of big electric current, and therefore width is relatively
Width, part-structure also needs to arrange fairlead on the interior polysilicon filled of groove later, the therefore width L2 of the second groove 242
Relatively first groove 221 wants width, and L2 can be 0.5 μm-5 μm；In the case of wider width, according to etching load effect, identical
Etch application relatively deep to the big live width region etch degree of depth, h2 the most under normal circumstances > h1, h2 can be 0.1 μm-50 μm.Need
It is noted that and simply can not show that the first groove 241 is consistent with the second groove 242 depth width according to accompanying drawing
Conclusion.
And then, perform step S131, at a temperature of 1000 DEG C-1200 DEG C, aoxidize described in described Semiconductor substrate 20 the
One groove 241 and the sidewall of the second groove 242 and diapire form the first oxide layer (not shown), with to described first groove
241 and second groove 242 sidewall and diapire repair.The thickness range of described first oxide layer is
Then perform step S132, remove described first oxide layer.BOE corrosive liquid or DHF (the hydrogen fluorine of dilution can be used
Acid) it is removed.
Then, perform step S14, as it is shown in figure 5, in the present embodiment, first ditch described in described Semiconductor substrate 20
Grid oxygen 25 is grown on groove 241 and the sidewall of the second groove 242 and diapire.Concrete, what described grid oxygen 25 used mixes oxychloride (i.e.
Containing chlorine, oxygen atmosphere under aoxidize) formed, be 1000 DEG C-1200 DEG C in temperature range and grow, to obtain thickness model
Enclose forGrid oxygen 25.The growth temperature more high-quality of described grid oxygen 25 is the best, mixes oxychloride and can effectively reduce
Impurity in grid oxygen 25, improves the quality of grid oxygen 25.
Then, perform step S15, described first groove 241 and the second groove 242 are formed gate material layers 26, goes
Except the 3rd trapping layer, described gate material layers 26 has the part higher than described second trapping layer 22.Refer to Fig. 6, such as,
Described gate material layers 26 can be doped polysilicon layer.Can first deposit the polysilicon that undopes, rear employing ion implanting is not to
DOPOS doped polycrystalline silicon is doped；Or, first depositing the polysilicon that undopes, it is doped by rear employing phosphorus pre-deposited technique；Again
Or, use the original position doping way of depositing polysilicon limit, limit doping.
Concrete, in this step S15, to be deposited complete after, produce at described 3rd trapping layer when also needing to remove deposit
Gate material layers 26 on surface, and make gate material layers in described first groove 241 and the second groove 242 26 and described the
Three trapping layer surfaces flush, and this process can use the dry etching with isotropic to complete.Then wet method is used to carve
Erosion drift to the greatest extent the 3rd trapping layer, makes the gate material layers 26 in described first groove 241 and the second groove 242 have higher than described the
A part for two trapping layers 22, its height h3 is less than or equal to the thickness of the 3rd trapping layer in step S12.
Then, perform step S16, aoxidize gate material layers 26 so that described gate material layers 26 is higher than described second resistance
Only a part for layer 22 produces the second oxide layer 27, and described second oxide layer 27 covering part the second trapping layer 22.Such as Fig. 7 institute
Show, use wet process oxidation technology so that described gate material layers 26 produces second higher than a part for described second trapping layer 22
Oxide layer 27, concrete, the temperature of described wet oxidation is 800 DEG C-1000 DEG C, and described second oxide layer 27 is silicon oxide layer,
Thickness is
Afterwards, perform step S17, remove the portion not covered by described second oxide layer 27 in described second trapping layer 22
Point.Refer to Fig. 8, use dry etching, by unlapped for the second oxide layer 27 of being formed in step S16 second trapping layer 22 quarter
To the greatest extent, the first trapping layer 21 is exposed.
And then, perform step S18, please continue to refer to Fig. 8, first groove 241 and the in described Semiconductor substrate 20
Two groove 242 both sides form p-well 28a.Concrete, first groove 241 both sides and the second groove in described Semiconductor substrate 20
242 both sides carry out ion implanting and annealing for the first time, form p-well 28a, and the junction depth degree of depth of described p-well 28a is less than the first groove
The degree of depth of 241.Described first time ion implanting is injected with being annealed into employing boron (B) ion zero angle, and Implantation Energy is 60KeV-
150KeV, implantation dosage 1E13/cm2-1E15/cm2, annealing temperature is 1000 DEG C-1200 DEG C.
Afterwards, step S19, please continue to refer to shown in Fig. 8, first groove 241 He in described Semiconductor substrate 20 are performed
N-type region 28b is formed in p-well 28a described in second groove 242 both sides.Concrete, can be in described Semiconductor substrate 20 first
Groove 241 both sides and the second groove 242 both sides carry out second time ion implanting and annealing, form N-type region 28b, described N-type region
Junction depth degree of depth h4 of 28b is 0.1 μm-0.5 μm.Described second time ion implanting uses phosphorus (P) ion or arsenic (As) with being annealed into
Ion zero angle is injected, and Implantation Energy is 60KeV-150Kev, implantation dosage 1E14/cm2-1E16/cm2, annealing temperature 800 DEG C-
1100℃.From step S18 and the implantation dosage of step S19, the doping content of N-type region 28b of formation is more than p-well 28a
Doping content, the most described N-type region 28b is N-type heavily doped region.
Afterwards, perform step S20, against the sidewall of described second oxide layer 27 and covered by described second oxide layer 27
The sidewall of the second trapping layer 22 forms side wall 29.Refer to Fig. 9, this step S16 can specifically include:
Step S201, at the second oxide layer 27 each described and the second trapping layer 22 of being covered by described second oxide layer 27
Between formed the 4th trapping layer.Preferably, the material of described 4th trapping layer is silicon dioxide, silicon nitride, silicon oxynitride, polycrystalline
The one of silicon or combination.In preferably selecting, the thickness of described 4th trapping layer is
Step S202, returns and carves described 4th trapping layer, to form described side wall 29.Carving for described time can be that employing is every same
Property dry etching carry out, utilize etching shadow effect, it is thus achieved that there is round and smooth sidewall and the side wall 29 in up-narrow and down-wide shape structure.
As seen from Figure 9, after described step S20 completes, in the first groove 241 and the second groove 242, gate material layers 26 is revealed
The sidewall going out Semiconductor substrate 20 surface is protected by second trapping layer the 22, second oxide layer 27 and side wall 29, simultaneously top also by
Second oxide layer 27 protects.Thus, slot grid structure obtains protection, is conducive to improving the Performance And Reliability of product.
Afterwards, perform step S21, described Semiconductor substrate 20 is formed blanket dielectric layer.Refer to Figure 10, specifically
, in the present embodiment, described blanket dielectric layer includes covering described first trapping layer 21, side wall 29 and the second oxide layer 27
First medium layer 30a and cover second dielectric layer 30b of described first medium layer 30a.The material of described first medium layer 30a is
Plain silicon dioxide, silicon nitride, the one of silicon oxynitride or a combination thereof, use the techniques such as CVD to be formed.Described first medium
The thickness of layer 30a can beThe material of described second dielectric layer 30b is BPSG (boron-phosphorosilicate glass), thickness
Can beCVD technique is equally used to be formed.Concrete, the reaction of described second dielectric layer 30b
Source gas bag includes SiH4、B2H6And/or PH3Deng.Concrete, in described second dielectric layer 30b, the mass percent of B be 1～
The mass percent of 5%, P is 2～6%.
Further, it is also possible to be that described blanket dielectric layer only covers described first trapping layer 21, side wall 29 and second
The first medium layer 30a of oxide layer 27.
Further, if described first medium layer 30a uses silicon nitride, can utilize in follow-up contact hole makes
The selection of first medium layer 30a, the 3rd dielectric layer 30b and silicon, than difference, enables trench region to be protected, further existing
Realize less live width and bigger alignment surplus under the conditions of having lithographic equipment, thus realize the life of the device architecture of less live width
Produce.
Afterwards, perform step S22, etch in described blanket dielectric layer extremely described Semiconductor substrate 20, form contact hole 31,
Described contact hole 31 is positioned in the first groove 241 both sides and the second groove 242.Refer to Figure 11, the contact hole 31 etched is big
Causing to be inverted trapezoidal, i.e. shape with wide top and narrow bottom, the width bottom contact hole 31 is L5, and open top width is L4, L5 < L4, thus real
The filling producing dielectric layer of the device architecture of the least live width.Wherein, the sidewall of described contact hole 31 and diapire extended line
Angle theta be 80 °～89 °, described contact hole 31 is positioned in described Semiconductor substrate 20 degree of depth h5 less than or equal to 1 μm.In contact
After hole 31 is formed, form the 3rd window region 31a in primitive unit cell district, form the 4th window region 31b in termination environment.
After this step S22 is specially sequentially etched second dielectric layer 30b, first medium layer 30a and the first trapping layer 21, continue
Continuous etch semiconductor substrates 20, it is thus achieved that the step of certain depth, thus the Semiconductor substrate being doping to N-type is etched away one
Part, makes follow-up p-type inject and can penetrate N-type region.It is understood that the portion of side wall 29 can also be etched away when etching
Partial width.
Concrete, the region having contact hole 31 in described 3rd window region 31a is the source region between groove and groove, as primitive unit cell
The source in district connects metal；Described 4th window region 31b has the region of contact hole 31 as the pressure ring of device or grid
(Gate-PAD) end connects metal.
More specifically, in conjunction with Fig. 1, Fig. 3 and Figure 11, the second dielectric layer 30b top width of primitive unit cell district shown in Figure 11 is L3,
Its width, more than the width L1 of the first groove 241 in Fig. 3, can make the top of the first groove 241 be protected by dielectric layer, no
Easily produce the problems such as GS electric leakage.
More specifically, in primitive unit cell district shown in Figure 11, contact hole 31 open top width is L4, and generally this width represents
The Limit Width of contact hole 31 photoetching.
Further, perform step S23, please continue to refer to Figure 11, bottom described contact hole 31, form p type island region 31c.Tool
Body, carry out third time ion implanting and annealing, (P+ district, relative p-well 28a has bigger doping dense to form described p type island region
Degree) 31c.Described third time ion implanting injects B11 or BF for using zero angle2, can first inject B11 and reinject BF2, inject
Energy is 20KeV-100KeV, and implantation dosage is 1E14/cm2-1E16/cm2；Use boiler tube or short annealing at 500 DEG C-1000
Anneal at DEG C.From step S18 and the implantation dosage of step S23, the doping content of the p type island region 31c of formation is more than p-well
The doping content of 28a, the most described p type island region 31c is p-type heavily doped region.
Further, perform step S24, refer to Figure 12, above-mentioned blanket dielectric layer is formed metal level 32, described gold
Belong to layer 32 and fill described contact hole 31.Concrete, the material of described metal level 32 can be titanium (Ti), titanium nitride (TiN), silication
The metals such as titanium (TiSi), tungsten (W), aluminum (Al), silicated aluminum (AlSi), copper silmin (AlSiCu), copper (Cu) or nickel (Ni) or
The compound of metal, its thickness can be 1 μm-8 μm.After metal level 32 is formed, perform a step etching technics, for example with dry
Method etches, it is thus achieved that the 5th window region 32a and the 6th window region 32b of termination environment in primitive unit cell district.
Further, it is also possible to according to product need increase passivation layer protection, complete the processing of device Facad structure, and
Final device architecture is completed through a series of postchannel process such as thinning, the back of the body gold, scribings.
Visible in conjunction with Fig. 3-Figure 12, that the present invention obtains groove power device, including:
Semiconductor substrate 20；
The first trapping layer 21 being positioned in described Semiconductor substrate 20；
It is positioned at the second trapping layer 22 on described first trapping layer 21；It is also preferred that the left the thickness of described first trapping layer 21 isThe thickness of described second trapping layer 22 isDescribed first trapping layer 21 and the second trapping layer
The material of 22 is silicon dioxide, silicon nitride, silicon oxynitride, the one of polysilicon or combination；
Run through described second trapping layer the 22, first trapping layer 21 and extend to the first groove in described Semiconductor substrate 20
241 and second groove 242；It is also preferred that the left the width of described first groove 241 is 0.05 μm-1 μm, the degree of depth is 0.1 μm-10 μm；Institute
The width stating the second groove 242 is 0.5 μm-5 μm, and the degree of depth is 0.1 μm-50 μm；
It is positioned at the grid on the first groove 241 described in described Semiconductor substrate 20 and the sidewall of the second groove 242 and diapire
Oxygen 25；The thickness of described grid oxygen 25 is
It is positioned at the gate material layers 26 in described first groove 241 and the second groove 242；
It is positioned at the second oxide layer 27 in described second trapping layer 22 and described gate material layers 26, it is also preferred that the left described
Dioxide layer thickness is
It is positioned at the first groove 241 and p-well 28a of the second groove 242 both sides in described Semiconductor substrate 20；
It is positioned at the N-type region in p-well 28a described in the first groove 241 and the second groove 242 both sides in described Semiconductor substrate 20
28b；The junction depth degree of depth of described N-type region 28b is less than the degree of depth of described p-well 28a, and such as, the junction depth degree of depth of described N-type region 28b is
0.1μm-0.5μm；
It is positioned on described first trapping layer 21, against the sidewall of described second trapping layer 22 and the sidewall of the second oxide layer 27
Side wall 29, described side wall 29 has round and smooth sidewall and in up-narrow and down-wide shape structure；
Being positioned at the blanket dielectric layer in described side wall 29 and the second oxide layer 27, described blanket dielectric layer includes that covering is described
First trapping layer 21, side wall 29 and the first medium layer 30a of the second oxide layer 27 and cover the second of described first medium layer 30a
Dielectric layer 30b；The material of described first medium layer 30a be plain silicon dioxide, silicon nitride, the one of silicon oxynitride or its
Combination, the material of described second dielectric layer 30b is boron-phosphorosilicate glass, and in described second dielectric layer 30b, the mass percent of boron is 1
～5%, the mass percent of phosphorus is 2～6%, it is also preferred that the left the thickness of described first medium layer 30a isInstitute
The thickness stating second dielectric layer 30b isCertainly, described blanket dielectric layer can also be only second medium
Layer 29a；
Contact hole 31, described contact hole 31 is positioned at described first groove 241 both sides and runs through described blanket dielectric layer, the first resistance
Only layer 21 extending in described Semiconductor substrate 20, and be positioned in described second groove 242 and extend to described grid material
In layer 26, described contact hole 31 is in shape with wide top and narrow bottom, and the described sidewall of contact hole 31 and the extended line of diapire are 80 ° of-89 ° of angles,
The degree of depth that described contact hole 31 is positioned in described Semiconductor substrate 20 is less than or equal to 1 μm；
It is positioned at the p type island region 31c bottom described contact hole 31；
The metal level 32 being positioned in described blanket dielectric layer, described metal level 32 fills described contact hole 31；It is also preferred that the left institute
State the material of metal level 32 be titanium (Ti), titanium nitride (TiN), titanium silicide (TiSi), tungsten (W), aluminum (Al), silicated aluminum (AlSi),
Metal or the compounds of metal such as copper silmin (AlSiCu), copper (Cu) or nickel (Ni)；And
It is positioned at the passivation layer on described metal level 32.
Thus, a kind of groove power device of present invention offer and manufacture method, by by the described grid material in groove
The bed of material has higher than a part for the second trapping layer and this partial oxidation produces the second oxide layer, and described second oxide layer
Covering part the second trapping layer, then by forming side wall, so that whole slot grid structure is all protected, at existing lithographic equipment
Under the conditions of make slot grid structure not affected by contact hole instability technique in processing technique, it is achieved less live width and bigger
The production of alignment surplus product, makes the parameter of product and reliability meet requirement.
Further, a kind of trench power device structure of the present invention and manufacture method, can be used in and include but do not limit
In the products such as CMOS, BCD, power MOSFET, high power transistor, IGBT and Schottky.
Obviously, those skilled in the art can carry out various change and the modification essence without deviating from the present invention to the present invention
God and scope.So, if these amendments of the present invention and modification belong to the scope of the claims in the present invention and equivalent technologies thereof
Within, then the present invention is also intended to comprise these change and modification.
Claims (33)
1. a manufacture method for groove power device, including:
Semiconductor substrate is provided；
Sequentially form the first trapping layer, the second trapping layer and the 3rd trapping layer on the semiconductor substrate；
Etch described 3rd trapping layer, the second trapping layer, the first trapping layer and part semiconductor substrate with formed the first groove and
Second groove；
Gate dielectric layer is grown on first groove and the sidewall of the second groove and diapire described in described Semiconductor substrate；
Forming gate material layers in described first groove and the second groove, remove the 3rd trapping layer, described gate material layers has
There is the part higher than described second trapping layer；
Oxidation gate material layers so that described gate material layers produces the second oxidation higher than a part for described second trapping layer
Layer, and described second oxide layer covering part the second trapping layer；
Remove the part not covered by described second oxide layer in described second trapping layer；
In described Semiconductor substrate, the first groove and the second groove both sides form p-well；
N-type region is formed in p-well described in first groove and the second groove both sides in described Semiconductor substrate；
Against the sidewall of described second oxide layer and formed side wall by the sidewall of the second trapping layer of described second oxide layer covering；
Form blanket dielectric layer on the semiconductor substrate；
Etching in described blanket dielectric layer extremely described Semiconductor substrate, form contact hole, described contact hole is positioned at the first groove two
In side and the second groove；And
P type island region is formed bottom described contact hole.
2. the manufacture method of groove power device as claimed in claim 1, it is characterised in that described first trapping layer, second
The material of trapping layer and the 3rd trapping layer is silicon dioxide, silicon nitride, silicon oxynitride, the one of polysilicon or combination.
3. the manufacture method of groove power device as claimed in claim 1 or 2, it is characterised in that described first trapping layer
Thickness isThe thickness of described second trapping layer isThe thickness of described 3rd trapping layer is
4. the manufacture method of groove power device as claimed in claim 3, it is characterised in that the width of described first groove is
0.05 μm-1 μm, the degree of depth is 0.1 μm-10 μm；The width of described second groove is 0.5 μm-5 μm, and the degree of depth is 0.1 μm-50 μm.
5. the manufacture method of groove power device as claimed in claim 1, it is characterised in that forming the first groove and second
After groove, before growth gate dielectric layer, also include:
Described in described Semiconductor substrate, the first groove and the sidewall of the second groove and diapire form the first oxide layer；
Remove described first oxide layer.
6. the manufacture method of groove power device as claimed in claim 1, it is characterised in that at described first groove and second
After groove forms gate material layers, before removing the 3rd trapping layer, also include:
Produce the gate material layers on described 3rd trapping layer surface when removing deposit, make the upper surface of described gate material layers
Upper surface flush with described 3rd trapping layer.
7. the manufacture method of groove power device as claimed in claim 1, it is characterised in that use wet process oxidation technology to be formed
Described second oxide layer.
8. the manufacture method of groove power device as claimed in claim 1, it is characterised in that described second oxidated layer thickness is
9. the manufacture method of groove power device as claimed in claim 1, it is characterised in that described against described second oxidation
Layer sidewall and by described second oxide layer cover the second trapping layer sidewall formed side wall include:
The 4th trapping layer is formed between described second oxide layer and the second trapping layer by described second oxide layer covering；
Return and carve described 4th trapping layer, to form described side wall.
10. the manufacture method of groove power device as claimed in claim 9, it is characterised in that the material of described 4th trapping layer
Material is silicon dioxide, silicon nitride, silicon oxynitride, the one of polysilicon or combination, and the thickness of described 4th trapping layer is
The manufacture method of 11. groove power devices as claimed in claim 9, it is characterised in that carve for described time as using every
Same sex dry etching.
The manufacture method of 12. groove power devices as claimed in claim 9, it is characterised in that described side wall has round and smooth side
Wall and in up-narrow and down-wide shape structure.
The manufacture method of 13. groove power devices as claimed in claim 1, it is characterised in that described blanket dielectric layer includes
Cover the first medium layer of described Semiconductor substrate.
The manufacture method of 14. groove power devices as claimed in claim 13, it is characterised in that described blanket dielectric layer is also wrapped
Include the second dielectric layer covering described first medium layer.
The manufacture method of 15. groove power devices as claimed in claim 14, it is characterised in that the material of described first medium layer
Material is plain silicon dioxide, one or more combinations of silicon nitride, silicon oxynitride；The material of described second dielectric layer is boron
Phosphorosilicate glass.
The manufacture method of 16. groove power devices as claimed in claim 10, it is characterised in that described first medium layer and
Second medium layer is all formed by chemical vapor deposition method.
The manufacture method of 17. groove power devices as claimed in claim 12, it is characterised in that form described second dielectric layer
Reaction source gas include SiH4、B2H6And/or PH3；In described second dielectric layer, the mass percent of boron is 1～5%, the matter of phosphorus
Amount percentage ratio is 2～6%.
The manufacture method of 18. groove power devices as claimed in claim 10, it is characterised in that the thickness of described first medium layer
Degree isThe thickness of described second dielectric layer is
The manufacture method of 19. groove power devices as claimed in claim 1, it is characterised in that the sidewall of described contact hole with
The extended line of diapire is 80 ° of-89 ° of angles, and the degree of depth of described contact hole is less than or equal to 1 μm.
The manufacture method of 20. groove power devices as claimed in claim 1, it is characterised in that shape bottom described contact hole
After becoming p type island region, also include:
Forming metal level in described blanket dielectric layer, described metal level fills described contact hole；And
Described metal level is formed passivation layer.
21. 1 kinds of groove power devices, including:
Semiconductor substrate；
The first trapping layer being positioned in described Semiconductor substrate；
It is positioned at the second trapping layer on described first trapping layer；
Run through described second trapping layer, the first trapping layer the first groove extending in described Semiconductor substrate and the second ditch
Groove；
It is positioned at the first groove described in described Semiconductor substrate and the sidewall of the second groove and the gate dielectric layer of diapire；
It is positioned at the gate material layers in described first groove and the second groove；
It is positioned at the second oxide layer in described second trapping layer and described gate material layers；
It is positioned at the first groove and the p-well of the second groove both sides in described Semiconductor substrate；
It is positioned at the N-type region in p-well described in the first groove and the second groove both sides in described Semiconductor substrate；
It is positioned on described first trapping layer, against the sidewall of described second trapping layer and the side wall of the sidewall of the second oxide layer；
It is positioned at the blanket dielectric layer in described Semiconductor substrate；
Contact hole, described contact hole is positioned at described first groove both sides to be run through described blanket dielectric layer, the first trapping layer and extends
To in described Semiconductor substrate, and it is positioned in described second groove and extends in described gate material layers；
It is positioned at the p type island region bottom described contact hole.
22. groove power devices as claimed in claim 21, it is characterised in that the thickness of described first trapping layer isThe thickness of described second trapping layer is
23. groove power devices as claimed in claim 21, it is characterised in that described first trapping layer and the second trapping layer
Material is silicon dioxide, silicon nitride, silicon oxynitride, the one of polysilicon or combination.
24. groove power devices as claimed in claim 21, it is characterised in that the width of described first groove is 0.05 μm-1
μm, the degree of depth is 0.1 μm-10 μm；The width of described second groove is 0.5 μm-5 μm, and the degree of depth is 0.1 μm-50 μm.
25. groove power devices as claimed in claim 21, it is characterised in that described second oxidated layer thickness is
26. groove power devices as claimed in claim 21, it is characterised in that described blanket dielectric layer includes covering described half
The first medium layer of conductor substrate.
27. groove power devices as claimed in claim 26, it is characterised in that described blanket dielectric layer also includes that covering is described
The second dielectric layer of first medium layer.
28. groove power devices as claimed in claim 27, it is characterised in that the material of described first medium layer is for undoping
Silicon dioxide, silicon nitride, silicon oxynitride one or more combination；The material of described second dielectric layer is boron-phosphorosilicate glass.
29. groove power devices as claimed in claim 27, it is characterised in that the percent mass of boron in described second dielectric layer
Ratio is 1～5%, and the mass percent of phosphorus is 2～6%.
30. groove power devices as claimed in claim 27, it is characterised in that the thickness of described first medium layer isThe thickness of described second dielectric layer is
31. groove power devices as claimed in claim 21, it is characterised in that described side wall has round and smooth sidewall and presents narrow
Lower wide shape structure.
32. groove power devices as claimed in claim 21, it is characterised in that the sidewall of described contact hole and the prolongation of diapire
Line is 80 ° of-89 ° of angles, and the degree of depth that described contact hole is positioned in described Semiconductor substrate is less than or equal to 1 μm.
33. groove power devices as claimed in claim 21, it is characterised in that also include:
Being positioned at the metal level in described blanket dielectric layer, described metal level fills described contact hole；And
It is positioned at the passivation layer on described metal level.
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| Publication number | Priority date | Publication date | Assignee | Title |
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