CN106104796B - 具有改进热性能的堆叠式半导体裸片组合件及相关的***及方法 - Google Patents

具有改进热性能的堆叠式半导体裸片组合件及相关的***及方法 Download PDF

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CN106104796B
CN106104796B CN201580012756.0A CN201580012756A CN106104796B CN 106104796 B CN106104796 B CN 106104796B CN 201580012756 A CN201580012756 A CN 201580012756A CN 106104796 B CN106104796 B CN 106104796B
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insert
bare chip
semiconductor bare
die
package substrate
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CN106104796A (zh
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迈克尔·科普曼斯
罗时剑
戴维·R·亨布里
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Micron Technology Inc
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Micron Technology Inc
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本文揭示具有改进热性能的堆叠式半导体裸片组合件及相关的***及方法。在一个实施例中，半导体裸片组合件可包含半导体裸片堆叠及导热外壳，所述导热外壳将所述半导体裸片堆叠至少部分封围于壳体内。封装衬底承载所述导热外壳，且***物安置于所述导热外壳与所述半导体裸片堆叠之间。所述***物的***部分侧向延伸超过所述半导体裸片堆叠且耦合到***于所述***部分与所述封装衬底之间的多个传导构件。

Description

具有改进热性能的堆叠式半导体裸片组合件及相关的***及 方法
技术领域
所揭示的实施例涉及半导体裸片组合件及管理此类组合件内的热量。特定来说，本技术涉及具有导热外壳及直接附接到外壳的***物的堆叠式半导体装置组合件。
背景技术
封装式半导体裸片(包含存储器芯片、微处理器芯片及成像器芯片)通常包含安装于衬底上且围封于塑料保护罩中的半导体裸片。裸片包含功能特征(例如存储器单元、处理器电路及成像器装置)，以及电连接到功能特征的接合垫。接合垫可经电连接到保护罩外侧的端子以允许裸片连接到更高阶的电路。
半导体制造者不断减小裸片封装的大小以装配于电子装置的空间约束内，同时也增大每一封装的功能能力以满足操作参数。一种用于增大半导体封装的处理能力而大体上不增大由封装覆盖的表面积(即，封装的“占用面积”)的方法是在单个封装中在彼此顶部上竖直堆叠多个半导体裸片。在此类竖直堆叠式封装中的裸片可通过使用穿硅通孔(TSV)将个别裸片的接合垫与相邻裸片的接合垫电耦合而互连。
在竖直堆叠式封装中，所产生的热量难以耗散，这增大了个别裸片、其间的结及封装作为一个整体的操作温度。在许多类型的装置中，这可使堆叠式裸片达到超过其最大操作温度(Tmax)的温度。
附图说明
图1到5是根据本技术的选定实施例配置的半导体裸片组合件的横截面图。
图6是包含根据本技术的实施例配置的半导体裸片组合件的***的示意图。
具体实施方式
下文描述具有改进的热性能的堆叠式半导体裸片组合件及相关的***及方法的若干实施例的特定细节。术语“半导体裸片”一般是指具有集成电路或组件、数据存储元件、处理组件及/或在半导体衬底上制造的其它特征的裸片。举例来说，半导体裸片可包含集成电路存储器及/或逻辑电路。相关领域的技术人员还将理解，本技术可具有额外实施例，且可在无下文参考图1到6描述的实施例的若干细节的情况下实践本技术。
如本文使用，鉴于图中展示的定向，术语“竖直”、“侧向”、“上部”及“下部”可指代半导体裸片组合件中的特征的相对方向或位置。举例来说，“上部”或“最上部”可指代经定位比另一特征更靠近页的顶部的特征。然而，这些术语应广义地解释为包含具有其它定向的半导体装置。
图1是根据本技术的实施例配置的半导体裸片组合件100(“组合件100”)的横截面图。组合件100包含经布置于堆叠105(“裸片堆叠105”)中的多个半导体裸片102及导热外壳(“外壳110”)，所述外壳附接到***于外壳110与裸片堆叠105之间的***物120。***物120包含***部分122，***部分122沿至少一个轴线侧向延伸超越裸片堆叠105的***或占用面积。***部分122包含多个接合垫123，其通过经***于***部分122与封装衬底130之间的个别传导构件(例如焊料凸块140)耦合到封装衬底130的对应接合垫132。封装衬底130可包含(例如)***物、印刷电路板或具有将组合件100连接到外部电路(未展示)的电连接器133(例如，焊料凸块)的其它适当衬底。
在图1的所说明的实施例中，焊料凸块140可包含金属焊料球。在若干实施例中，焊料凸块140可具有等于或大于裸片堆叠105的竖直高度的竖直高度。举例来说，取决于裸片堆叠105的竖直高度，焊料凸块140可具有在从约200μm到约1mm或更多的范围中的竖直高度。焊料凸块的间距也可基于焊料凸块的竖直高度而变化。此外，虽然焊料凸块140在所说明的实施例中展示为具有小于其竖直高度的间距，但在其它实施例中，间距可等于或大于竖直高度。
外壳110包含盖部分112及附接到盖部分112或与其一体形成的壁部分113。盖部分112可通过第一界面材料115a(例如，粘合剂)附接到***物120的背侧表面121。壁部分113竖直延伸远离盖部分112，且通过第二界面材料115b(例如，粘合剂)附接到封装衬底130的***或上表面135。在所说明的实施例中，外壳110至少部分将裸片堆叠105封围于壳体(例如，腔室)内。在其它实施例中，外壳110可以不同方式配置或省略。举例来说，在一个实施例中，壁部分113可从外壳110省略。除提供保护罩之外，外壳110也可作为吸收热能且将其从裸片堆叠105耗散开的散热器。因此，外壳110可由导热材料制成，例如具有高导热率的镍、铜、铝、陶瓷材料(例如，氮化铝)及/或其它适当导热材料。
在一些实施例中，第一界面材料115a及/或第二界面材料115b可由此项技术中称为“热界面材料”或“TIM”的材料制成，“热界面材料”经设计以增大表面结处(例如，在裸片表面与散热器之间)的热传导。TIM可包含用传导材料(例如碳纳米管、焊料材料、类金刚石碳(DLC)等等)、以及相变材料掺杂的硅基脂、凝胶或粘合剂。在一些实施例中，举例来说，热界面材料可由亚利桑那州菲尼克斯市的信越化工公司(Shin-Etsu MicroSi,Inc.ofPhoenix,Arizona)所制造的X-23-7772-4TIM制成，X-23-7772-4TIM具有约3到4W/m°K的导热率。在其它实施例中，第一界面材料115a及/或第二界面材料115b可包含其它适当材料，例如金属(例如，铜)及/或其它适当导热材料。
在若干实施例中，裸片堆叠105可通过第三界面材料115c(例如粘合剂、裸片附接材料(例如，裸片附接膜或膏)、电介质间隔件或其它适当材料)附接到封装衬底130。在一个实施例中，第三界面材料115c是将裸片堆叠105与堆叠105下方的封装衬底130电隔离的电介质材料。在另一实施例中，第三界面材料115c可包含用于第一界面材料115a及/或第二界面材料115b的界面材料(例如，TIM)。在其它实施例中，可省略第三界面材料115c。举例来说，在一个实施例中，***物120可将裸片堆叠105承载在封装衬底130上方，使得裸片堆叠105与封装衬底130由间隙(例如，空气间隙)分离。
裸片堆叠105可电耦合到***物120，且通过多个互连件106(例如，铜柱、焊料凸块及/或其它传导特征)彼此电耦合。举例来说，互连件106的部分可附接到定位于***物120的有效表面124处的对应接合垫125。半导体裸片102中的每一者可包含在互连件106的相对侧上耦合的多个贯穿衬底互连件108(例如，贯穿衬底通孔、TSV等等)。互连件及贯穿衬底互连件106及108可由各种类型的传导材料(例如，金属材料)形成，例如铜、镍、铝等等。在一些实施例中，传导材料可包含焊料(例如，基于SnAg的焊料)、充填导体的环氧树脂及/或其它导电材料。在选定实施例中，举例来说，互连件106可为铜柱，而在其它实施例中，互连件106可包含更复杂的结构，例如氮化物上凸块结构。在其它实施例中，互连件106可用其它类型的材料或结构替换，例如传导性膏。
除电连通之外，互连件106及贯穿衬底互连件108也将热量从裸片堆叠105朝向外壳110传递。在一些实施例中，裸片堆叠105的最外裸片104的贯穿衬底互连件108也可将热量从裸片堆叠105传递到封装衬底130。举例来说，贯穿衬底互连件108可与第三界面材料115c直接接触。在若干实施例中，组合件100也可包含在半导体裸片102之间以填隙方式定位的多个导热元件或“虚设元件”(未展示)以进一步促进穿过裸片堆叠105的热传递。此类虚设元件可具有至少大体与互连件106及/或贯穿衬底互连件108相似的结构及组成，除所述虚设元件并不电耦合到半导体裸片102的其它电路外。
底部填充材料117可经沉积(或以其它方式形成)于裸片堆叠105的半导体裸片102中的一些或全部裸片周围及/或之间以将互连件106彼此电隔离及/或增强半导体裸片102之间的机械连接。底部填充材料117可为非传导性环氧树脂膏(例如，由日本新泻的纳美仕公司(Namics Corporation of Niigata,Japan)制造的XS8448-171)、毛细管底部填充物、非传导性膜、经模制底部填充物及/或包含其它适当电绝缘材料。在一些实施例中，可基于底部填充材料117的导热率来选择底部填充材料117以增强贯穿裸片堆叠105的热耗散。
半导体裸片102可各自由半导体衬底形成，例如硅、绝缘体上硅、复合半导体(例如，氮化镓)或其它适当衬底。半导体衬底可经切割或单粒化为具有各种电路组件或功能特征(例如动态随机存取存储器(DRAM)、静态随机存取存储器(SRAM)、快闪存储器、其它形式的集成电路装置(包含存储器、处理电路、成像组件)及/或其它半导体装置)中的任何者的半导体裸片。在选定实施例中，组合件100可经配置为混合存储器立方体(HMC)，其中一些半导体裸片102提供数据存储(例如，DRAM裸片)且半导体裸片102中的至少一者提供HMC内的存储器控制(例如，DRAM控制)。在一些实施例中，半导体裸片102可包含除数据存储及/或存储器控制组件外及/或不同于所述组件的其它电路组件。此外，尽管在图1中展示的裸片堆叠105包含五个裸片，但在其它实施例中，堆叠105可包含少于五个裸片(例如，三个裸片)或五个以上裸片(例如，八个裸片、十个裸片、十二个裸片等等)。举例来说，在一个实施例中，裸片堆叠105可包含九个裸片而非五个裸片。
***物120可包含印刷电路板、半导体衬底或经形成为不具有集成电路组件的其它适当衬底。举例来说，***物120可包含由结晶、半结晶及/或陶瓷衬底材料(例如硅、多晶硅、氧化铝(Al2O3)、蓝宝石及/或其它适当材料)形成的“空白”衬底。在此实施例的一个方面中，***物120可在不具有贯穿衬底互连件的情况下形成，这是因为***物120是朝向组合件100的顶部而非朝向组合件的底部安置。举例来说，常规半导体裸片封装具有安置于封装衬底与半导体裸片堆叠之间的***物。此布置需要***物具有贯穿衬底互连件以将封装衬底与半导体裸片堆叠电连接。此布置也需要***物为薄的以减少贯穿衬底互连件的竖直高度及纵横比。举例来说，常规***物(或用来形成***物的衬底)可通过背面研磨、蚀刻及/或化学机械抛光(CMP)薄化到适当大小。因此，***物120定位成朝向组合件的顶部的一个优点在于***物120可是相对厚的，且因此消除数个制造步骤。举例来说，可消除用于形成贯穿衬底互连件的衬底薄化、穿孔蚀刻及金属沉积过程。另一优点在于***物120所增大的厚度可促进热量远离裸片堆叠105且朝向***物的***部分122侧向传递。
图2是根据本技术的另一实施例配置的半导体裸片组合件200(“组合件200”)的横截面图。组合件200可包含大体类似于组合件100的特征的特征。举例来说，组合件200包含封围于外壳110内且附接到半导体裸片堆叠205(“裸片堆叠205”)的***物120。在图2的所说明实施例中，裸片堆叠205包含***于多个存储器裸片202b之间的逻辑裸片202a。逻辑裸片202a可包含(例如)存储器控制器、串行化器/解串行化器电路及/或其它集成电路组合件。个别存储器裸片202b可包含(例如)经由互连件106及贯穿衬底互连件108可操作地耦合到逻辑裸片202a的集成电路组件的存储器单元的阵列或块。
在此实施例的一个方面中，在逻辑裸片202a与外壳110之间的***物120的布置可减小操作期间由裸片堆叠205产生的热量的量。一般来说，由逻辑裸片(例如，逻辑裸片202a)产生的热量可明显大于由存储器裸片(例如，存储器裸片202b)共同产生的热量。例如，HMC组合件中的逻辑裸片可消耗操作期间的总电力的80％。在常规半导体裸片组合件中，在***物朝向组合件的底部的情况下定位逻辑裸片。因而，来自逻辑裸片的热量在到组合件的外壳途中传递穿过存储器裸片，这增大了组合件的总体温度。随着温度接近或增大超过最大操作温度(Tmax)，组合件的操作性能下降。举例来说，通常需要降低(例如，逻辑裸片的)处理速度以将操作维持在于可接受温度下。在一些例子中，举例来说，需要将数据输送量处理量减少到最大输送量处理量水平的四分之一，使得组合件保持在Tmax或低于Tmax。相反，根据本技术的若干实施例配置的HMC及其它裸片组合件可减小穿过存储器裸片202b的热量流。特定来说，***物120将逻辑裸片202a定位成靠近外壳110以引导热量流远离存储器裸片202b。这又可使逻辑裸片202a及存储器裸片202b能够在低于Tmax温度下操作，且因此以更快速度且以更多数据处理量操作。
在图2的所说明实施例中，沿至少一个轴线，逻辑裸片202a的占用面积大于个别存储器裸片202b。在此实施例的一个方面中，逻辑裸片202a的特定集成电路组件可经形成朝向逻辑裸片202a的外部分201，外部分201在逻辑裸片202a与存储器裸片202b之间的结209***。举例来说，具有较高操作温度的电路(例如，串行化器/解串行化器电路)可经形成为朝向外部分201。在这些电路经定位朝向外部分201的情况下，结209传递更少热量，且因此裸片堆叠205可以更低操作温度操作。
图3是根据本技术的另一实施例配置的半导体裸片组合件300(“组合件300”)的横截面图。组合件300可包含大体类似于组合件100的特征的特征。举例来说，组合件300包含封围于外壳110内且附接到裸片堆叠105的***物120。在图3的所说明实施例中，组合件300包含安置于凸起接合垫323与332之间的传导构件(或焊料凸块440)。在若干实施例中，接合垫323及/或接合垫332的高度可经配置以容纳具有各种大小及/或间距的焊料凸块。另外或替代地，接合垫323及/或332的高度可经选择以容纳各种高度的裸片堆叠105。此外，在一些实施例中，可仅使一组接合垫323及332凸起。
如在图3中进一步展示，***物120包含(例如)传导迹线、接合垫及/或在接合垫323与125之间电耦合的其它适当传导结构的再分布网络327。如所展示，再分布网络327可包含在接合垫323与125之间耦合的一或多个电路元件329(示意性展示)。在若干实施例中，电路元件329可包含电容器、电阻器及/或其它适当电路元件。举例来说，电路元件329可包含经配置以调节通过电力供应器(未展示)提供到裸片堆叠105的电压或电力的大面积金属电容器及/或电感器。
图4是根据本技术的另一实施例配置的半导体裸片组合件400(“组合件400”)的横截面图。组合件400可包含大体类似于图1的组合件100的特征的特征。举例来说，组合件400包含封围于外壳110内的***物120，***物120经耦合到***于***部分122与封装衬底130之间的传导结构440。在图4的所说明实施例中，传导结构440中的每一者可包含在封装衬底130的接合垫132与中间支撑件445上的对应接合垫444之间耦合的第一焊料凸块442a。中间支撑件445可包含将接合垫444电耦合到中间支撑件445的相对侧上的对应接合垫446的贯穿衬底互连件448。接合垫446可又通过第二焊料凸块442b耦合到***物120的接合垫123。
在此实施例的一个方面中，中间支撑件445可相对于焊料凸块140(图1)的高度减小第一焊料凸块442a及第二焊料凸块442b的高度。在一些实施例中，第一焊料凸块442a及第二焊料凸块442b可为更小，且传导结构440可包含额外水平的中间支撑件及焊料凸块以进一步减小焊料凸块的高度。举例来说，在一些实施例中，传导结构可包含两个或两个以上中间支撑件，其中焊料凸块安置于中间支撑件中的每一者之间。在若干实施例中，中间支撑件445可包含至少部分围绕裸片堆叠105的***的单一结构。举例来说，中间支撑件445可包含具有接纳裸片堆叠105的开口的图案化***物。在另一实施例中，中间支撑件445可包含金属框。在其它实施例中，中间支撑件445可包含在一对焊料凸块之间或在多对焊料凸块之间的离散元件。
图5是根据本技术的另一实施例配置的半导体裸片组合件500(“组合件500”)的横截面图。组合件500可包含大体类似于图1的组合件100的特征的特征。举例来说，组合件500包含封围于外壳110内且附接到封装衬底530的***物120。在图5的所说明实施例中，封装衬底530包含腔室537，腔室537具有凹入于封装衬底530的上表面135下方且通过第三界面材料115c附接到裸片堆叠105的凹入表面539。***物120经耦合到定位于腔室537外侧的在***物120的接合垫523与封装衬底530的对应接合垫532之间的多个焊料凸块540。在若干实施例中，焊料凸块540可类似于图1的焊料凸块140，但具有更小的竖直高度及/或间距。
在若干实施例中，组合件500的竖直轮廓(例如，高度)小于上文参考图1到4分别详细描述的组合件100到400的竖直轮廓。在各种实施例中，组合件500的竖直轮廓可部分由腔室537的深度及/或腔室537内的裸片堆叠105的竖直高度决定。尽管在图5中展示的裸片堆叠105完全安置于腔室537内，但在其它实施例中，裸片堆叠105的部分可至少部分延伸于腔室537外侧(例如，当裸片堆叠105具有大于腔室537的深度的高度时)。在一个实施例中，逻辑裸片(未展示)可经承载于腔室537外侧，而存储器裸片(未展示)可保持于腔室537内。此外，在一些实施例中，腔室外侧的焊料凸块540可具有与互连件106的在***物120与裸片堆叠105之间的部分相同的高度，而在其它实施例中，焊料凸块540可具有不同于互连件106的此部分的高度(例如，更大的高度)。
上文参考图1到5描述的堆叠式半导体裸片组合件中的任一者可并入大量更大及/或更复杂***中的任何者，所述***的代表性实例是图6中示意性展示的***670。***670可包含半导体裸片组合件600、电源672、驱动器674、处理器676及/或其它子***或组件678。半导体裸片组合件600可包含大体类似于上文描述的堆叠式半导体裸片组合件的特征的特征，且因此可包含增强热量耗散的各种特征。所得***670可执行多种多样的功能(例如存储器存储、数据处理及/或其它适当功能)中的任何者。因此，代表性***670可包含(但不限于)手持式装置(例如，移动电话、平板计算机、数字阅读器及数字音频播放器)、计算机及电器。***670的组件可装纳于单个单元中或分布于多个互连的单元上(例如，通过通信网络)。***670的组件也可包含远程装置及多种多样的计算机可读媒体中的任何者。
根据上文将了解，在本文中已出于说明的目的描述本技术的特定实施例，但可在不脱离本发明的情况下做出各种修改。举例来说，尽管关于HMC描述半导体裸片组合件的许多实施例，但在其它实施例中，半导体裸片组合件可经配置为其它存储器装置或其它类型的堆叠式裸片组合件。另外，虽然在所说明的实施例中，特定特征或组件已展示为具有特定布置或配置，但其它布置及配置是可能的。举例来说，图1的焊料凸块140可安置于裸片堆叠105的单个侧处而非安置于两个侧或多个侧处。焊料凸块140也可包含相较于在所说明实施例中展示的更大或更小数目的焊料凸块。而且，在特定实施例中，图2的逻辑裸片202a可安置于存储器裸片202b与封装衬底130之间而非存储器裸片202b与***物120之间。另外，在特定实施例的上下文中描述的新技术的特定方面也可在其它实施例中组合或消除。举例来说，图5的组合件500可包含图3的再分布网络327的电路元件329。此外，尽管与新技术的特定实施例相关的优点已在那些实施例的上下文中描述，但其它实施例也可展现此类优点，且并非所有实施例需要必要地展现此类优点来落入本技术的范围内。因此，本发明及相关技术可涵盖在本文中未清楚展示或描述的其它实施例。

Claims (35)

1.一种半导体裸片组合件，其包括：
半导体裸片堆叠；
导热外壳；
***物，其在所述导热外壳与所述半导体裸片堆叠之间，其中所述***物的***部分侧向延伸超过所述半导体裸片堆叠；
封装衬底，其承载所述导热外壳；及
多个传导构件，其经***于所述封装衬底与所述***物的所述***部分之间。
2.根据权利要求1所述的裸片组合件，其中所述导热外壳包含：
盖部分，其附接到所述***物的背侧表面；及
壁部分，其在所述盖部分与所述封装衬底之间竖直延伸；
其中所述壁部分附接到所述封装衬底的外表面。
3.根据权利要求2所述的裸片组合件，其中所述半导体裸片堆叠包含：
存储器裸片堆叠；及
逻辑裸片，其安置于所述存储器裸片堆叠与所述***物之间。
4.根据权利要求1所述的裸片组合件，其中所述裸片组合件进一步包括经***于所述封装衬底与所述半导体裸片堆叠之间的界面材料。
5.根据权利要求4所述的裸片组合件，其中：
所述界面材料是电绝缘的；
所述半导体裸片堆叠包含具有延伸穿过其的多个贯穿衬底互连件的最外裸片；且所述多个贯穿衬底互连件接触所述界面材料。
6.根据权利要求1所述的裸片组合件，其中所述半导体裸片堆叠进一步包括：
存储器裸片堆叠，其具有第一占用面积；及
逻辑裸片，其具有沿所述存储器裸片堆叠的至少一个轴线大于所述第一占用面积的第二占用面积。
7.根据权利要求6所述的裸片组合件，其中所述***物具有沿所述逻辑裸片的至少一个轴线大于所述第二占用面积的第三占用面积。
8.根据权利要求6所述的裸片组合件，其中个别传导构件包含焊料凸块。
9.根据权利要求1所述的裸片组合件，其中所述***物包含将所述传导构件电耦合到所述半导体裸片堆叠的再分布网络，且其中所述再分布网络包含在所述传导构件中的至少一者与所述半导体裸片堆叠之间耦合的电路元件。
10.根据权利要求9所述的裸片组合件，其中所述电路元件包含电容器。
11.根据权利要求1所述的裸片组合件，其中所述封装衬底包含：
外表面，其附接到所述导热外壳；及
凹入表面，其相对于所述外表面凹入，其中所述半导体裸片堆叠附接到所述凹入表面。
12.一种半导体裸片组合件，其包括：
导热外壳；
封装衬底，其中所述封装衬底及所述导热外壳一起界定壳体；
***物，其附接到所述壳体内的所述导热外壳；及
半导体裸片堆叠，其安置于所述***物与所述壳体内的所述封装衬底之间，其中所述半导体裸片电耦合至所述***物。
13.一种半导体裸片组合件，其包括：
导热外壳；
封装衬底，其包括多个第一接合垫，其中所述封装衬底和所述导热外壳一起界定壳体；
***物，其附接到所述壳体内的所述导热外壳，其中所述***物包含多个第二接合垫；
半导体裸片堆叠，其安置于所述***物与所述壳体内的所述封装衬底之间；以及所述半导体裸片组合件进一步包括多个传导构件，其中个别传导构件经安置于个别第一接合垫与个别第二接合垫之间。
14.根据权利要求13所述的裸片组合件，其中所述个别传导构件包含焊料凸块。
15.根据权利要求13所述的裸片组合件，其中所述多个传导构件包含：
个别第一焊料凸块，其耦合到所述个别第一接合垫，
个别第二焊料凸块，其耦合到所述个别第二接合垫，及
中间支撑件，其经安置于所述个别第一焊料凸块与所述个别第二焊料凸块之间。
16.根据权利要求15所述的裸片组合件，其中所述中间支撑件包含半导体材料。
17.一种半导体裸片组合件，其包括：
封装衬底，其具有腔室；
半导体裸片堆叠，其至少部分经安置于所述腔室内；
***物，其附接到所述半导体裸片堆叠，其中所述***物在所述腔室外侧；及导热外壳，其在所述腔室上方侧向延伸，其中所述导热外壳包含附接到所述封装衬底的第一部分及附接到所述***物的第二部分。
18.根据权利要求17所述的裸片组合件，其中所述***物的***部分侧向延伸超过所述半导体裸片堆叠，且其中所述半导体裸片组合件进一步包括经***于所述封装衬底与所述***物的所述***部分之间的多个焊料凸块。
19.根据权利要求17所述的裸片组合件，其中所述半导体裸片堆叠包含存储器裸片堆叠及***于所述存储器裸片堆叠与所述***物之间的逻辑裸片。
20.根据权利要求19所述的裸片组合件，其中所述逻辑裸片在所述腔室外侧附接到所述封装衬底。
21.一种形成半导体裸片组合件的方法，其包括：
将半导体裸片堆叠附接到***物；
在封装衬底与所述***物的***部分处的有效表面之间形成焊料凸块；及
将导热外壳附接到所述***物的与所述有效表面相对的背侧表面以至少部分将所述***物及所述半导体裸片堆叠封围于壳体内。
22.根据权利要求21所述的方法，其中所述方法进一步包含：将所述导热外壳附接到所述封装衬底。
23.根据权利要求21所述的方法，其中所述方法进一步包含：将所述半导体裸片堆叠附接到所述封装衬底，使得所述焊料凸块在所述半导体裸片堆叠与所述导热外壳之间竖直延伸。
24.根据权利要求23所述的方法，其中形成所述焊料凸块包含：形成具有等于或大于所述半导体裸片堆叠的竖直高度的竖直高度的焊料凸块。
25.根据权利要求21所述的方法，其中形成所述焊料凸块包含：将所述焊料凸块中的每一者附接到所述***物上的接合垫且附接到所述封装衬底上的对应接合垫。
26.根据权利要求21所述的方法，其中形成所述焊料凸块包含：将第一焊料凸块附接到所述***物上的第一接合垫；且其中所述方法进一步包括：
将第二焊料凸块附接到所述封装衬底上的第二接合垫；以及
将中间支撑件安置于个别第一焊料凸块与个别第二焊料凸块之间。
27.根据权利要求21所述的方法，其中所述半导体裸片堆叠包含附接到逻辑裸片的存储器裸片堆叠，且其中将所述半导体裸片堆叠附接到所述***物进一步包含将所述逻辑裸片附接到所述***物而使其位于所述***物与所述存储器裸片堆叠之间。
28.根据权利要求27所述的方法，其进一步包括：在所述***物上形成再分布网络，所述再分布网络将所述焊料凸块电耦合到所述半导体裸片堆叠。
29.根据权利要求28所述的方法，其中形成所述再分布网络包含：形成在所述存储器裸片堆叠与所述***物之间电耦合的电路元件。
30.根据权利要求29所述的方法，其中所述电路元件包含电容器。
31.一种形成半导体裸片组合件的方法，其包括：
将半导体裸片堆叠至少部分安置于封装衬底的腔室内；
将***物附接到所述半导体裸片堆叠及所述封装衬底的邻近于所述腔室的***表面；以及
将所述***物至少部分封围于导热外壳内。
32.根据权利要求31所述的方法，其进一步包括在所述封装衬底与所述***物的在所述腔室外侧的部分之间形成焊料凸块。
33.根据权利要求31所述的方法，其进一步包括将所述导热外壳附接到所述封装衬底。
34.根据权利要求31所述的方法，其进一步包括：
将逻辑裸片附接到存储器裸片堆叠以形成所述半导体裸片堆叠；以及
将所述存储器裸片堆叠附接到具有所述腔室的所述封装衬底。
35.一种半导体***，其包括：
混合存储器立方体HMC，其包含
封装衬底，
导热外壳，其界定壳体，
***物，其附接到所述壳体内的所述导热外壳，
半导体裸片堆叠，其在所述壳体内，其中所述裸片堆叠包含存储器裸片堆叠及附接到所述存储器裸片堆叠的至少一个逻辑裸片，及
多个焊料凸块，其在所述***物与所述封装衬底之间耦合，其中所述多个焊料凸块邻近于所述半导体裸片堆叠；及
驱动器，其经由所述封装衬底电耦合到所述HMC。
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