CN106098790A - There is nitrogenous FET device of sull and preparation method thereof - Google Patents
There is nitrogenous FET device of sull and preparation method thereof Download PDFInfo
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- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 title claims abstract description 54
- 238000002360 preparation method Methods 0.000 title claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000005516 engineering process Methods 0.000 claims abstract description 21
- 230000004888 barrier function Effects 0.000 claims abstract description 18
- 238000002161 passivation Methods 0.000 claims abstract description 15
- 238000005546 reactive sputtering Methods 0.000 claims abstract description 10
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 claims abstract 6
- 238000000034 method Methods 0.000 claims description 48
- 238000000059 patterning Methods 0.000 claims description 39
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 17
- 238000004544 sputter deposition Methods 0.000 claims description 16
- 239000010409 thin film Substances 0.000 claims description 14
- 239000010408 film Substances 0.000 claims description 12
- 229910052757 nitrogen Inorganic materials 0.000 claims description 10
- 239000000919 ceramic Substances 0.000 claims description 9
- 238000000231 atomic layer deposition Methods 0.000 claims description 8
- 238000001704 evaporation Methods 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052733 gallium Inorganic materials 0.000 claims description 5
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims description 5
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 4
- 229910004205 SiNX Inorganic materials 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 4
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 229910052804 chromium Inorganic materials 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 238000001771 vacuum deposition Methods 0.000 claims description 4
- 239000011701 zinc Substances 0.000 claims description 4
- 229910052725 zinc Inorganic materials 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000001035 drying Methods 0.000 claims description 3
- 229910052738 indium Inorganic materials 0.000 claims description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 3
- 238000002156 mixing Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000007738 vacuum evaporation Methods 0.000 claims description 3
- SMFFOCYRDBWPIA-UHFFFAOYSA-N N.[O-2].[Zn+2] Chemical compound N.[O-2].[Zn+2] SMFFOCYRDBWPIA-UHFFFAOYSA-N 0.000 claims description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 2
- 230000033228 biological regulation Effects 0.000 claims description 2
- 229910052791 calcium Inorganic materials 0.000 claims description 2
- 229910052681 coesite Inorganic materials 0.000 claims description 2
- 229910052593 corundum Inorganic materials 0.000 claims description 2
- 229910052906 cristobalite Inorganic materials 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims description 2
- 229910052749 magnesium Inorganic materials 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 229910052682 stishovite Inorganic materials 0.000 claims description 2
- 229910052715 tantalum Inorganic materials 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N titanium dioxide Inorganic materials O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052905 tridymite Inorganic materials 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 2
- 239000011787 zinc oxide Substances 0.000 claims description 2
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 claims 1
- 238000005286 illumination Methods 0.000 abstract description 19
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 230000001737 promoting effect Effects 0.000 abstract description 4
- 230000000052 comparative effect Effects 0.000 description 11
- 229910007717 ZnSnO Inorganic materials 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 239000007792 gaseous phase Substances 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 230000005669 field effect Effects 0.000 description 4
- 238000012546 transfer Methods 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 150000001768 cations Chemical class 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- FIPWRIJSWJWJAI-UHFFFAOYSA-N Butyl carbitol 6-propylpiperonyl ether Chemical compound C1=C(CCC)C(COCCOCCOCCCC)=CC2=C1OCO2 FIPWRIJSWJWJAI-UHFFFAOYSA-N 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000009833 condensation Methods 0.000 description 1
- 230000005494 condensation Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 239000003792 electrolyte Substances 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/34—Sputtering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
Abstract
The invention discloses and a kind of there is nitrogenous FET device of sull and preparation method thereof, belong to TFT device arts.Main containing nitrogen oxide is realized by reactive sputtering, cosputtering, and the most total mole percent level of N element controls between 0.1 to 3%.This device is made up of substrate, grid, insulating barrier, nitrogen-containing oxide active layer, source electrode, drain electrode, passivation layer successively.The present invention can realize promoting electric property and the illumination back bias voltage stability of oxide simultaneously.It addition, the preparation method of nitrogen-containing oxide and existing oxide TFT preparation technology have good compatibility, the most effectively save the manufacturing cost of nitrogen-containing oxide TFT.
Description
Technical field
The present invention relates to a kind of FET device and preparation method thereof, particularly relate to a kind of thin film field-effect brilliant
Body tube device and preparation method thereof, is applied to TFT technical field.
Background technology
Display Technique is referred to as the window of wisdom and the window of civilization of modern humans society, and TFT
(TFT) technology is one of key core technology of Display Technique.Comparing traditional non-crystalline silicon tft, oxide thin film transistor has
There are the plurality of advantages such as mobility is high, preparation technology temperature is low, visible light transmissivity is high, and cost of manufacture is low, to replacing non-crystalline silicon
TFT is applied to active display.Although oxide TFT shows good electric property, but oxide TFT is in stability still
The application requirement of reality can not be met, it has also become the Pinch technology of oxide TFT development.Owing to TFT is in the process of continuous firing
In, often being acted on by while illumination and bias, the illumination back bias voltage stability of oxide TFT is substantially deteriorated, current
Research mainly uses the cation dopings such as Hf, Zr, Ga to reduce Lacking oxygen, thus the illumination back bias voltage promoting oxide TFT is steady
Qualitative, but the method for this cation suppression room improving stability, may often be such that with the mobility of sacrifical oxide TFT as generation
Valency, the scheme application causing this cation doping to promote illumination back bias voltage stability is restricted.
Summary of the invention
In order to solve prior art problem, it is an object of the invention to the deficiency overcoming prior art to exist, it is provided that a kind of
There is nitrogenous FET device of sull and preparation method thereof, there is the field effect of nitrogenous sull
Answer transistor device can realize promoting electric property and the illumination back bias voltage stability of sull TFT simultaneously.It addition, this
Light field field effect transistor devices preparation method and existing oxide TFT preparation technology have good compatibility, the most effective
Saved the manufacturing cost of nitrogen-containing oxide TFT.
Creating purpose for reaching foregoing invention, the present invention uses following technical proposals:
A kind of FET device with nitrogenous sull, is the most successively prepared from by structure sheaf order,
Mainly constituted bottom grating structure or top gate structure, active layer by substrate, grid, insulating barrier, active layer, source electrode, drain electrode and passivation layer
Use containing N element relative in active layer the mole percent level of total material amount be 0.1～3% sull make, have
The thickness of active layer is 20～80 nm, and the thickness of insulating barrier and passivation layer is 50～200 nm, the thickness of grid, source electrode and drain electrode
Degree is 50～100 nm.
The sull of above-mentioned active layer preferably employs nitrogen indium gallium zinc, nitrogen zinc oxide, nitrogen stannum oxide and nitrogen oxidation
Any one oxide or the most several oxide mixing materials in indium are made.
Aforesaid substrate preferably employs any one in silicon chip, flexible substrate, glass substrate and ceramic substrate.
The material of above-mentioned grid preferably employ in Au, Al, Cu, Mo, Cr, Ti, ITO, W, Ag and Ta any one or
The most several.
It is any that above-mentioned source electrode and above-mentioned drain material preferably employ in Au, Ag, Mo, Al, Cu, Cr, Ti, Mg and Ca respectively
One or any several.
Above-mentioned insulating barrier and above-mentioned passivation layer preferably employ Ta respectively2O5、Al2O3、SiO2、TiO2And SiNxIn any one
Kind material or the thin film that arbitrarily different materials is prepared from.
A kind of present invention has the preparation method of the FET device of nitrogenous sull, by layer of structure
Sequence is the most successively prepared, and comprises the steps:
A. select to meet the substrate being sized requiring, clean post-drying, standby；
B., in step a on the substrate of the dried and clean of preparation, by vacuum evaporation method or sputtering technology, and pattern is realized
Change, prepare the grid of the patterning that thickness is 50～100 nm, obtain the substrate with grid；When the method using vacuum evaporation
When preparing grid, preferably control vacuum less than 10-3Pa；
On the substrate with grid prepared the most in stepb, use atomic layer deposition method, chemical vapour deposition technique, sputtering method
Or method of evaporating prepares the insulating barrier that thickness is 50～200 nm；
D. use and be passed through N2Carry out reactive sputtering method or use the target containing N element to carry out cosputtering method, and realizing figure
Case, in step c on the insulating barrier of preparation, prepares the nitrogenous sull of the patterning that thickness is 20～80 nm, makees
For active layer, relative in active layer, the mole percent level of total material amount is 0.1～3% to the N element in active layer；Preferably
Any one oxide in indium gallium zinc, zinc oxide, stannum oxide and Indium sesquioxide. or the most several oxides is used to mix
Condensation material makes ceramic target, preferably makes the N being passed through2Flow is 1～4 sccm, uses reactive sputtering method, carries out patterning system
Standby nitrogenous sull, is formed with active layer, and uses regulation N2The method of flow is come in control oxide thin film active layer
Nitrogen element content；
E. after preparing active layer through step d patterning, on the partial insulative layer being not covered with active layer, then vacuum is used
Method of evaporating or sputtering method prepare source electrode and drain electrode respectively, make source electrode and drain electrode realize patterning, and make source electrode and drain electrode
Thickness is 50～100 nm；When the method using vacuum evaporation prepares source electrode and drain electrode, preferably control vacuum less than 10- 3Pa；
F., after preparing active layer through step d patterning, on active layer, Atomic layer deposition method, chemical gaseous phase are used
Deposition process, sputtering method or method of evaporating prepare the passivation layer that thickness is 50～200 nm, thus complete have bottom grating structure
The preparation of FET device of sull.
Nitrogen-containing oxide of the present invention breaks through routine as active layer material preparation method, and this nitrogen-containing oxide can be effectively
Reduce thin-films Oxygen room, simultaneously without the mobility of sacrifical oxide thin film, can realize promoting the electrical property of oxide TFT simultaneously
Can be with illumination back bias voltage stability.It addition, the preparation method of nitrogen-containing oxide has good with existing oxide TFT preparation technology
Good compatibility, has saved the manufacturing cost of nitrogen-containing oxide TFT the most effectively.The present invention has been adequately bonded nitrogenous oxidation
The unique advantage of thing, is effectively improved the illumination back bias voltage stability of oxide TFT, and oxide TFT will be sent out by this preparation technology
Exhibition has positive impetus.
The present invention compared with prior art, has and the most obviously highlights substantive distinguishing features and remarkable advantage:
1. the present invention uses nitrogen-containing oxide semi-conducting material as the active layer of TFT, and wherein N doping is by being passed through N2Instead
Should sputter or be prepared by the target cosputtering method containing N element, technique simple possible, use reactive sputtering or
Cosputtering method can accurately control the content of N element；
2. the nitrogen-containing oxide TFT that prepared by the present invention and current ordinary oxide TFT have good processing compatibility.
Accompanying drawing explanation
Fig. 1 is the embodiment of the present invention one nitrogen-containing oxide TFT device architecture schematic diagram.
Fig. 2 is to use different N2Flow utilize reactive sputtering method prepare sull active time, the present invention implement
Not nitrogen-containing oxide prepared by example one and the nitrogen-containing oxide TFT device of embodiment two preparation and comparative example
The transfer characteristic curve comparison diagram of TFT device.
Fig. 3 is the illumination back bias voltage stability curve of unazotized ZnSnO-TFT device prepared by comparative example.
Fig. 4 is that the illumination back bias voltage stability with nitrogenous ZnSnON-TFT device of the embodiment of the present invention one preparation is bent
Line.
Detailed description of the invention
Details are as follows for the preferred embodiments of the present invention:
Embodiment one:
In the present embodiment, Fig. 1,2 and 4, the system of a kind of FET device with nitrogenous sull are seen
Preparation Method, is the most successively prepared by structure sheaf order, comprises the steps:
A. select to meet the silicon chip substrate being sized requiring as substrate, clean post-drying, standby；
B., in step a on the substrate of the dried and clean of preparation, form one layer of ITO by sputtering technology, and realize patterning,
Prepare the grid of the patterning that thickness is 80 nm, obtain the substrate with grid；
On the substrate with grid prepared the most in stepb, sputtering method is used to prepare the SiOx electrolyte that thickness is 100 nm
Insulating barrier；
D. use ZnSnO ceramic target, make the N being passed through2Flow is respectively 1sccm, 2sccm, 4sccm, is respectively adopted reaction and spatters
Shooting method, and realize patterning, in step c on the insulating barrier of preparation, prepare the nitrogenous of the patterning that thickness is 40nm respectively
ZnSnON oxide semiconductor film layer, as active layer；
E. after preparing active layer through step d patterning, on the partial insulative layer being not covered with active layer, then vacuum is controlled
Degree is less than 10-3Pa, uses vacuum evaporation method to prepare source electrode and drain electrode respectively, makes source electrode and drain electrode realize patterning, and makes source
The thickness of pole and drain electrode is 60nm；
F., after preparing active layer through step d patterning, on active layer, Atomic layer deposition method is used to prepare thickness
It is the Al of 100 nm2O3Layer is as passivation layer, thus completes the FET device with the sull of bottom grating structure
Preparation.
Thin film transistor (TFT) prepared by the present embodiment is bottom grating structure, sees Fig. 1, from bottom to up by substrate 1, grid 2, insulation
Layer 3, the active layer 4 of ZnSnON oxide semiconductor film, source electrode 5, drain electrode 6, passivation layer 7 are constituted successively.Use the present embodiment
Preparing FET device compared with traditional devices, maximum difference is to promote the electricity of oxide TFT device simultaneously
Learn performance and illumination back bias voltage stability；It addition, the preparation method of nitrogen-containing oxide has with existing oxide TFT preparation technology
There is good compatibility, the most effectively saved the manufacturing cost of nitrogen-containing oxide TFT.Visible employing the present embodiment method system
Standby ZnSnON-TFT without changing traditional preparation technology, program simple possible, will have well in flat display field
Application prospect.
Embodiment two:
The present embodiment is essentially identical with embodiment one, is particular in that:
In this comparative example, see Fig. 2, the preparation side of a kind of FET device with nitrogenous sull
Method, is the most successively prepared by structure sheaf order, comprises the steps:
A. this step is identical with embodiment one；
B. this step is identical with embodiment one；
C. this step is identical with embodiment one；
D. use ZnSnO ceramic target, make the N being passed through2Flow is 6sccm, uses reactive sputtering method, and realizes patterning,
In step c on the insulating barrier of preparation, prepare the nitrogenous ZnSnON oxide semiconductor film layer of the patterning that thickness is 40nm,
As active layer；
E. this step is identical with embodiment one；
F. this step is identical with embodiment one.
Prepared by the present embodiment has transfer characteristic and the illumination of the FET device of nitrogenous sull
The FET device with nitrogenous sull that back bias voltage stability is prepared with embodiment one is close, uses this
Embodiment prepares FET device compared with traditional devices, and maximum difference is promote oxide TFT device simultaneously
The electric property of part and illumination back bias voltage stability.ZnSnON-TFT prepared by visible employing the present embodiment method passes without changing
The preparation technology of system, program simple possible, will there is good application prospect in flat display field.
Embodiment three:
The present embodiment is substantially the same as in the previous example, and is particular in that:
In this comparative example, the preparation method of a kind of FET device with nitrogenous sull, by structure
Layer order is the most successively prepared, and comprises the steps:
A. this step is identical with embodiment one；
B., in step a on the substrate of the dried and clean of preparation, form one layer of ITO by sputtering technology, and realize patterning,
Prepare the grid of the patterning that thickness is 50nm, obtain the substrate with grid；
On the substrate with grid prepared the most in stepb, chemical gaseous phase deposition is used to prepare the SiNx that thickness is 50 nm
Dielectric insulation layer；
D. use ZnSnO ceramic target, make the N being passed through2Flow is 6sccm, uses reactive sputtering method, and realizes patterning,
In step c on the insulating barrier of preparation, prepare the nitrogenous ZnSnON oxide semiconductor film layer of the patterning that thickness is 20nm,
As active layer；
E. after preparing active layer through step d patterning, on the partial insulative layer being not covered with active layer, then sputtering is used
Method prepares source electrode and drain electrode respectively, makes source electrode and drain electrode realize patterning, and makes the thickness of source electrode and drain electrode be 50nm；
F., after preparing active layer through step d patterning, on active layer, Atomic layer deposition method, chemical gaseous phase are used
Deposition process, sputtering method or method of evaporating prepare the Al that thickness is 50nm2O3Layer is as passivation layer, thus completes have bottom gate
The preparation of the FET device of the sull of structure.
Prepared by the present embodiment has transfer characteristic and the illumination of the FET device of nitrogenous sull
The FET device with nitrogenous sull that back bias voltage stability is prepared with embodiment one is close, uses this
Embodiment prepares FET device compared with traditional devices, and maximum difference is promote oxide TFT device simultaneously
The electric property of part and illumination back bias voltage stability.ZnSnON-TFT prepared by visible employing the present embodiment method passes without changing
The preparation technology of system, program simple possible, will there is good application prospect in flat display field.
Embodiment four:
The present embodiment is substantially the same as in the previous example, and is particular in that:
In this comparative example, the preparation method of a kind of FET device with nitrogenous sull, by structure
Layer order is the most successively prepared, and comprises the steps:
A. this step is identical with embodiment one；
B., in step a on the substrate of the dried and clean of preparation, form one layer of ITO by sputtering technology, and realize patterning,
Prepare the grid of the patterning that thickness is 100 nm, obtain the substrate with grid；
On the substrate with grid prepared the most in stepb, chemical gaseous phase deposition is used to prepare the SiNx that thickness is 200 nm
Dielectric insulation layer；
D. use ZnSnO ceramic target, make the N being passed through2Flow is 6sccm, uses reactive sputtering method, and realizes patterning,
In step c on the insulating barrier of preparation, prepare the nitrogenous ZnSnON oxide semiconductor film of the patterning that thickness is 80 nm
Layer, as active layer；
E. after preparing active layer through step d patterning, on the partial insulative layer being not covered with active layer, then sputtering is used
Method prepares source electrode and drain electrode respectively, makes source electrode and drain electrode realize patterning, and makes the thickness of source electrode and drain electrode be 100 nm；
F., after preparing active layer through step d patterning, on active layer, Atomic layer deposition method, chemical gaseous phase are used
Deposition process, sputtering method or method of evaporating prepare the Al that thickness is 200 nm2O3Layer is as passivation layer, thus completes have the end
The preparation of the FET device of the sull of grid structure.
Prepared by the present embodiment has transfer characteristic and the illumination of the FET device of nitrogenous sull
The FET device with nitrogenous sull that back bias voltage stability is prepared with embodiment one is close, uses this
Embodiment prepares FET device compared with traditional devices, and maximum difference is promote oxide TFT device simultaneously
The electric property of part and illumination back bias voltage stability.ZnSnON-TFT prepared by visible employing the present embodiment method passes without changing
The preparation technology of system, program simple possible, will there is good application prospect in flat display field.
Comparative example:
This comparative example is substantially the same as in the previous example, and is particular in that:
In this comparative example, see Fig. 2 and 3, the preparation method of a kind of FET device with sull, press
Structure sheaf order is the most successively prepared, and comprises the steps:
A. this step is identical with embodiment one；
B. this step is identical with embodiment one；
C. this step is identical with embodiment one；
D. use ZnSnO ceramic target, use sputtering method, and realize patterning, in step c on the insulating barrier of preparation, preparation
Thickness is the ZnSnO oxide semiconductor film layer of the patterning of 40nm, as active layer；
E. this step is identical with embodiment one；
F., after preparing active layer through step d patterning, on active layer, Atomic layer deposition method is used to prepare thickness
It is the Al of 100 nm2O3Layer is as passivation layer, thus the field effect completing to have the unazotized sull of bottom grating structure is brilliant
The preparation of body tube device.
Thin film transistor (TFT) prepared by this comparative example is bottom grating structure, from bottom to up by substrate, grid, insulating barrier, ZnSnO half
The active layer of conducting oxide thin film, source electrode, drain electrode, passivation layer are constituted successively.
Experimental test and analysis:
Prepared by the FET device of the nitrogenous sull preparing above-described embodiment and comparative example the most nitrogenous
The FET device of sull carry out detection respectively and analyze, and in conjunction with the embodiments one, embodiment two and
Comparative example compares, and is changed to 6sccm, mobility first increases and then decreases, threshold when the flow of nitrogen from 0 sccm as can be seen from Figure 2
Threshold voltage is gradually reduced.Comparing embodiment one, the ZnSnON film effect transistor device in embodiment two presents poor electricity
Learn performance.Considering, such as embodiment one, when the flow of nitrogen is 2 sccm, ZnSnON film effect transistor device has
Optimum electric property, mobility is 7.0 cm2/V s, threshold voltage is 2.5 V, and on-off ratio is 107Magnitude.
From the figure 3, it may be seen that the ZnSnO film effect transistor device of routine is 2000 lux in light intensity, back bias voltage is-10 V
Time, after aging 3600 s, threshold voltage shift 6.2V.As shown in Figure 4, ZnSnON thin film effect when the flow of nitrogen is 2 sccm
Answering transistor device under identical condition, threshold voltage has only drifted about 2.9V.Visible, mix the ZnSnON film effect after N
The illumination back bias voltage stability of transistor device is substantially better than the ZnSnO film effect transistor device of routine.
Use the FET device of nitrogenous sull prepared by above-described embodiment compared with traditional devices,
Maximum difference is promote the electric property of oxide TFT device and illumination back bias voltage stability simultaneously.Seeing Fig. 2 can
Know, in embodiment one and embodiment two, use the flow of nitrogen to control the nitrogen element content in ZnSnON thin film, thus adjust
The electric property of control ZnSnON thin film and Lacking oxygen content.ZnSnON-TFT prepared by this kind of technology of visible employing passes without changing
The preparation technology of system, program simple possible, will there is good application prospect in flat display field.
Above in conjunction with accompanying drawing, the embodiment of the present invention is illustrated, but the invention is not restricted to above-described embodiment, it is also possible to
The purpose of the innovation and creation according to the present invention makes multiple change, under all spirit according to technical solution of the present invention and principle
The change made, modify, substitute, combine or simplify, all should be the substitute mode of equivalence, as long as meeting the goal of the invention of the present invention,
There is the know-why of the nitrogenous FET device of sull and preparation method thereof without departing from the present invention
And inventive concept, broadly fall into protection scope of the present invention.
Claims (9)
1. a FET device with nitrogenous sull, it is characterised in that: by structure sheaf order successively
Successively it is prepared from, mainly by substrate (1), grid (2), insulating barrier (3), active layer (4), source electrode (5), drain electrode (6) and passivation
Layer (7) constitutes bottom grating structure or top gate structure, described active layer (4) use containing N element relative in active layer (4) total material amount
Mole percent level be 0.1～3% sull make, the thickness of described active layer (4) is 20～80 nm, described
The thickness of insulating barrier (3) and described passivation layer (7) is 50～200 nm, described grid (2), described source electrode (5) and described leakage
The thickness of pole (6) is 50～100 nm.
The most according to claim 1, there is the FET device of nitrogenous sull, it is characterised in that: described
The sull of active layer (4) uses any one in nitrogen indium gallium zinc, nitrogen zinc oxide, nitrogen stannum oxide and nitrogen Indium sesquioxide.
Oxide or the most several oxide mixing materials are made.
The most according to claim 1, there is the FET device of nitrogenous sull, it is characterised in that: substrate
(1) any one in employing silicon chip, flexible substrate, glass substrate and ceramic substrate.
The most according to claim 1, there is the FET device of nitrogenous sull, it is characterised in that: described
The material of grid (2) use in Au, Al, Cu, Mo, Cr, Ti, ITO, W, Ag and Ta any one or the most several.
The most according to claim 1, there is the FET device of nitrogenous sull, it is characterised in that: described
Source electrode (5) and described drain electrode (6) material be respectively adopted in Au, Ag, Mo, Al, Cu, Cr, Ti, Mg and Ca any one or appoint
Anticipate several.
The most according to claim 1, there is the FET device of nitrogenous sull, it is characterised in that: described
Insulating barrier (3) and described passivation layer (7) are respectively adopted Ta2O5、Al2O3、SiO2、TiO2And SiNxIn any one material or
The thin film that arbitrarily different materials is prepared from.
7. having a preparation method for the FET device of nitrogenous sull described in claim 1, it is special
Levy and be, the most successively prepare by structure sheaf order, comprise the steps:
A. select to meet the substrate being sized requiring, clean post-drying, standby；
B., in described step a on the substrate of the dried and clean of preparation, by vacuum evaporation method or sputtering technology, and realize
Patterning, prepares the grid of the patterning that thickness is 50～100 nm, obtains the substrate with grid；
C., in described step b on the substrate with grid of preparation, use atomic layer deposition method, chemical vapour deposition technique, spatter
Penetrate method or method of evaporating prepares the insulating barrier that thickness is 50～200 nm；
D. use and be passed through N2Carry out reactive sputtering method or use the target containing N element to carry out cosputtering method, and realizing figure
Case, in described step c on the insulating barrier of preparation, prepares the thin containing nitrogen oxide of the patterning that thickness is 20～80 nm
Film, as active layer, relative in active layer, the mole percent level of total material amount is 0.1～3% to the N element in active layer；
E., after preparing active layer through described step d patterning, on the partial insulative layer being not covered with active layer, then use
Vacuum evaporation method or sputtering method prepare source electrode and drain electrode respectively, make source electrode and drain electrode realize patterning, and make source electrode and leakage
The thickness of pole is 50～100 nm；
F., after preparing active layer through described step d patterning, on active layer, Atomic layer deposition method, chemistry are used
CVD method, sputtering method or method of evaporating prepare the passivation layer that thickness is 50～200 nm, thus complete have bottom gate
The preparation of the FET device of the sull of structure.
The most according to claim 7, have the preparation method of the FET device of nitrogenous sull, it is special
Levy and be: in described step b and step e, when the method using vacuum evaporation prepares electrode, control vacuum less than 10- 3Pa。
The most according to claim 7, have the preparation method of the FET device of nitrogenous sull, it is special
Levy and be: in described step d, use any one oxide in indium gallium zinc, zinc oxide, stannum oxide and Indium sesquioxide. or
Ceramic target made by the most several oxide mixing material of person, makes the N being passed through2Flow is 1～4 sccm, uses reactive sputtering side
Method, carries out patterning and prepares nitrogenous sull, is formed with active layer, and uses regulation N2The method of flow controls oxidation
Nitrogen element content in thing thin film active layer.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107976476A (en) * | 2017-11-17 | 2018-05-01 | 中山大学 | A kind of assay method of the lactic acid dehydrogenase activity based on titanium deoxid film field-effect tube |
| CN111146277A (en) * | 2020-01-02 | 2020-05-12 | 歌尔股份有限公司 | Field effect transistor and preparation method thereof |
| CN111769161A (en) * | 2019-04-01 | 2020-10-13 | 山东大学 | Nitrogen-doped amorphous oxide thin film transistor and preparation method thereof |
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| US20150034942A1 (en) * | 2013-08-05 | 2015-02-05 | Samsung Electronics Co., Ltd. | Thin film transistor and method of manufacturing the same |
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| KR20100055655A (en) * | 2008-11-18 | 2010-05-27 | 국민대학교산학협력단 | Method for preparing n-type zno semiconductor thin film and thin film transistor |
| US20150034942A1 (en) * | 2013-08-05 | 2015-02-05 | Samsung Electronics Co., Ltd. | Thin film transistor and method of manufacturing the same |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107976476A (en) * | 2017-11-17 | 2018-05-01 | 中山大学 | A kind of assay method of the lactic acid dehydrogenase activity based on titanium deoxid film field-effect tube |
| CN107976476B (en) * | 2017-11-17 | 2020-06-30 | 中山大学 | Determination method of lactate dehydrogenase activity based on titanium dioxide thin film field effect transistor |
| CN111769161A (en) * | 2019-04-01 | 2020-10-13 | 山东大学 | Nitrogen-doped amorphous oxide thin film transistor and preparation method thereof |
| CN111146277A (en) * | 2020-01-02 | 2020-05-12 | 歌尔股份有限公司 | Field effect transistor and preparation method thereof |
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