CN106098563B - Narrow frame display panel, thin film transistor (TFT) and preparation method thereof - Google Patents
Narrow frame display panel, thin film transistor (TFT) and preparation method thereof Download PDFInfo
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- CN106098563B CN106098563B CN201610728527.5A CN201610728527A CN106098563B CN 106098563 B CN106098563 B CN 106098563B CN 201610728527 A CN201610728527 A CN 201610728527A CN 106098563 B CN106098563 B CN 106098563B
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- 239000010409 thin film Substances 0.000 title claims abstract description 60
- 238000002360 preparation method Methods 0.000 title claims abstract description 17
- 238000007514 turning Methods 0.000 claims abstract description 49
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 46
- 229920005591 polysilicon Polymers 0.000 claims abstract description 45
- 238000005520 cutting process Methods 0.000 claims abstract description 37
- 238000000034 method Methods 0.000 claims abstract description 32
- 239000010410 layer Substances 0.000 claims description 96
- 239000002184 metal Substances 0.000 claims description 35
- 239000010408 film Substances 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 19
- 239000011229 interlayer Substances 0.000 claims description 18
- 239000013078 crystal Substances 0.000 claims description 2
- 238000009413 insulation Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 16
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000012528 membrane Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a kind of narrow frame display panels, thin film transistor (TFT) and preparation method thereof, wherein cut by the perpendicular corners of source region and drain region to thin film transistor (TFT) polysilicon layer, so that the turning after cutting is greater than the distance between turning and channel region edge before cutting at a distance from channel region edge, conducting resistance of the thin film transistor (TFT) in process deviation between source electrode and drain electrode unbalance problem is effectively improved under the premise of not changing display panel size so as to realize.
Description
Technical field
The present invention relates to technical field of display panel, more particularly to a kind of narrow frame display panel, thin film transistor (TFT) and
Preparation method.
Background technique
With low temperature polycrystalline silicon (Low temperature Poly silicon；Write a Chinese character in simplified form are as follows: LTPS) semiconductive thin film crystalline substance
The development of body pipe, and due to the characteristic of LTPS semiconductor superhigh current carrying transport factor itself, everybody starts to put forth effort to study to exist
The relevant technologies of LTPS display panel periphery integrated circuit and System on Panel (SOP).Traditional narrow frame TFT (Thin
Film Transistor；Thin film transistor (TFT)), due to the limitation of design rule, polysilicon layer is in NP (N-type heavy doping) region meeting
There is a vertical turning.Therefore, when processing procedure equation deviation occurs for thin film transistor (TFT), the region NP is relative to polysilicon layer
Position can change.
Fig. 1 to Fig. 2 is please referred to, Fig. 1 is the structural schematic diagram of the standard processing procedure of the thin film transistor (TFT) of the prior art, and Fig. 2 is
Structural representation of traditional thin film transistor (TFT) in process deviation.Wherein, S indicates source region, and G indicates that area of grid, D indicate
Drain region, LDD (Low Doping Drain) indicate low doped region.Between the source electrode and drain electrode of traditional thin film transistor (TFT)
The principle that changes in process deviation of total conducting resistance it is as follows:
When process deviation occurs in thin film transistor (TFT), the LDD of thin film transistor (TFT) the right and left is unbalance, film shown in Fig. 2
LDD is deviated to the left side when transistor process deviation, i.e. LDD covers part source region S.Therefore, thin film transistor (TFT) processing procedure is inclined
The width of left-hand component LDD is caused to increase when poor, the width of the LDD of right-hand component is constant.Compared with the thin film transistor (TFT) of standard,
The LDD gross area of the thin film transistor (TFT) of process deviation is greater than the LDD gross area of the thin film transistor (TFT) of standard processing procedure, so as to cause thin
Film transistor the right and left LDD's is unbalance, i.e., process deviation when thin film transistor (TFT) total conducting resistance be less than standard processing procedure
Thin film transistor (TFT) total conducting resistance.
Summary of the invention
The present invention provides a kind of narrow frame display panel, thin film transistor (TFT) and preparation method thereof, and realization is not changing film
Under the premise of transistor size, solve the problems, such as that thin film transistor (TFT) is unbalance in process deviation bring resistance.
In order to solve the above technical problems, first technical solution that the present invention uses is: providing the preparation of thin film transistor (TFT)
Method, comprising:
Underlay substrate is provided；
Polysilicon layer is formed on underlay substrate, polysilicon layer includes channel region, source region and drain region, source
There are turnings for polar region domain and/or drain region；
Channel doping is carried out to polysilicon layer；
Heavy doping is carried out to source region and drain region；
Gate metal layer is set on channel region；
Source-drain electrode metal layer is set on source region and drain region；
Wherein, further comprise: turning is cut, so that the turning after cutting is at a distance from channel region edge
Greater than the turning and the distance between channel region edge before cutting.
Wherein, the step of cutting turning include:
Cutting and top rake are carried out to turning, to form oblique angle.
Wherein, after the step of gate metal layer is arranged on channel region, method further comprises: in gate metal layer
Upper setting interlayer insulating film, interlayer insulating film covering gate metal layer simultaneously extend on polysilicon layer.
Wherein, method further comprises:
Through-hole is set in interlayer insulating film, source-drain electrode metal layer is connect by through-hole with source region and drain region.
Wherein, include: to the step of source region and drain region progress heavy doping
N-type heavy doping is carried out to source region and drain region.
In order to solve the above technical problems, second technical solution that the present invention uses is: providing a kind of thin film transistor (TFT), wrap
It includes:
Underlay substrate；
Polysilicon layer is set on underlay substrate, and polysilicon layer includes channel region, source region and drain region；
Gate metal layer is set on channel region；
Source-drain electrode metal layer is set on source region and drain region；
Wherein there is the turning after cutting in source region and/or drain region, and turning and channel region after cutting
The distance between edge is greater than the distance between turning and channel region edge before cutting.
Wherein, the turning after cutting is oblique angle.
Wherein, thin film transistor (TFT) further includes interlayer insulating film, and interlayer insulating film covering gate metal layer simultaneously extends to polycrystalline
On silicon layer.
Wherein, through-hole is provided on interlayer insulating film, source-drain electrode metal layer passes through through-hole and source region and drain region
Connection.
In order to solve the above technical problems, the third technical solution that the present invention uses is: providing a kind of narrow frame display surface
Plate, including above-mentioned thin film transistor (TFT).
The beneficial effects of the present invention are: being in contrast to the prior art, thin film transistor (TFT) of the invention leads on processing procedure
It crosses and the source region of polysilicon layer and/or the turning of drain region is cut, so that turning and channel region after cutting
The distance at edge is greater than the distance between turning and channel region edge before cutting, is not changing film crystalline substance so as to realize
Under the premise of body pipe size, it is effectively improved resistance unbalance of the thin film transistor (TFT) in process deviation.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the standard processing procedure of the thin film transistor (TFT) of the prior art；
Fig. 2 is structural schematic diagram of the thin film transistor (TFT) in process deviation in Fig. 1；
Fig. 3 is the flow diagram of the preparation method of the thin film transistor (TFT) of one embodiment of the invention；
Fig. 4 is the structural schematic diagram of the polysilicon layer of thin film transistor (TFT) of the invention；
Fig. 5 is the schematic diagram that channel doping is carried out to the polysilicon layer in Fig. 4；
Fig. 6 is the schematic diagram that N-type heavy doping is carried out to the source region of the polysilicon layer in Fig. 5 and drain region；
Fig. 7 is the schematic diagram that gate metal layer is arranged on the channel region of the polysilicon layer in Fig. 6；
Fig. 8 is to the schematic diagram that interlayer insulating film is arranged on the thin film transistor (TFT) in Fig. 7；
Fig. 9 is the structural schematic diagram of thin film transistor (TFT) of the invention；
Figure 10 is schematic diagram of the thin film transistor (TFT) in process deviation in Fig. 9；
Figure 11 is the structural schematic diagram of narrow frame display panel of the invention.
Specific embodiment
The present invention is described in detail with embodiment with reference to the accompanying drawing.
The present invention be directed to for the processing procedure of N-type TFT.
Fig. 3 is referred to, Fig. 3 is the flow diagram of the preparation method of thin film transistor (TFT) of the invention.As shown in figure 3, this
The preparation method of embodiment thin film transistor (TFT) includes:
S31: underlay substrate is provided.
Underlay substrate (not shown) is preferably glass substrate.
S32: polysilicon layer is formed on underlay substrate, and the turning in polysilicon layer is cut.
On underlay substrate formed polysilicon layer 400, polysilicon layer 400 include channel region 401, source region 402 with
And drain region 403, and there is cutting turning 405, in the present embodiment, source in source region 402 and/or drain region 403
There is cutting turning 405 in polar region domain 402 and drain region 403, as shown in Figure 4.
The cutting turning 405 of source region 402 and drain region 403 is by the polysilicon layer to formation in the present embodiment
400 source region 402 and the perpendicular corners 404 of drain region 403 are cut and are formed, i.e., by perpendicular corners 404
Cutting and top rake are carried out, so that oblique angle 405 is formed, so that the oblique angle 405 of the formation after cutting and 401 edge of channel region
Distance is greater than the distance between perpendicular corners 404 and 401 edge of channel region before cutting.For example, former perpendicular corners 404 and ditch
The distance at 401 edge of road region is L1, and the turning 405 after cutting is L2, L2 > L1 at a distance from 401 edge of channel region.
In other embodiments, thin film transistor (TFT) 900 further includes one layer of buffer layer (not shown), can be in advance in substrate base
One layer of buffer layer is formed on plate, and then polysilicon layer 400 is set on buffer layer.
S33: channel doping is carried out to polysilicon layer.
In the present embodiment, polysilicon layer 400 is lightly doped using N type dopant, to adjust thin film transistor (TFT) 900
Leakage current and cut-in voltage.Wherein, as shown in Figure 5 to the schematic diagram after the progress channel doping of polysilicon layer 400.
S34: heavy doping is carried out to source region and drain region.
N-type heavy doping further carried out to source region 402 and drain region 403, in the present embodiment, N-type heavy doping refers to
P (phosphorus) atom is injected to source region 402 and drain region 403.Wherein, N is carried out to source region 402 and drain region 403
Schematic diagram after type heavy doping is as shown in Figure 6.
S35: gate metal layer is set on channel region.
As shown in fig. 7, gate metal layer 700 is arranged on channel region 401, gate metal layer 700 is used to form film
The grid of transistor 900.In other embodiments, gate insulating layer (not shown) can be preset on polysilicon layer 400, so
Gate metal layer 700 is set on gate insulating layer afterwards, and gate metal layer 700 is correspondingly arranged on polysilicon layer 400
Channel region 401 on, it is preferred that the area of gate metal layer 700 be less than or equal to channel region 401 area.Grid is exhausted
Edge layer corresponds to source region 402 and the position of drain region 403 and is provided with through-hole, so that the source electrode being subsequently formed and drain electrode
By the through-hole on polysilicon layer 400 source region 402 and drain region 403 be electrically connected.Wherein, gate metal layer 700
The low doped region 701 of two sides formation thin film transistor (TFT) 900.
S36: interlayer insulating film is set in gate metal layer.
As shown in figure 8, interlayer insulating film (not shown) is further arranged in gate metal layer 700, wherein layer insulation
Layer covering gate metal layer 700 simultaneously extend on polysilicon layer 400, and interlayer insulating film correspond to source region 402 and
Through-hole 800 is arranged in the position of drain region 403, so that the source electrode and drain electrode that are subsequently formed pass through the through-hole 800 and polysilicon
Source region 402 and drain region 403 on layer 400 are electrically connected.
Wherein, the edge at the turning 405 after cutting no more than through-hole 800 edge, as shown in figure 8, turning 405 is separate
Position of the farthest point B in 401 edge of channel region no more than 800 edge A line of through-hole.
In other embodiments, if being previously provided with gate insulating layer on polysilicon layer 400, gate insulating layer leads to
Hole and the position of through-hole 800 on interlayer insulating film are correspondingly arranged, to facilitate the source electrode being subsequently formed and drain electrode to pass through gate insulator
Layer through-hole and interlayer insulating film on through-hole 800 on polysilicon layer 400 source region 402 and drain region 403 be electrically connected.
S37: source-drain electrode metal layer is set on source region and drain region.
Source-drain electrode metal layer is further set on the source region 402 and drain region 403 after N-type heavy doping
901, source-drain electrode metal layer 901 is used to form source electrode and the drain electrode of thin film transistor (TFT) 900, and the source electrode and drain electrode pass through interlayer
On insulating layer by being electrically connected respectively with source region 402 and drain region 403.Wherein, method system through this embodiment
The structural schematic diagram of the thin film transistor (TFT) 900 obtained is as shown in Figure 9.
In the present embodiment, thin film transistor (TFT) 900 is carrying out ditch to polysilicon layer 400 after forming polysilicon layer 400
Before road doping, the turning 404 on the source region 402 and drain region 403 on polysilicon layer 400 is cut and cut
Angle, and in other embodiments, the cutting operation at turning 404 can be carried out after forming polysilicon layer 400, to turning 404
Cutting operation and formed polysilicon layer 400 after other steps between execution sequence this is not restricted.Also, at it
In his embodiment, turning, preparation process and above-described embodiment only can be formed on source region 402 or drain region 403
Preparation process it is similar, therefore not to repeat here.
Therefore, the thin film transistor (TFT) 900 of the present embodiment passes through the source region 402 and drain region to polysilicon layer 400
403 perpendicular corners 404 carry out cutting and top rake, form oblique angle 405, and make oblique angle and 401 edge of channel region away from
From the distance between the turning and 401 edge of channel region being greater than before cutting, so that thin film transistor (TFT) 900 is in processing procedure
Make that process deviation occurs, as shown in Figure 10, when thin film transistor (TFT) 100 is in process deviation, such as source region 402 and drain region
403 deviate to the left in N-type heavy doping, therefore, so that the subsequent source-drain electrode formed in source region 402 and drain region 403
Metal layer 901 also deviates to the left accordingly, and left side will expose source region 402 of the part Jing Guo N-type heavy doping, and due to turning
Angle be by cutting and top rake formed oblique angle 405, therefore, the gross area of low doped region 701 not the amount of being altered or varied compared with
It is small, amplitude of variation in error range so that total conducting resistance between source electrode and drain electrode is constant or the change of total conducting resistance
Change in reasonable error range, to effectively improve what thin film transistor (TFT) 900 in the prior art was generated in process deviation
Conducting resistance unbalance.
Turning before cutting in the present embodiment is perpendicular corners 404, and the turning after cutting is oblique angle 405, is actually cut
Cut front and back turning shape can according to need depending on.The distance between turning 405 and 401 edge of channel region in the present embodiment
Be defined as in turning 405 apart from 401 edge of channel region it is farthest a little the distance between with 401 edge of channel region, at it
It can also be using the distance between the midpoint at turning 405 and 401 edge of channel region as turning 405 and channel region in his embodiment
The distance between 401 edge of domain.
The present invention also provides a kind of thin film transistor (TFT)s 900, as shown in figure 9, the thin film transistor (TFT) 900 of the present embodiment is using upper
The preparation method for stating the thin film transistor (TFT) 900 of embodiment is made, and details are not described herein.
The present invention also provides a kind of narrow frame display panels, as shown in figure 11, the narrow frame display panel 110 of the present embodiment
Including array substrate 130, color membrane substrates 120 and the liquid crystal layer 140 being arranged between array substrate 130 and color membrane substrates 120, battle array
Column substrate 130 is including being the revealed thin film transistor (TFT) 900 of above-described embodiment, and details are not described herein.
In conclusion thin film transistor (TFT) of the invention is in processing procedure, by polysilicon layer source region and/or leakage
The turning in polar region domain is cut, so that the turning after cutting is greater than turning and ditch before cutting at a distance from channel region edge
The distance between road edges of regions is effectively improved film crystal to realize under the premise of not changing display panel size
The problem that conducting resistance of the pipe in process deviation between source electrode and drain electrode is unbalance.
Mode the above is only the implementation of the present invention is not intended to limit the scope of the invention, all to utilize this
Equivalent structure or equivalent flow shift made by description of the invention and accompanying drawing content, it is relevant to be applied directly or indirectly in other
Technical field is included within the scope of the present invention.
Claims (10)
1. a kind of preparation method of thin film transistor (TFT) characterized by comprising
Underlay substrate is provided；
Polysilicon layer is formed on the underlay substrate, the polysilicon layer includes channel region, source region and drain region
There are turnings for domain, the source region and/or the drain region；
Channel doping is carried out to the polysilicon layer；
Heavy doping is carried out to the source region and the drain region；
Gate metal layer is set on the channel region；
Source-drain electrode metal layer is set on the source region and the drain region；
Wherein, further comprise: the turning is cut, so that the turning and the channel region edge after cutting
Distance is greater than the distance between turning and described channel region edge before cutting.
2. preparation method according to claim 1, which is characterized in that the step of cutting turning packet
It includes:
Cutting and top rake are carried out to the turning, to form oblique angle.
3. preparation method according to claim 1, which is characterized in that gate metal layer is arranged on the channel region
After step, the method further includes:
Interlayer insulating film is set in the gate metal layer, and the interlayer insulating film covers the gate metal layer and extends to
On the polysilicon layer.
4. preparation method according to claim 3, which is characterized in that the method further includes:
Through-hole is set on the interlayer insulating film, and the source-drain electrode metal layer passes through the through-hole and the source region and institute
State drain region connection.
5. preparation method according to claim 1, which is characterized in that described to the source region and the drain region
Carry out heavy doping the step of include:
N-type heavy doping is carried out to the source region and the drain region.
6. a kind of thin film transistor (TFT) characterized by comprising
Underlay substrate；
Polysilicon layer is set on the underlay substrate, and the polysilicon layer includes channel region, source region and drain region
Domain；
Gate metal layer is set on the channel region；
Source-drain electrode metal layer is set on the source region and the drain region；
Wherein there is the turning after cutting in the source region and/or the drain region, and the turning after the cutting with
The distance between described channel region edge is greater than the distance between turning and described channel region edge before cutting.
7. thin film transistor (TFT) according to claim 6, which is characterized in that the turning after the cutting is oblique angle.
8. thin film transistor (TFT) according to claim 6, which is characterized in that the thin film transistor (TFT) further includes layer insulation
Layer, the interlayer insulating film cover the gate metal layer and extend on the polysilicon layer.
9. thin film transistor (TFT) according to claim 8, which is characterized in that be provided with through-hole, institute on the interlayer insulating film
Source-drain electrode metal layer is stated to connect by the through-hole with the source region and the drain region.
10. a kind of narrow frame display panel, which is characterized in that including film crystal described in any one of claim 6 to 9
Pipe.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101256959A (en) * | 2007-02-28 | 2008-09-03 | 国际商业机器公司 | Fin type FET and manufacturing method thereof |
| CN102365740A (en) * | 2009-01-27 | 2012-02-29 | 新思科技有限公司 | Boosting transistor performance with non-rectangular channels |
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| JP5672785B2 (en) * | 2010-06-15 | 2015-02-18 | 富士通株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| KR20140108026A (en) * | 2013-02-28 | 2014-09-05 | 삼성디스플레이 주식회사 | Thin film semiconductor device, organic light emitting display, and method of manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101256959A (en) * | 2007-02-28 | 2008-09-03 | 国际商业机器公司 | Fin type FET and manufacturing method thereof |
| CN102365740A (en) * | 2009-01-27 | 2012-02-29 | 新思科技有限公司 | Boosting transistor performance with non-rectangular channels |
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