CN106093884A - A kind of manifold relevant treatment implementation method of based on FPGA of improvement - Google Patents
A kind of manifold relevant treatment implementation method of based on FPGA of improvement Download PDFInfo
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- CN106093884A CN106093884A CN201610377929.5A CN201610377929A CN106093884A CN 106093884 A CN106093884 A CN 106093884A CN 201610377929 A CN201610377929 A CN 201610377929A CN 106093884 A CN106093884 A CN 106093884A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/28—Details of pulse systems
- G01S7/285—Receivers
- G01S7/295—Means for transforming co-ordinates or for evaluating data, e.g. using computers
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/28—Details of pulse systems
- G01S7/2806—Employing storage or delay devices which preserve the pulse form of the echo signal, e.g. for comparing and combining echoes received during different periods
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/35—Details of non-pulse systems
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Abstract
A kind of manifold relevant treatment implementation method of based on FPGA of improvement, first treat relevant treatment signal and carry out orthogonal transformation, same or computing, obtain together or binary adder after result data, will be used respectively to obtain adder output data, then counter cycle count is made, adder exports data in data, RAM block input as accumulator, obtain accumulation result data and as data in new RAM block, finally when counting is equal to the time of integration, the result of calculation of accumulator is exported as multichannel associated processing outcomes.The inventive method by carrying out 1bit additive operation, binary adder packet to related data, compared with prior art, while simplifying FPGA arithmetic logic, also reduce the occupancy of logical resource in FPGA, when input signal way is more, the treatment effeciency of FPGA can be significantly improved, there is preferable applied value.
Description
Technical field
The present invention relates to Space Microwave remote sensing technology field, the relevant place of the multichannel based on FPGA of a kind of improvement
Reason implementation method.
Background technology
Digital correlator is parts the most key in Ocean Salinity explorer satellite microwave radiometer, and it completes four
Stocks vector parameters is measured, and provides input for data inversion, and microwave radiometer application is had decisive role.When ocean salt
During degree explorer satellite microwave radiometer work, microwave radiometer antenna battle array main beam points to and is observed ground or sea, antenna array
Receive the radiant flux of ground or radiation from sea surface, cause the change of antenna receiving signal energy.Antenna receiving signal is through just
Handing over mode coupler to be divided into V, H two-way, the receiver front end docking collection of letters number to reach optical module after being amplified, optical sender is by microwave
Signal is modulated to optical signal, and the optical demodulator in fiber-optic transfer to cabin, center, optical signal is reduced to microwave by optical demodulator
Signal, subsequently into receiver, filtered, downconvert to intermediate frequency.The AD device of digital correlator carries out modulus to intermediate-freuqncy signal
Conversion, the processing apparatus FPGA of digital correlator completes relevant treatment to the digital signal obtained.
Microwave current radiometer, in order to obtain sufficiently high ground resolution, the most all uses two-dimensional synthetic aperture to observe skill
Art, utilize the two dimension small aperture antenna big observation bore of synthesis, it is to avoid the weight of large aperture antenna, volume, scanning are to carrying
Difficulty in terms of the requirement of platform and processing, efficiently solves the contradiction between spatial resolution and observation swath, it is easy to spaceborne
Application.The element number of existing two-dimensional synthetic aperture array can reach dozens or even hundreds of, and therefore back-end digital correlator is multiple
Miscellaneous degree, power consumption and volume are also significantly increased, and also make the aspects such as digital correlator hardware development, software debugging, performance test
Difficulty increase, solving the correlator quantity multiplication problem that a large amount of crosscorrelation brings is comprehensive study aperture microwave radiometer
Crucial.
The multiplication of correlator quantity, certainty of measurement and the raising of bandwidth requirement brought along with a large amount of crosscorrelations, tradition spoke
The analog correlator penetrating meter employing can not meet requirement.Digital correlator, compared with analog correlator, is mainly characterized by profit
Realize full parellel wideband digital relevant treatment with super large-scale integration, and digital correlator uses FPGA design, can be anti-
The important parameters, more motility such as multiple erasable, amendment accumulation interval.The research of digital correlator at present is concentrated mainly on raising AD
The aspects such as sampling rate, raising FPGA processing speed, such as " complete polarization microwave radiometer system high speed digital correlator sets
Meter " devise a kind of digital correlator based on four tunnel input signals, AD sample rate can reach 360Mhz；" Synthetic Aperture Microwave spoke
Penetrate meter second order quantization digital correlator research " method that have employed second order quantization digital signal, the impact on signal to noise ratio is carried out
Analysis verification；" synthetic aperture radiometer multichannel high-order digit complex correlator project study " have employed lack sampling, Digital Down Convert,
The methods such as filtering extraction reduce the requirement to FPGA processing speed, but the method has certain shadow to synthetic aperture directional diagram
Ring, be only applicable to the situation that radiometer system index request is the highest, it is therefore desirable to a kind of new can preferably solution is patrolled on FPGA sheet
The multichannel relevant treatment implementation method of the contradiction volume between resources occupation rate and computing unit quantity.
Summary of the invention
Present invention solves the technical problem that and be: overcome the deficiencies in the prior art, it is provided that be a kind of by related data is entered
Row 1bit additive operation, binary adder packet, while simplifying FPGA arithmetic logic, also reduce logic in FPGA
The manifold relevant treatment implementation method based on FPGA of the improvement of the occupancy of resource.
The technical solution of the present invention is: the manifold relevant treatment implementation method based on FPGA of a kind of improvement, including
Following steps:
(1) gather need to carry out the N road signal of relevant treatment after carry out orthogonal transformation and obtain 2N circuit-switched data, to the 2N obtained
Circuit-switched data carries out 1bit quantization, and then to obtain 2N degree of having a lot of social connections be the quantized data of 1bit, then is the quantization of 1bit to 2N degree of having a lot of social connections
Any two paths of data in data carries out same or computing, obtainsDegree of having a lot of social connections is the same of 1bit or result data；
(2) using the i-th tunnel with or result data as the input data of i-th binary adder and carry, obtainIndividual width is the binary adder output data of 4bit, wherein,
(3) rightIndividual binary adder carries out packet and obtainsGroup binary adder, then to often group
Middle binary adder is numbered, and is designated as 0,1,2,3 ... 15, for often organizing binary adder and opening up a degree of depth is respectively
The RAM block of 16bit, using the jth RAM block of jth group adder and correspondence as a minimum calculation unit, wherein,
(4) obtain an enumerator make counter cycle count, using the counting k of enumerator asIndividual
The reading address of RAM block, controlsThe data that the address k of individual RAM block deposits respectively appeared in+1 clock cycle of kth
On the output FPDP of corresponding RAM block, wherein, each circulation of enumerator includes 16 cycles, the counting k=0 of computer, 1,
2,3 ... 15, the data that address 15 is deposited the 0th cycle in lower whorl circulates occurs in the output FPDP of RAM block, address k
Represent the k+1 layer of RAM block；
(5) when when being counted as k of enumerator ,-1 binary adder of kth in reading jth group minimum calculation unit
Output data, and it is designated as DATA (j), then resetThe binary adder being read in group minimum calculation unit, its
In, when the value of computer is 0, the 15th binary adder defeated in jth group minimum calculation unit in wheel circulation in reading
Going out data, when the value of enumerator is 1, in reading, in wheel circulation, in jth group minimum calculation unit, the 0th binary adder is defeated
Go out data；
(6) designIndividual accumulator, by the output data of RAM block in jth group minimum calculation unit in step (4)
Output data on port, DATA (j), as the input of jth accumulator, obtainIndividual accumulation result data, wherein,
In minimum calculation unit, the initial value of RAM block is 0；
(7) when when being counted as k of enumerator, DATA (j) is written to the address of RAM block in jth group minimum calculation unit
K-2, wherein, when enumerator when being counted as 0, by take turns DATA (j) in circulation and be written in jth group minimum calculation unit
The address 14 of RAM block, when the value of enumerator is 1, by take turns DATA (j) in circulation and be written in jth group minimum calculation unit
The address 15 of RAM block；
(8) make counter cycle count, when the gate time of enumerator is equal to the time of integration, the calculating of accumulator is tied
Fruit exports as multichannel associated processing outcomes, and willThe clearing of RAM in group minimum calculation unit.
The described method carrying out orthogonal transformation is Hilbert transform method.
Described binary adder output data use the Binary Counter IP kernel in FPGA to realize.
The RS485 interface that the result of calculation of described accumulator is connected by FPGA exports.
The described time of integration is much larger than the clock cycle.
Described width be the width of RAM block be 32bit.
The width of described enumerator is not less than 4bit.
Frequency corresponding to described clock cycle is 60MHZ.
Present invention advantage compared with prior art is:
(1) the inventive method is by using FPGA binary adder to carry out 1bit additive operation related data, with existing
There is technology to compare, while simplifying FPGA arithmetic logic, also reduce the occupancy of logical resource in FPGA；
(2) the inventive method is compared with prior art, by being grouped binary adder, decreases multichannel phase
The control signal that pass needs in processing, simplifies the program of FPGA, when input signal way is more, can significantly improve FPGA's
Treatment effeciency；
(3) the inventive method is by opening up RAM memory space for each binary adder and entering RAM memory space
The means that road wheel is ask, solve the resources occupation rate waste problem that in prior art, big bit wide adder is caused；
(4) the inventive method is compared with prior art, by using RAM resource to replace more nervous logic in FPGA
Resource, when solving multiple signals input, FPGA calculates the problem that logic processing capability is not enough, has preferable applied value.
Accompanying drawing explanation
Fig. 1 is digital correlator fundamental diagram in the inventive method；
Fig. 2 is the FPGA multichannel relevant treatment implementation method flow chart of a kind of improvement of the present invention.
Detailed description of the invention
Being illustrated in figure 1 digital correlator fundamental diagram, multiple AD devices are simultaneously laggard to multichannel if signal sampling
Row number filtering, IQ orthogonal transformation realize Digital Down Convert, and the result of Digital Down Convert carries out 1bit, and to have quantified signal pre-
Process and deliver to multiple correlation computing unit.Multiple correlation computing unit is mainly made up of multiplier and integrator, and wherein, multiplier is complete
Become is same or computing, and integrator completes quantization level discretization in time and the tiring out along time shaft on high level
Adding, each orthogonal signalling carry out multiple correlation process with other orthogonal signalling respectively, export multiple correlation result to host computer
I.e. obtain the complex correlation value that any two AD passage is corresponding.
The present invention is directed to the deficiencies in the prior art, propose the FPGA multichannel relevant treatment implementation method of a kind of improvement, gram
Take the limitation of existing relevant treatment implementation method, solve logical resource occupancy and computing unit quantity on FPGA sheet
Between contradiction, compared with prior art, the inventive method realize simple, reliability high, for the actual application of digital correlator
Lay key foundation, below in conjunction with the accompanying drawings the inventive method is described in detail.The inventive method includes as follows as shown in Figure 2
Step:
(1) make the signal that microwave radiometer antenna battle array receives through orthomode coupler, optical module, receiver, simulation
Wave filter, downconvert to intermediate-freuqncy signal, i.e. obtain the input signal of digital correlator, make the AD front-end collection N of digital correlator
Road IF input signals, use FPGA to AD front-end collection to N circuit-switched data use Hilbert transform method just carrying out respectively
Alternation gets 2N circuit-switched data in return, the 2N circuit-switched data obtained carries out 1bit quantization, and then obtains the quantization that 2N degree of having a lot of social connections is 1bit
Data, more any two paths of data in the quantized data that 2N degree of having a lot of social connections is 1bit is carried out same or (xnor) computing, obtain
Degree of having a lot of social connections is the same of 1bit or result data.
(2) using the i-th tunnel that step (1) obtains with or result data as the input number of i-th binary adder
According to and carry,ObtainIndividual width is the adder output data of 4bit, wherein, binary system
Adder uses the Binary Counter IP kernel in FPGA to realize, and input data bit width is 1bit, a width of 1bit of carry digit,
Output data width is 4bit.
(3) rightIndividual binary adder is grouped, and every 16 adders, as one group, obtainGroup adds
Musical instruments used in a Buddhist or Taoist mass, is numbered adder in often group, is designated as 0,1,2,3 ... 15, then opens up a degree of depth for often group adder and is
16bit, width are the RAM block of 32bit, totalIndividual RAM block, the initial value of each RAM block is zero, jth group adder
And the jth RAM block of correspondence is as a minimum calculation unit,When the middle frequency gathered
According to during for N road, minimum calculation unit number is
(4) design one enumerator not less than 4bit, the counting k of enumerator every 16 clock cycle is added to 15, k by 0
=0,1,2,3 ... 15, counter cycle count, arrives k as 1The reading address of individual RAM block, the ground of jth RAM block
The data that location k deposits will occur on the output FPDP of RAM block in+1 clock cycle of kth, and wherein, address 15 is deposited
The 0th cycle in lower whorl circulation is occurred in the output FPDP of RAM block by data, and address k represents the k+1 layer of RAM block.
(5) when the value of step (4) Counter is k, the most rightKth-1 in group minimum calculation unit
Binary adder output conducts interviews, and obtains-1 binary adder output data of individual kth, jth group is minimum
In computing unit, binary adder output data are designated as DATA (j), arrive 1 simultaneouslyGroup minimum calculation unit in interviewed
The binary adder asked be zeroed out operation, wherein, when the value of computer is 0, on take turns in circulationOrganize subtotal
Calculate the 15th binary adder output in unit to conduct interviews, when the value of enumerator is 1, on take turns in circulationGroup
In minimum calculation unit, the 0th binary adder output conducts interviews.
(6) designIndividual accumulator, wherein, the first via of jth accumulator inputs the jth obtained for step (4)
The output data of RAM block, the second tunnel input is jth minimum calculation unit output DATA (j) obtained in step (5), wherein,
The first via input data width of accumulator is 32bit, and the second tunnel input data width is 4bit, and output data width is
32bit。
(7), when the value of step (4) Counter is k, making k is 1 to arriveThe write address of individual RAM block, writes DATA (j)
To the address k-2 of jth RAM block, wherein, when the value of enumerator is 0, by take turns DATA (j) in circulation and be written to jth
The address 14 of RAM block, when the value of enumerator is 1, by take turns DATA (j) in circulation and be written to the address 15 of jth RAM block,
The data width of writing of RAM block is 32bit.
(8) make counter cycle count, when arriving the time of integration, the result of calculation of accumulator is correlated with as multichannel
Result is exported by the RS485 interface that FPGA connects and incites somebody to actionThe storage content of individual RAM resets, wherein, and the time of integration
Much larger than the clock cycle, frequency corresponding to clock cycle is 60MHZ.
The content not being described in detail in description of the invention belongs to the known technology of those skilled in the art.
Claims (8)
1. the manifold relevant treatment implementation method based on FPGA improved, it is characterised in that comprise the steps:
(1) gather need to carry out the N road signal of relevant treatment after carry out orthogonal transformation and obtain 2N circuit-switched data, to the 2N way obtained
According to carrying out 1bit quantization, and then to obtain 2N degree of having a lot of social connections be the quantized data of 1bit, then is the quantized data of 1bit to 2N degree of having a lot of social connections
In any two paths of data carry out with or computing, obtainDegree of having a lot of social connections is the same of 1bit or result data；
(2) using the i-th tunnel with or result data as the input data of i-th binary adder and carry, obtain
Individual width is the binary adder output data of 4bit, wherein,
(3) rightIndividual binary adder carries out packet and obtainsGroup binary adder, then in often group two
System adder is numbered, and is designated as 0,1,2,3 ... 15, is 16bit for often organize binary adder opening up a degree of depth respectively
RAM block, using the jth RAM block of jth group adder and correspondence as a minimum calculation unit, wherein,
(4) obtain an enumerator make counter cycle count, using the counting k of enumerator asIndividual RAM block
Reading address, controlThe data that the address k of individual RAM block deposits respectively appear in correspondence in+1 clock cycle of kth
On the output FPDP of RAM block, wherein, each circulation of enumerator includes 16 cycles, the counting k=0 of computer, 1,2,
3 ... 15, the data that address 15 is deposited the 0th cycle in lower whorl circulates occurs in the output FPDP of RAM block, address k generation
The k+1 layer of table RAM block；
(5) when when being counted as k of enumerator, the output of-1 binary adder of kth in reading jth group minimum calculation unit
Data, and it is designated as DATA (j), then resetThe binary adder being read in group minimum calculation unit, wherein,
When the value of computer is 0, the output number of the 15th binary adder in jth group minimum calculation unit during wheel circulates in reading
According to, when the value of enumerator is 1, in reading, in wheel circulation, in jth group minimum calculation unit, the 0th binary adder exports number
According to；
(6) designIndividual accumulator, by the output FPDP of RAM block in jth group minimum calculation unit in step (4)
On output data, DATA (j) as the input of jth accumulator, obtainIndividual accumulation result data, wherein, minimum
In computing unit, the initial value of RAM block is 0；
(7) when when being counted as k of enumerator, DATA (j) is written to the address k-2 of RAM block in jth group minimum calculation unit,
Wherein, when enumerator when being counted as 0, by take turns DATA (j) in circulation and be written to RAM block in jth group minimum calculation unit
Address 14, when the value of enumerator is 1, by take turns DATA (j) in circulation and be written to RAM block in jth group minimum calculation unit
Address 15；
(8) make counter cycle count, when the gate time of enumerator is equal to the time of integration, the result of calculation of accumulator is made
Export for multichannel associated processing outcomes, and willThe clearing of RAM in group minimum calculation unit.
The manifold relevant treatment implementation method based on FPGA of a kind of improvement the most according to claim 1, it is characterised in that:
The described method carrying out orthogonal transformation is Hilbert transform method.
The manifold relevant treatment implementation method based on FPGA of a kind of improvement the most according to claim 1 and 2, its feature exists
In: described binary adder output data use the Binary Counter IP kernel in FPGA to realize.
The manifold relevant treatment implementation method based on FPGA of a kind of improvement the most according to claim 3, it is characterised in that:
The RS485 interface that the result of calculation of described accumulator is connected by FPGA exports.
The manifold relevant treatment implementation method based on FPGA of a kind of improvement the most according to claim 1 and 2, its feature exists
In: the described time of integration is much larger than the clock cycle.
The manifold relevant treatment implementation method based on FPGA of a kind of improvement the most according to claim 1 and 2, its feature exists
In: described width be the width of RAM block be 32bit.
The manifold relevant treatment implementation method based on FPGA of a kind of improvement the most according to claim 1 and 2, its feature exists
In: the width of described enumerator is not less than 4bit.
The manifold relevant treatment implementation method based on FPGA of a kind of improvement the most according to claim 1 and 2, its feature exists
The frequency corresponding in: described clock cycle is 60MHZ.
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Cited By (6)
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| CN107015063A (en) * | 2017-03-21 | 2017-08-04 | 中国科学院国家天文台 | Wide band multi-channel Correlation receiver and method of reseptance |
| CN110907933A (en) * | 2019-11-26 | 2020-03-24 | 西安空间无线电技术研究所 | Distributed-based synthetic aperture correlation processing system and method |
| CN113702804A (en) * | 2021-07-26 | 2021-11-26 | 西安空间无线电技术研究所 | Correlation error correction method in multi-channel digital correlator |
| CN113702804B (en) * | 2021-07-26 | 2024-02-09 | 西安空间无线电技术研究所 | Correlation error correction method in multichannel digital correlator |
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