CN106066823B - A kind of mbist clock optimization method and device - Google Patents
A kind of mbist clock optimization method and device Download PDFInfo
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- CN106066823B CN106066823B CN201610348382.6A CN201610348382A CN106066823B CN 106066823 B CN106066823 B CN 106066823B CN 201610348382 A CN201610348382 A CN 201610348382A CN 106066823 B CN106066823 B CN 106066823B
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/27—Built-in tests
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Abstract
The invention discloses a kind of mbist clock optimization method and devices, the described method comprises the following steps: clock provides unit and provides clock first；Then operational mode configuration of described dispensing unit logic circuit operational mode, the operational mode include functional mode and test pattern；When the operational mode of operational mode configuration of described dispensing unit is functional mode, logic circuit control unit provides clock to clock provided by unit and is sent to functional logic circuit, and closes test logic circuit；When the operational mode of operational mode configuration of described dispensing unit is test pattern, logic circuit control unit provides clock to clock provided by unit and is sent to test logic circuit, and closing function logic circuit.Since functional logic circuit and test logic circuit are completely independent and separate, when a certain logic circuit is in running order, another logic circuit can be completely closed, and thus greatly reduced power consumption when chip carries out mbist test, enhanced the stability of test.
Description
Technical field
The present invention relates to SOC chip design field, in particular to a kind of mbist clock optimization method and device.
Background technique
MBIST, that is, memory (memory) built-in self-test, is the main test method of memory inside current chip, it is logical
It crosses and test vector generation circuit and comparison circuit is embedded into chip interior, only by the simple several control signals in periphery, open
It moves internal memory and tests circuit, the automatic test realized to memory is automatic to export test and comparison knot after test
Fruit.
Memory tests the clock that the work clock of circuit is all direct sharing functionality logic module at present, and what is done so is good
Place is the clock that can be directly multiplexed functional circuit, does not increase additional timing topology, but this also results in and is carrying out memory survey
When examination, the clock of other non-mbist tests circuit (i.e. function mode logic block circuit) is also ceaselessly being overturn, when tested
Chip-scale is bigger, when test frequency is higher, often will appear power consumption it is too high, test electricity shortage situations such as, influence to survey
The stability of examination.
Previous technology, the clock gating unit being inserted into such as synthesis phase (clock gating cell) can allow function
Many logics in energy module are when mbist is tested, in a dormant state, but since mbist has been multiplexed function logic
Clock Tree (clock tree), the Clock Tree part for causing them public can not close, during the test due to Clock Tree
It can ceaselessly be overturn always, and be positively correlated with working frequency, so this part logic can bring ratio when mbist is tested
Biggish power consumption；Simultaneously as when growing Clock Tree, it is corresponding if containing many memory in soc
Mbist test logic also accordingly increases, when mbist logic occupies certain ratio, such as more than total logic 5% when
It waits, can significantly increase the Clock Tree length of functional logic circuit.Cause under function operation mode, the power consumption on Clock Tree is opened
Pin increases, and increases the power consumption of the circuit under function operation mode.
Summary of the invention
For this reason, it may be necessary to a kind of technical solution of mbist clock optimization be provided, to solve existing chip since mbist is surveyed
Examination has been multiplexed the work clock of functional logic circuit, leads to when carrying out mbist test that power consumption is big, test electricity shortage, tests
The problems such as unstable.
To achieve the above object, a kind of mbist clock optimization device is inventor provided, described device includes that clock provides
Unit, operational mode configuration unit, logic circuit control unit, functional logic circuit and test logic circuit；The clock mentions
It is connect for unit with operational mode configuration unit, the operational mode configuration unit is connect with logic circuit control unit, described
Logic circuit control unit is connect with functional logic circuit, and the logic circuit control unit is connect with test logic circuit；
The clock provides unit for providing clock；
The operational mode configuration unit is used for configuration logic operational mode, and the operational mode includes functional mode
And test pattern；
When the operational mode of operational mode configuration of described dispensing unit be functional mode when, logic circuit control unit be used for by when
Clock provides clock provided by unit and is sent to functional logic circuit, and closes test logic circuit；
When the operational mode of operational mode configuration of described dispensing unit be test pattern when, logic circuit control unit be used for by when
Clock provides clock provided by unit and is sent to test logic circuit, and closing function logic circuit.
Further, the quantity of the clock offer unit is multiple, and described device further includes clock selecting unit, described
Clock provides unit and connect with clock selecting unit, and the clock selecting unit, which is used to provide in unit from multiple clocks, selects one
Clock provides unit, and the operational mode configured according to operational mode configuration unit, provides selected clock to unit institute
The clock of offer is sent to the corresponding logic circuit of operational mode of configuration.
Further, multiple clocks provide the clock for the different clock frequencies that unit is provided respectively by gradient.
Further, it is PLL that the clock, which provides the clock source of unit,.
Inventor additionally provides a kind of mbist clock optimization method, and the method is applied to mbist clock and optimizes device,
Described device includes that clock provides unit, operational mode configuration unit, logic circuit control unit, functional logic circuit and test
Logic circuit；The clock provides unit and connect with operational mode configuration unit, the operational mode configuration unit and logic electricity
The connection of road control unit, the logic circuit control unit connect with functional logic circuit, the logic circuit control unit and
Test logic circuit connection；It the described method comprises the following steps:
Clock provides unit and provides clock；
Operational mode configuration of described dispensing unit logic circuit operational mode, the operational mode include functional mode and test mould
Formula；
When the operational mode of operational mode configuration of described dispensing unit is functional mode, logic circuit control unit mentions clock
It is sent to functional logic circuit for clock provided by unit, and closes test logic circuit；
When the operational mode of operational mode configuration of described dispensing unit is test pattern, logic circuit control unit mentions clock
Test logic circuit, and closing function logic circuit are sent to for clock provided by unit.
Further, the quantity of the clock offer unit is multiple, and described device further includes clock selecting unit, described
Clock provides unit and connect with clock selecting unit；The described method includes:
Clock selecting unit provides in unit from multiple clocks selects a clock to provide unit, and is configured according to operational mode
The operational mode that unit is configured provides selected clock to the operational mode pair that clock provided by unit is sent to configuration
The logic circuit answered.
Further, multiple clocks provide the clock for the different clock frequencies that unit is provided respectively by gradient.
Further, it is PLL that the clock, which provides the clock source of unit,.
Mbist clock optimization method and device described in above-mentioned technical proposal, the method optimize applied to mbist clock
Device, described device include that clock provides unit, operational mode configuration unit, logic circuit control unit, functional logic circuit
With test logic circuit；The clock provides unit and connect with operational mode configuration unit, the operational mode configuration unit and
The connection of logic circuit control unit, the logic circuit control unit are connect with functional logic circuit, the logic circuit control
Unit is connect with test logic circuit；The described method comprises the following steps: clock provides unit and provides clock first；Then run
Mode configuration unit configuration logic operational mode, the operational mode include functional mode and test pattern；When operation mould
When the operational mode of formula configuration of described dispensing unit is functional mode, when logic circuit control unit provides clock provided by unit
Clock is sent to functional logic circuit, and closes test logic circuit；When the operational mode of operational mode configuration of described dispensing unit is to survey
When die trial formula, logic circuit control unit provides clock to clock provided by unit and is sent to test logic circuit, and closes
Functional logic circuit.It is provided since the clock of functional logic circuit and test logic circuit provides unit by clock, so that function
Energy logic circuit and test logic circuit are completely independent and separate, and multiplexing part is not present, thus when chip is in normal function
When under operating mode, test logic circuit can be completely closed；Conversely, when chip is under test pattern, function logic electricity
Road can completely close, and thus greatly reduce power consumption when chip carries out mbist test, enhance the stability of test.
Detailed description of the invention
Fig. 1 is the schematic diagram that the mbist clock that an embodiment of the present invention is related to optimizes device；
Fig. 2 is the flow chart for the mbist clock optimization method that an embodiment of the present invention is related to；
Description of symbols:
101, clock provides unit；
102, operational mode configuration unit；
103, logic circuit control unit；
104, functional logic circuit；
105, logic circuit is tested；
106, clock selecting unit.
Specific embodiment
Technology contents, construction feature, the objects and the effects for detailed description technical solution, below in conjunction with specific reality
It applies example and attached drawing is cooperated to be explained in detail.
DVFS (Dynamic Voltage and Frequency Scaling) dynamic voltage frequency is adjusted, and is a kind of reality
When voltage and frequency regulation technology.Power consumption can be mainly divided into dynamic power consumption and static power in cmos circuitry
Consumption, formula are as follows:
Power=∑ (CV2αf+VIdq)
Wherein C represents the capacitance of load capacitance, and V is operating voltage, and α is the overturning rate under current clock frequency, and f is work
Frequency, I_dq represent quiescent current.What the preceding part of formula represented is dynamic power consumption, and what rear part then represented is static function
Rate consumption.It can be seen that from formula, it is desirable to which reducing dynamic power consumption can set about from C, V, α, f, for software often
Regulative mode relates only to two factors of V, f, i.e., in the case where clock frequency is certain, need reduces clock as far as possible is turned over
Rate of rotation, to reduce circuit power consumption.
Referring to Fig. 1, optimizing the schematic diagram of device for the mbist clock that an embodiment of the present invention is related to.Described device
Unit 101, operational mode configuration unit 102, logic circuit control unit 103,104 and of functional logic circuit are provided including clock
Test logic circuit 105；The clock provides unit 101 and connect with operational mode configuration unit 102, the operational mode configuration
Unit 102 is connect with logic circuit control unit 103, and the logic circuit control unit 103 connects with functional logic circuit 104
It connects, the logic circuit control unit 103 is connect with test logic circuit 105；
The clock provides unit 101 for providing clock；
The operational mode configuration unit 102 is used for configuration logic operational mode, and the operational mode includes function
Mode and test pattern；
When the operational mode that operational mode configuration unit 102 configures is functional mode, logic circuit control unit 103 is used
It is sent to functional logic circuit 104 in providing clock to clock provided by unit 101, and closes test logic circuit 105；
When the operational mode that operational mode configuration unit 102 configures is test pattern, logic circuit control unit 103 is used
Test logic circuit 105, and closing function logic circuit 104 are sent in providing clock to clock provided by unit 101.
When using mbist clock optimization device, clock provides unit 101 and provides clock first.In the present embodiment,
The clock source that the clock provides unit is PLL.Phaselocked loop (PLL) is a kind of feed circuit, and effect is so that on circuit
The Phase synchronization of clock and a certain external clock.Phase of the PLL by comparing external signal and the phase by voltage controlled crystal oscillator (VCXO)
Position is synchronous to realize, during comparison, phase-locked loop circuit can constantly adjust local crystalline substance according to the phase of external signal
The clock phase of vibration, until the Phase synchronization of two signals.
Then 102 configuration logic operational mode of operational mode configuration unit.The operational mode includes functional mode
And test pattern, functional mode refer to that chip logic is in normal operating conditions, test pattern refers to that chip logic is in test
State.Preferably, operational mode configuration unit can be clock selector, when it receives the first signal, by logic circuit
Operational mode is configured to functional mode；When its receive second signal when, by the operational mode of logic circuit be configured to but mode.
Preferably, the first signal is 0, second signal 1.
When the operational mode of operational mode configuration of described dispensing unit is functional mode, logic circuit control unit mentions clock
It is sent to functional logic circuit for clock provided by unit, and closes test logic circuit；When operational mode configuration unit is matched
When the operational mode set is test pattern, logic circuit control unit provides clock to clock provided by unit and is sent to test
Logic circuit, and closing function logic circuit.Since the clock of functional logic circuit and test logic circuit is provided by clock
Unit provides, so that functional logic circuit and test logic circuit are completely independent and separate, multiplexing part is not present, thus works as core
When piece is under normal functional operation mode, test logic circuit can be completely closed；Conversely, when chip is under test pattern
When, functional logic circuit can completely close, and thus greatly reduce power consumption when chip carries out mbist test, enhance survey
The stability of examination.
In the present embodiment, the quantity of the clock offer unit 101 is multiple, and described device further includes clock selecting
Unit 106, the clock provide unit 101 and connect with clock selecting unit 106, and the clock selecting unit 106 is used for from more
A clock, which provides, selects a clock to provide unit, and the operational mode configured according to operational mode configuration unit 102 in unit,
There is provided selected clock to the corresponding logic circuit of operational mode that clock provided by unit 101 is sent to configuration.It is preferred that
, multiple clocks provide the clock for the different clock frequencies that unit is provided respectively by gradient.Such as multiple clocks provide units according to
The working frequency of the clock of secondary offer is 50MHZ, 100MHZ, 150MHZ etc., to adapt to the needs of different performance chip, is met
Demand of the chip interior different function module to mbist test clock.
And a kind of mbist clock optimization method is inventor provided, referring to Fig. 2, being related to for an embodiment of the present invention
And mbist clock optimization method flow chart.The method is applied to mbist clock and optimizes device, when described device includes
Clock provides unit, operational mode configuration unit, logic circuit control unit, functional logic circuit and test logic circuit；It is described
Clock provides unit and connect with operational mode configuration unit, and the operational mode configuration unit and logic circuit control unit connect
It connects, the logic circuit control unit is connect with functional logic circuit, the logic circuit control unit and test logic circuit
Connection；It the described method comprises the following steps:
It initially enters step S201 clock and unit offer clock is provided.In the present embodiment, the clock provides unit
Clock source be PLL.Phaselocked loop (PLL) is a kind of feed circuit, effect be so that clock on circuit and it is a certain external when
The Phase synchronization of clock.PLL is synchronous to realize with the phase by voltage controlled crystal oscillator (VCXO) by comparing the phase of external signal,
During comparing, phase-locked loop circuit can constantly adjust the clock phase of local crystal oscillator according to the phase of external signal, until
The Phase synchronization of two signals.
Then enter step S202 operational mode configuration of described dispensing unit logic circuit operational mode.The operational mode includes
Functional mode and test pattern, functional mode refer to that chip logic is in normal operating conditions, and test pattern refers to chip logic
In test mode.Preferably, operational mode configuration unit can be that clock selector will be patrolled when it receives the first signal
The operational mode for collecting circuit is configured to functional mode；When it receives second signal, configure the operational mode of logic circuit to
But mode.Preferably, the first signal is 0, second signal 1.
S203 is then entered step when the operational mode of operational mode configuration of described dispensing unit is functional mode, logic circuit
Control unit provides clock to clock provided by unit and is sent to functional logic circuit, and closes test logic circuit.Alternatively,
S204 can be entered step when the operational mode of operational mode configuration of described dispensing unit is test pattern, logic circuit control unit
It provides clock to clock provided by unit and is sent to test logic circuit, and closing function logic circuit.Due to function logic
The clock of circuit and test logic circuit provides unit by clock and provides, so that functional logic circuit and test logic circuit are complete
It is complete independently to separate, multiplexing part is not present, thus when chip is under functional mode, test logic circuit can close completely
It closes；Conversely, functional logic circuit can completely close when chip is under test pattern, thus greatly reduce chip into
Power consumption when row mbist is tested, enhances the stability of test.
In the present embodiment, the quantity of the clock offer unit is multiple, and described device further includes clock selecting list
Member, the clock provide unit and connect with clock selecting unit, which comprises clock selecting unit is provided from multiple clocks
A clock is selected to provide unit in unit, and the operational mode configured according to operational mode configuration unit, when will be selected
Clock provides the corresponding logic circuit of operational mode that clock provided by unit is sent to configuration.Preferably, multiple clocks provide
The clock for the different clock frequencies that unit is provided respectively by gradient.Such as multiple clocks provide the work for the clock that unit successively provides
Working frequency is 50MHZ, 100MHZ, 150MHZ etc., to adapt to the needs of different performance chip, meets chip interior different function
Demand of the module to mbist test clock.
It should be noted that, in this document, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to
Non-exclusive inclusion, so that the process, method, article or the terminal device that include a series of elements not only include those
Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or end
The intrinsic element of end equipment.In the absence of more restrictions, being limited by sentence " including ... " or " including ... "
Element, it is not excluded that there is also other elements in process, method, article or the terminal device for including the element.This
Outside, herein, " being greater than ", " being less than ", " being more than " etc. are interpreted as not including this number；" more than ", " following ", " within " etc. understand
Being includes this number.
It should be understood by those skilled in the art that, the various embodiments described above can provide as method, apparatus or computer program production
Product.Complete hardware embodiment, complete software embodiment or embodiment combining software and hardware aspects can be used in these embodiments
Form.The all or part of the steps in method that the various embodiments described above are related to can be instructed by program relevant hardware come
It completes, the program can store in the storage medium that computer equipment can be read, for executing the various embodiments described above side
All or part of the steps described in method.The computer equipment, including but not limited to: personal computer, server, general-purpose computations
It is machine, special purpose computer, the network equipment, embedded device, programmable device, intelligent mobile terminal, smart home device, wearable
Smart machine, vehicle intelligent equipment etc.；The storage medium, including but not limited to: RAM, ROM, magnetic disk, tape, CD, sudden strain of a muscle
It deposits, USB flash disk, mobile hard disk, storage card, memory stick, webserver storage, network cloud storage etc..
The various embodiments described above are referring to the method according to embodiment, equipment (system) and computer program product
Flowchart and/or the block diagram describes.It should be understood that can be realized by computer program instructions every in flowchart and/or the block diagram
The combination of process and/or box in one process and/or box and flowchart and/or the block diagram.It can provide these computers
Program instruction generates a machine to the processor of computer equipment, so that the finger executed by the processor of computer equipment
It enables and generates to specify in one or more flows of the flowchart and/or one or more blocks of the block diagram
The device of function.
These computer program instructions, which may also be stored in, to be able to guide computer equipment computer operate in a specific manner and sets
In standby readable memory, so that the instruction being stored in the computer equipment readable memory generates the manufacture including command device
Product, command device realization refer in one or more flows of the flowchart and/or one or more blocks of the block diagram
Fixed function.
These computer program instructions can also be loaded into computer equipment, so that executing on a computing device a series of
Operating procedure is to generate computer implemented processing, so that the instruction executed on a computing device is provided for realizing in process
The step of function of being specified in figure one process or multiple processes and/or block diagrams one box or multiple boxes.
Although the various embodiments described above are described, once a person skilled in the art knows basic wounds
The property made concept, then additional changes and modifications can be made to these embodiments, so the above description is only an embodiment of the present invention,
It is not intended to limit scope of patent protection of the invention, it is all to utilize equivalent structure made by description of the invention and accompanying drawing content
Or equivalent process transformation, being applied directly or indirectly in other relevant technical fields, similarly includes in patent of the invention
Within protection scope.
Claims (8)
1. a kind of mbist clock optimizes device, which is characterized in that described device includes that clock provides unit, operational mode configuration
Unit, logic circuit control unit, functional logic circuit and test logic circuit；The clock provides unit and matches with operational mode
Set unit connection, the operational mode configuration unit connect with logic circuit control unit, the logic circuit control unit and
Functional logic circuit connection, the logic circuit control unit are connect with test logic circuit；The test logic circuit and function
Energy logic circuit is mutually indepedent and multiplexing part is not present；
The clock provides unit for providing clock；
The operational mode configuration unit is used for configuration logic operational mode, and the operational mode includes functional mode and survey
Die trial formula；
When the operational mode of operational mode configuration of described dispensing unit is functional mode, logic circuit control unit is for mentioning clock
It is sent to functional logic circuit for clock provided by unit, and closes test logic circuit；
When the operational mode of operational mode configuration of described dispensing unit is test pattern, logic circuit control unit is for mentioning clock
Test logic circuit, and closing function logic circuit are sent to for clock provided by unit.
2. mbist clock as described in claim 1 optimizes device, which is characterized in that the quantity that the clock provides unit is
Multiple, described device further includes clock selecting unit, and the clock provides unit and connect with clock selecting unit, the clock choosing
It selects unit and selects a clock to provide unit for providing in unit from multiple clocks, and configured according to operational mode configuration unit
Operational mode, provide selected clock to the operational mode corresponding logic electricity that clock provided by unit is sent to configuration
Road.
3. mbist clock as claimed in claim 2 optimizes device, which is characterized in that multiple clocks provide unit by gradient point
The clock of the different clock frequencies indescribably supplied.
4. mbist clock as claimed in claim 1 or 2 optimizes device, which is characterized in that the clock provides the clock of unit
Source is PLL.
5. a kind of mbist clock optimization method, which is characterized in that the method is applied to mbist clock and optimizes device, the dress
It sets and provides unit, operational mode configuration unit, logic circuit control unit, functional logic circuit and test logic electricity including clock
Road；The clock provides unit and connect with operational mode configuration unit, and the operational mode configuration unit and logic circuit control
Unit connection, the logic circuit control unit are connect with functional logic circuit, and the logic circuit control unit is patrolled with test
Collect circuit connection；It the described method comprises the following steps:
Clock provides unit and provides clock；
Operational mode configuration of described dispensing unit logic circuit operational mode, the operational mode includes functional mode and test pattern；
When the operational mode of operational mode configuration of described dispensing unit is functional mode, logic circuit control unit provides clock to list
Clock provided by member is sent to functional logic circuit, and closes test logic circuit；
When the operational mode of operational mode configuration of described dispensing unit is test pattern, logic circuit control unit provides clock to list
Clock provided by member is sent to test logic circuit, and closing function logic circuit.
6. mbist clock optimization method as claimed in claim 5, which is characterized in that the quantity that the clock provides unit is
Multiple, described device further includes clock selecting unit, and the clock provides unit and connect with clock selecting unit；The method packet
It includes:
Clock selecting unit provides in unit from multiple clocks selects a clock to provide unit, and according to operational mode configuration unit
The operational mode configured, by selected clock provide clock provided by unit be sent to configuration operational mode it is corresponding
Logic circuit.
7. mbist clock optimization method as claimed in claim 6, which is characterized in that multiple clocks provide unit by gradient point
The clock of the different clock frequencies indescribably supplied.
8. such as mbist clock optimization method described in claim 5 or 6, which is characterized in that the clock provides the clock of unit
Source is PLL.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101387686A (en) * | 2008-10-22 | 2009-03-18 | 炬力集成电路设计有限公司 | Apparatus and method for making system-on-a-chip into test mode |
| CN103116384A (en) * | 2013-02-01 | 2013-05-22 | 山东华芯半导体有限公司 | System on a chip (SoC) system clock control method and SoC |
| CN104950251A (en) * | 2015-07-02 | 2015-09-30 | 大唐微电子技术有限公司 | Clock network system for SOC (system on chip) chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9891279B2 (en) * | 2013-06-17 | 2018-02-13 | Stmicroelectronics International N.V. | Managing IR drop |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101387686A (en) * | 2008-10-22 | 2009-03-18 | 炬力集成电路设计有限公司 | Apparatus and method for making system-on-a-chip into test mode |
| CN103116384A (en) * | 2013-02-01 | 2013-05-22 | 山东华芯半导体有限公司 | System on a chip (SoC) system clock control method and SoC |
| CN104950251A (en) * | 2015-07-02 | 2015-09-30 | 大唐微电子技术有限公司 | Clock network system for SOC (system on chip) chip |
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Address after: 350003 building, No. 89, software Avenue, Gulou District, Fujian, Fuzhou 18, China Patentee after: Ruixin Microelectronics Co., Ltd Address before: 350003 building, No. 89, software Avenue, Gulou District, Fujian, Fuzhou 18, China Patentee before: Fuzhou Rockchips Electronics Co.,Ltd. |